JPH08221327A - Information processor - Google Patents

Abstract

PURPOSE: To provide an information processor capable of shortening read access time while suppressing the increase of design quantity of hardware. CONSTITUTION: A certain quantity of data is brought in comprehensively from main memory 3 and accumulated in cache memory 12 since much time to read in data from the main memory 3 is required. A CPU 10 efficiently reads the data by reading out sequentially from the cache memory 12. When the CPU 10 makes red access the I/O working area 4a of the main memory 3, all blocks including target data are brought in. Then, when the data in the same block is desired to make access, it is read quickly from a buffer 11 dedicated for non-cache area since the data is written in the buffer 11 dedicated for non-cache area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to a main memory which is a central processing unit (CPU) or an input / output (I).
/ O) and an information processing apparatus having a cache memory which is shared and used by a device and which is accessed by a write-back method.

[0002]

2. Description of the Related Art In an information processing apparatus that shares a main memory with a CPU or an I / O device and has a cache memory, there are a write-through method and a write-back method as a method for writing data to the cache memory.
The former write-through method is a method of writing data to the main memory when there is a write access from the CPU or I / O device, and writing data to the cache memory at least when it matches the entry address. Since access to the memory is required, the data between the main memory and the cache memory can be matched. On the other hand, all the writes will access the main memory, so access conflicts will occur and system performance will be reduced. There is a problem of causing a decrease.

On the other hand, the latter write-back method uses a CPU
When a write access is made from, the data is written only to the cache memory, so the processing is fast, but the main memory data is not updated until the cache memory is replaced. However, if the processor or I / O device accesses the same address before this update, there is a problem in that the stored contents of the cache memory may not match the stored contents of the main memory.

Therefore, conventionally, the cache memory write method is selected according to whether the cache memory is a shared area which is shared by the CPU or the I / O device of the main memory, or a non-shared area which is not shared and used. An information processing device for switching is conventionally known (Japanese Patent Laid-Open No. 2-2).
No. 26449: Title of the invention "Cache memory control system").

FIG. 2 is a block diagram showing an example of this conventional information processing apparatus. In the figure, a CPU 1, an I / O device 2,
The main memory 3, the write-through cache memory 5, and the write-back cache memory 6 are connected to each other via a bus 7. The main memory 3 has an I / O use area (shared area) 4a whose storage area is commonly used by the CPU 1 and the I / O device 2, and an I / O non-use area which is not used by the I / O device 2. (Non-shared area) 4b. The write-through cache memory 5 is a cache memory in which data is written by the write-through method, and the write-back cache memory 6 is a cache memory in which data is written by the write-back method. The I / O device 2 may be another CPU.

In this conventional device, data writing from the I / O device 2 to the main memory 3 is performed only in the I / O use area 4a. Further, when writing data from the CPU 1 to the I / O use area 4a of the main memory 2, it is necessary to match the data between the cache memory and the main memory 3. Therefore, according to the write-through method, the write-through cache memory is used. 5 and the I / O use area 4a are respectively written with data.

On the other hand, the CPU 1 to the main memory 2
At the time of write access to the I / O unused area 4b, data is normally written in the write-back cache memory 6 according to the write-back method. This allows
Unnecessary data writing to the I / O unused area 4b of the main memory 3 which is conventionally performed by the write through method can be eliminated, and data writing to the I / O used area 4a is performed by the write through method. The consistency of the data stored in the through-cache memory 5 and the main memory 3 can be maintained, so that when the CPU 1 needs the data next time and it is in the write-through cache memory 5 and hits, it is used as it is. The advantage is that the access speed is improved.

[0008]

However, in the above-mentioned conventional information processing apparatus, the write address is seen in the cache memories 5 and 6, and it is determined whether the write address is the I / O use area 4a of the main memory 3 or the I / O nonuse. A mechanism for determining whether it is the region 4b is required. Further, since the state transition of the cache memory is different between the write-back method and the write-through method, two types of cache memories, the cache memories 5 and 6, are required to realize it, which increases the hardware design amount, There is a problem that it takes time to design the hardware, the possibility of bugs increases, the number of parts increases, and the cost increases accordingly.

The present invention has been made in view of the above points,
An object of the present invention is to provide an information processing device capable of reducing read access time while suppressing an increase in the amount of hardware design.

[0010]

In order to achieve the above object, the present invention has a central processing unit connected to a cache memory via a bus, and a main memory connected via the bus to an input / output device or In an information processing apparatus configured to be shared with another central processing unit, a buffer dedicated to a non-cache area provided in the central processing unit and the central processing unit reads data from the shared area when reading data from the shared area of the main memory. To a buffer for exclusive use in the non-cache area, then when the central processing unit reads data from the same address block in the shared area, data is read from the buffer for exclusive use in the non-cache area, and when writing data to the shared area, the control means writes the data in the shared area. , Shared area of main memory from I / O device or other central processing unit A memory controller that monitors the presence / absence of access to the memory, generates an access detection signal when an access is detected, supplies the signal to a central processing unit having a non-cache area dedicated buffer, and invalidates the data in the non-cache area dedicated buffer. It is what

[0011]

According to the present invention, when the shared area of the main memory is accessed, data is written to or read from the shared area, but at the time of data read, the data read from the shared area is further written to the non-cache area dedicated buffer, and the same address after that. When reading data, the data is read from the non-cache area dedicated buffer. Therefore, in the present invention, the access to the main memory shared area can be performed without passing through the cache memory.

Particularly, when the data is read from the shared area of the main memory, the control means performs block refilling of the block containing the target data from the shared area and writes all the blocks into the non-cache area dedicated buffer at the same time. Data can be read at high speed from the non-cache area dedicated buffer at the time of address data reading.

Further, the central processing unit writes data in the cache memory according to the write-back method at the time of write access to the non-shared area of the main memory,
Processing is easy and fast.

[0014]

Next, an embodiment of the present invention will be described. FIG. 1 shows a block diagram of an embodiment of an information processing apparatus according to the present invention. In FIG. 1, the same components as those in FIG. 2 are designated by the same reference numerals. In this embodiment, the CPU 10, the I / O device 2, the cache memory 12, and the memory controller 13 are connected to each other via the bus 15, and the main memory 3 is connected to the bus 15 via the memory controller 13. There is.

In the CPU 10, a non-cache area dedicated buffer 11 such as a register having a capacity of about a block size is provided. The memory controller 13 is I /
Whether or not the O device 2 accesses the main memory 3 is monitored, and when there is an access, an I / O access signal is supplied to the CPU 10 via the signal line 14, and data in the non-cache area dedicated buffer 11 is supplied. Invalidate.

The CPU 10 reads instructions and data stored in the main memory 3 via the bus 15 and sequentially executes them. The main memory 3 stores an instruction code to be executed and data used during execution. Since it takes time for the CPU 10 to read the data from the main memory 3 in the cache memory 12, a certain amount of data is brought together from the main memory 3 and accumulated, and the efficiency can be improved by sequentially reading the data from there to the CPU 10. It is provided for the purpose of effective lead. I / O device 2 is main memory 3
Data is written in the I / O use area 4a.

Next, the operation of this embodiment will be described.
Since the CPU 10 executes the instruction, when the main memory 3 is read-accessed to obtain the data necessary for the instruction, and the data is in the I / O use area 4a of the main memory 3, the I / O access is performed in this embodiment. In order to maintain the consistency of the data, the non-cache memory access is performed without passing through the cache memory 12.

That is, when data is read from the I / O use area 4a, a reduced instruction set computer (RISC) is usually used.
You can bring only 1 word at a time, but
In this embodiment, a block containing the target data (here,
Block size is set to 16 words) and all are brought by block refill.

Since the block refill takes 16 words at a time, it takes a little longer than the one-word refill. However, when the user wants to access the data in the same block next time, the data is stored in the non-cache area dedicated buffer 11. Since it is written, it can be quickly read from the non-cache area dedicated buffer 11. In fact, data access is often done in contiguous addresses, where the first data in a 16-word block is accessed, and if all 16 words are used, the average access time per word is (block (Refilling time) / 16, which is much faster than reading one word at a time.

In this case, since the I / O use area 4a is a shared area in which the I / O device 2 and the like may also write data, the CPU 10 stores the data read into the non-cache area dedicated buffer 11. There is a possibility that the I / O device 2 writes to the same block while reading.

Therefore, in this embodiment, the memory controller 13 monitors the access from the I / O device 2 to the main memory 3, and when there is an access, the signal line 1
The I / O access signal on 4 is made active (for example, high level). When the I / O access signal goes high, the data in the main memory 3 may not be consistent, so the data in the non-cache area dedicated buffer 11 is automatically invalidated by hardware. To do.

For this invalidation, for example, an invalidation flag is provided in the block of 16 words, the invalidation flag is set when the I / O access signal becomes high level, and the CPU 10 is activated when the invalidation flag is set. Is a method of reading a block in the I / O use area 4a of the main memory 3.

When the CPU 10 detects that the I / O access signal becomes high level while the data read in the non-cache area dedicated buffer 11 is being read, the read operation is stopped. .

The I / O accessed by the I / O device 2
The block in the used area 4a may be different from the block read in the non-cache area dedicated buffer 11, and in that case, invalidation is not necessary in principle, but the simplicity of the architecture and immediate reaction This method is adopted here for the sake of sex.

In this embodiment, in order to maintain consistency with the access to the I / O use area 4a of the main memory 3 by the I / O device 2, when the CPU 10 makes a non-cache access, The speed is increased by a method of quickly reading from the dedicated buffer 11.

In the present embodiment, the CPU 10 writes data only to the I / O use area 4a of the main memory 3 at the time of write access to the I / O use area 4a of the main memory 3. Further, the CPU 10 is the I of the main memory 3.
At the time of write access to the / O unused area 4b, data is written in the cache memory 12 by the write back method.

[0027]

As described above, according to the present invention,
Since the access to the shared area of the main memory is performed without passing through the cache memory, it is only necessary to add a dedicated buffer for the non-cache area and a memory controller, which has a sufficiently smaller capacity than the write-through cache memory required by the write-through method. In addition, the amount of hardware design can be reduced and the amount of components can be reduced as compared with the conventional case, and improvement in design, cost and mounting can be realized.

Further, according to the present invention, when consecutive data of the same address in the shared area is read, the block containing the target data in the shared area is block-filled from the non-cache area dedicated buffer and all of them are read at once.
Data can be efficiently read without loss and the read access speed can be improved as compared with the case where data is read word by word over time.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional example.

[Explanation of symbols]

 2 input / output (I / O) device 3 main memory 4a I / O used area 4b I / O unused area 10 central processing unit (CPU) 11 non-cache area dedicated buffer 12 cache memory 13 memory controller 14 I / O access signal Signal line for transmission

Claims (3)

[Claims] 1. An information processing apparatus having a configuration in which a central processing unit is connected to a cache memory via a bus, and a main memory connected via the bus is shared with an input / output device or another central processing unit. A non-cache area dedicated buffer provided in the central processing unit, and when the central processing unit reads data in the shared area of the main memory, reads data from the shared area and writes the data in the non-cache area dedicated buffer, and When the central processing unit reads data from the same address block of the shared area, the data is read from the non-cache area dedicated buffer, and when the shared area is written, the control unit writes the data to the shared area, and the input / output device. Or access to the shared area of the main memory from another central processing unit. Access to the central processing unit having the non-cache area dedicated buffer by generating an access detection signal when the access is detected,
An information processing apparatus comprising: a memory controller that invalidates data in the non-cache area dedicated buffer. 2. The control means, at the time of reading data from a shared area of the main memory, block refills a block containing target data from the shared area and writes all the blocks to the non-cache area dedicated buffer at one time. The information processing apparatus according to claim 1, which is characterized in that. 3. The information processing apparatus according to claim 1, wherein the central processing unit writes data in the cache memory according to a write back method at the time of write access to a non-shared area of the main memory.