JPH08221286A - Multi-information processing system - Google Patents

Abstract

PURPOSE: To provide a multi-information processing system in which a CPU subsystem is designated in accordance with plural peripheral control units(PCU) respectively and system operation can be made flexible by making the CPU subsystem of the object of a majority decision among the CPU subsystems of redundant configuration capable of being designated arbitrarily. CONSTITUTION: The CPU to be the object of the majority decision among plural CPUs is set beforehand in an F/F group 202. During the system operation, the CPU of the object of the majority decision is operated and majority decision processed. As for the CPU other than the object of the majority decision, the CPU of an executed object is designated beforehand for every CPU in a PCU management table 259, and at the time of a DMA request from the PCU, the CPU corresponding to the PCU is determined by referring to this table, and another task is executed. Thus, a multi-task system capable of executing simultaneously plural tasks (OS) can be constructed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-information processing system, and more particularly to a multi-information processing system in which a plurality of CPUs (central processing units) are provided in a redundant configuration to improve the reliability of the entire system. Is.

[0002]

2. Description of the Related Art A conventional redundant information processing system of this type is a so-called fault tolerant computer (F
TC) system, for example, Japanese Patent Laid-Open No. 2-
202637, JP-A-3-015946,
JP-A-3-050916 and JP-A-64-046
A CPU having a redundant configuration, which is disclosed in Japanese Patent No. 844, etc.
This is a technique for improving the reliability of the entire system by taking a majority decision of a plurality of outputs (also called an information processing subsystem) and selectively adopting an output that matches the majority decision.

For example, referring to the technique disclosed in Japanese Patent Application Laid-Open No. 2-20637, FIG. 15 shows the entire system configuration, and three CPU subsystems (CPU-
a, b, c), two global memories (global memories # 1, # 2), and a plurality of I / O processors (I / O).
O processors # 1, # 2, # 3) and a plurality of I / O controllers.

Each CPU subsystem has a local memory inside, and each local memory cannot be directly accessed from other CPU subsystems. These three CPU subsystems are stored in the local memory. It has a core OS program,
The three CPU subsystems operate by independent clocks CK.

Fault tolerant is realized by causing three CPU subsystems, which originally operate independently, to perform the same operation in synchronization with each other and to majority the behavior of the CPU subsystem.

Due to this majority decision, global memory #
1 and # 2 are provided, and global memory has 3 CPs.
It is accessible from the U subsystem and page swaps to and from local memory. Specifically, the user program and data used by the user program are stored. The majority access to the global memory from the 3CPU subsystem is decided by the global memory.

Each of the two global memories has a plurality of I's.
The I / O processor is connected by a bus, and the bus between the global memory and the I / O processor is duplicated.

The DMA operation of the peripheral device (disk device under the I / O controller) is performed by the I / O processor and the I / O processor.
Only via the / O controller to global memory, no DMA operation from peripherals to each local memory in the CPU subsystem.

Each access to a register in the global memory, a register in the I / O processor, and a register in the I / O controller is performed, and these accesses are largely decided by the port circuit in the global memory. ing.

The global memory is duplicated and has a 1: 2 connection configuration with each CPU subsystem, and one is defined as "primary" and the other is defined as "backup". Writes to the global memory from the CPU subsystem are made to both, and reads from the global memory are made from the primary. At the time of reading, the backup side internally performs the read operation, but does not output the read data and returns only the status to the CPU subsystem.

The write operation from the I / O processor to the global memory is performed for both the primary and backup by using the duplicated bus. For the read operation, data from both memories is received and the data on the primary side is used.

[0012]

In the conventional example shown in FIG. 15, since a plurality of redundant CPU subsystems are always subject to majority voting, for example, the CPU subsystem subject to majority voting is arbitrarily designated. However, it is not possible to execute one common task for the majority CPU target subsystem, and to execute other tasks for the remaining CPU subsystems other than the majority target CPU, which results in flexible system operation. It has the drawback of lacking.

An object of the present invention is to allow the CPU subsystems subject to majority voting to be arbitrarily designated in advance so that CPU subsystems other than the majority voting subject can also be used for execution of other tasks, enabling flexible system operation. Is to provide a multi-information processing system.

[0014]

According to the present invention, at least three information processing subsystems in a redundant configuration,
An input / output bus, a plurality of peripheral control devices connected to the input / output bus, and a bus that is provided in common to the plurality of peripheral control devices and that connects the information processing subsystem and the input / output bus A multi-information processing system including an interface device, wherein the bus interface device is capable of pre-designating which subsystem of the information processing subsystem is to be a majority decision target;
In response to a transaction request from the peripheral control device to the information processing subsystem, the first transaction request transmission for selectively transmitting the transaction request to the information processing subsystem designated by the majority decision target designating means. Means, a majority decision means for taking a majority decision of the transaction execution result from the information processing subsystem sent in response to the transaction request by the first transaction request sending means, and the peripheral control device, A storage unit for previously designating and storing the information processing subsystem other than the majority voting target designated by the majority voting target designating unit and the transmission target from which the corresponding peripheral control unit should send the transaction request, and the peripheral control unit Transaction to Information Processing Subsystem In response to the request, the transaction request is sent to the designated information processing subsystem when the information processing subsystem corresponding to the peripheral control device that generated the transaction request by referring to the storage means is designated. And a transaction request sending means of (1).

[0015]

A bus interface unit (BIA) for connecting an input / output (IO) bus to which a plurality of peripheral control units (PCU) are commonly connected and a plurality of redundant information processing (CPU) subsystems. , Provide a majority vote function. This as majority function adds the ability to set whether to advance which CPU subsystem and majority target, to allow any to the majority target, by allocating different resources to the CPU subsystem of the outer majority target, multi OS
Can be operated.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic system block diagram of an embodiment of the present invention. In the drawing, three redundant information processing (CPU) subsystems CPU-a to c are provided, and each CPU subsystem is a processor (MPU) 1a.
To 1c, memories 2a to 2c, diagnostic processors 3a to 3c
And N triple redundancy interface units TIU # 0-a to # N-a and TIU # 0-b to #N.
-B, TIU # 0-c to # N-c. These blocks are interconnected by internal buses BUS-a-c.

Each of the TIUs # 0-a to # N-a is connected to each of the bus interface adapter devices BIA # 0 to #N via each of the interfaces TRI-INF # 0-a to # N-a. . In addition, TIU # 0-b to # N-b
Each of the bus interface adapter devices BIA # 0
#N and each interface TRI-INF # 0-b to #N
-B are connected to each other. Furthermore, TIU # 0-
Each of c to # N-c is a bus interface adapter device BIA # 0 to #N and each interface TRI-INF #.
0-c to # N-c are connected to each other.

Bus interface adapter device BIA #
Each of 0 to #N has a plurality of peripheral control units PCU under its control.
Via each IO bus (IO-BUS) # 0 to #N.

In the following description, PCU to BI
A transaction to the internal buses BUS-a to c via A and TIU is called an UP transaction, and a transaction transferred from the internal buses BUS-a to c to the PCU via TIU and BIA is called a DOWN transaction. For UP transaction, DMA read /
There are write and register read / write, and the DOWN transaction includes DMA read response and register read / write.

FIG. 2 is a circuit diagram of a specific example of the triple redundancy interface unit TIU-a to c of FIG. In FIG. 2, the TIU transfer control unit 10 is a circuit for controlling UP transactions and DOWN transactions executed by the TIU, and the register 11 is an internal bus BUS.
Register for storing the DOWN transfer command on the command line (STT) of
A circuit for receiving the address / data of the DOWN transaction on the line (SAD) and outputting it to the DOWN buffer 15, a decoder 13 for decoding the transaction command of the register 11, and a command conversion circuit 14 for the internal bus BUS of the register 11. A circuit for converting a command into an access code of the TRI interface, a buffer 15 for storing the DOWN transfer address and data of the SAD line of the internal bus BUS, and a selector 16 for the TIU.
DOW to be transferred to TRI according to an instruction from the transfer control circuit 10
Register 1 for selecting N transaction data
7 receives selector 16 and AD of TRI interface
(TAD) output circuit, conversion circuit 18 is register 1
When the register address is stored in 2, the circuit for converting the BIA or PCU number having the register from the register address, the selector 19 is the conversion circuit 18 and the register 28.
Is a circuit for selecting the execution destination of the DOWN transaction from among the above.

The register 20 receives the selector 19 and receives the DO signal.
Transaction execution destination PCU of WN transaction
A circuit for storing numbers, a parity check circuit 21 is a check circuit of the register 11, a parity check circuit 22 is a check circuit of the register 12, a parity check circuit 2
Reference numeral 3 is a check circuit of the register 17.

The register 24 is the A of the TRI interface.
A circuit that receives UP transfer transaction data on the D (TAD line)
A circuit for storing the access code of the transaction, a register 26 for receiving the register 24 and storing the address of the UP transaction, a buffer 27 for storing the transfer data of the UP transaction transferred from the TRI via the register 24, a register 28 is T
BIA or PCU requesting the UP transaction transferred from the RI interface via the register 24
It is a circuit that stores a number.

The decoder 29 is a circuit for decoding the TRI access code of the register 25, and a command conversion circuit 30.
Is a circuit that converts the TRI access code of the register 25 into a bus command, a selector 31 is a circuit that selects UP transaction data of the internal bus BUS according to an instruction from the TIU transaction control circuit 10, and a register 32 is the internal bus BUS that receives the selector 31. UP to the SAD line
The circuit for outputting transaction data and the interrupt control 33 are IOs transferred from the TRI via the register 24.
End interrupt, PCU failure notification (E1 signal) and F / F notified via F / F (flip-flop) 41
It is a circuit that receives a BIA failure notification signal (E0 signal) notified via 42 and generates a transaction interrupt on the internal bus BUS.

The selector 34 selects the UP transaction command from the command conversion circuit 30 and the interrupt control 33, and the register 35 receives the selector 34 and outputs the UP transaction command to the command (STT line) of the internal bus BUS. Circuit, the parity check circuit 36 is a check circuit of the register 32, the parity check circuit 37 is a check circuit of the register 35, the parity check circuit 38 is a check circuit of the register 24, and the register 39 is a parity check circuit 38 when a parity error occurs. The BIA or PCU number of the request source of the UP transaction of the register 28 is set as an error BIA / PC.
This is a circuit registered as a U number.

The comparator 40 has registers 28 and 39.
And a circuit for notifying the TIU transfer control 10 of the comparison result, an F / F 41 receiving a PCU failure notification (E1 signal) of the TRI interface, and an F / F 42 receiving a BIA failure notification (E0 signal) of the TRI interface. Circuit.

The F / F 43 is a circuit for receiving the DOWN transfer data valid signal output from the TIU transfer control circuit 10 and outputting it to the data valid (TADV line) of the TRI interface, and the F / F 44 is for the UP transaction on the TADV line of the TRI interface. TI on data valid signal
The circuit for notifying the U transfer control circuit 10, F / F45 is TR
After receiving the transfer permission (TGNT line) of the I interface, T
A circuit for notifying the IU transfer control circuit 10, F / F 46 is T
Upon receiving the TRI transfer request from the IU transfer control circuit 10, the transfer request (TREQ) of the TRI interface is received.
Line), the F / F 47 receives the address valid signal output from the TIU transfer control circuit 10 and receives the internal bus BU.
Circuit for outputting to S address valid line (SADS), F /
F48 is the address valid line (SADS) of the internal bus BUS
A circuit for receiving the address validity of the above DOWN transaction and notifying it to the TIU transfer control circuit 10, the F / F 49 receives the transfer permission (SGNTn) of the internal bus BUS and receives the TI.
This is a circuit for notifying the U transfer control circuit 10.

The F / F 50 is a circuit for receiving a bus transfer request output from the TIU transfer control circuit 10 and outputting it to a transfer request (SREQn) of the internal bus BUS. The F / F 51 is T
A circuit to be set when the IU transfer control 10 detects a CPU failure, an OR circuit 52 is a circuit to perform a logical sum of F / F51 and F / F55, and an F / F53 receives the output of the OR circuit 52 and disconnects the CPU to the TRI interface. (DISC signal) output circuit, F / F 54 is a circuit for receiving TRI interface CPU fault notification (CPER signal), F / F 54
/ F55 is a circuit for receiving a CPU disconnection signal notified from the DGU, an OR circuit 56 is a circuit for ORing the F / F51 and the F / F54, and an F / F57 is a CPU for the diagnostic device DGU by receiving the output of the OR circuit 56. It is a circuit that outputs a fault signal.

The F / F group 78 is composed of F / Fs which can be set by the TIU register write, and outputs the BIA common part reset signal (IOR) and the CPU port reset (MR) to the TRI. CPU port reset (MR)
With respect to, the CPU port reset signal from the DGU is received by the receiver 80, and the OR circuit 79 logically sums it with the output of the F / F group 78 and outputs to the TRI.

The drivers / receivers 58 to 65 are input / output circuits for the internal bus BUS, and the drivers / receivers 66, 67 and 80 are input / output circuits for the DGU. The drivers / receivers 68 to 77 and 81 to 82 are input / output circuits of the TRI interface.

3 and 4 are concrete circuit diagrams of the bus interface adapter BIA of FIG.
The circuit of 100c (FIG. 3) and the unification part (FIG. 4) is shown.
The triplex units 100a-100c correspond to the triple CPU subsystems CPUa-c, respectively.

3 and 4, 100a, 100b,
Reference numeral 100c denotes a CPU port unit which is connected to a TIU of 3 CPUs of BIA via a TRI interface (TRI-INF). Although not shown, 100b and 100c have the same configuration as 100a.

The register 101a is a circuit for receiving the transaction data of the DOWN transaction on the TAD line of the TRI interface, the F / F 102a is a circuit for receiving the data valid signal of the DOWN transaction on the TADV line of the TRI interface, and the register 103a is the UP of a selector 228 described later. A circuit for receiving the transaction data and outputting it on the TAD line of the TRI interface, the F / F 104a receives a data valid signal of the UP transaction of the BIA transfer control 200 via the AND circuits 204 and 112a, and outputs it to the TRI interface. / F105a receives TRI interface transfer request (TREQ) from TIU and receives TRI
A circuit for notifying the arbitration 201, the F / F 108a is a circuit for receiving the TRI transfer permission signal of the TRI arbitration 201 and outputting a TGNT signal of the TRI interface, F / F 108a.
Is a circuit that receives the CPU disconnection (DISC signal) of the TRI, and the F / F 107a notifies the TRI of the CPU failure (CPE).
It is a circuit that outputs an R signal).

Parity check circuits 109a and 110
a is a check circuit for the registers 101a and 103a, an OR circuit 111a is an F / F 107a, a parity check circuit 109a, a circuit for logically ORing an error detection signal of a parity check circuit 110a and a CPUa of a determination circuit 208 described later, and an AND circuit 112a is OR circuit 111a
And an output of an AND circuit 204 described later, the AND circuit 113a is a CP of the F / F group 202 described later.
F / F11 circuit that logically ANDs Ua output and F / F246
4a indicates the occurrence of BIA failure by the BIA of the TRI interface.
AND circuit 11 that outputs a failure notification (E0 signal)
5a is an output from the CPUa of the F / F group 202, which will be described later, and F / F2
An F / F 116a, which is a circuit for ANDing 44, is a circuit for outputting the occurrence of a PCU failure to the PCU failure notification (E1 signal) of the TRI interface.

The F / F 127a is a circuit for receiving the BIA common part reset (IOR) signal from the TRI, and the F / F 128a.
Is a circuit for receiving a CPU port reset (MR) signal from TRI. Drivers / receivers 117a to 126
Reference numerals a, 129a to 130a are input / output circuits of the TRI interface.

The BIA transfer control 200 is a circuit for controlling UP / DOWN transactions executed by the BIA, TR
The I arbitration 201 is F /
A CPU that executes a transaction by TRI in response to a TRI transfer request by the majority target CPU indicated by the F group 202 and the F / F 105a of the CPUa port unit 100a, a TRI transfer request of the CPUb port unit 100b, and a TRI transfer request of the CPUc port unit 100c. Is a circuit that arbitrates.

The F / F group 202 comprises 3-bit F / Fs, each F / F corresponding to a CPU, and a circuit showing which CPU is a majority decision target. C
A circuit which is composed of a 3-bit F / F corresponding to the PU, and which shows a CPU that executes the traction by the TRI in response to the arbitration result of the TRI arbitration 201, and the AND circuit 204 is the BIA.
It is a circuit that logically ANDs the data valid signal of the UP transaction of the transfer control 200 and the output of each CPU of the F / F group 203.

The comparator 205 is a CPUa port section 100a.
A circuit for comparing the DOWN transaction data from the register 101a of the CPUa and the DOWN transaction data of the CPUb port unit 100b, the comparator 206 is the CPUa.
DOWN transaction data of port and CPUc
A circuit for comparing the DOWN transaction data of the port unit, a comparator 207 is a circuit for comparing the DOWN transaction data of the CPUb port unit with the CPUc transaction data, and a determination circuit 208 is a transfer CPU indicated by the F / F group 203 and the comparators 205 to 207. A circuit for deciding which CPU port section the DOWN transaction data is to be selected in response to the comparison result, the selector 209 is instructed by the determination circuit 208, and the DOWN transaction data of the CPUa port section, the DOWN transaction data of the CPUb port section, and the CPUc port. DOWN
This is a circuit for selecting any of transaction data.

The register 210 receives the output of the selector 209, and is the BIA which is the execution destination of the DOWN transaction.
Alternatively, a circuit for storing the PCU number, a register 211 for receiving the output of the selector 209 and a circuit for storing the access code of the DOWN transaction, and a register 212 for receiving the output of the selector 209 and the DOWN transaction for register read / write of the BIA register or the PCU register. The register 213 is a circuit for storing the register address at the time of writing, and the register 213 is a circuit for receiving the output of the selector 209 and storing the write data at the time of register writing of the BIA register or the PCU register by the DOWN transaction.

The buffer 214 receives the output of the selector 209 and stores the DMARD data when the DOWN transaction is the DMARD response transaction. The selector 215 stores the registers 212 and 2.
13 and a circuit for selecting DOWN transaction data from the buffer 214, the register 216 receives the DOWN transaction data by receiving the selector 215.
The register 217 is a circuit for outputting on the BAD line of the bus and receiving the access code of the DOWN transaction of the register 211 and outputting it on the BAC line of the IO bus.

The decoder 218 uses the DO of the register 211.
This is a circuit for decoding the access code of the WN transaction. The decoder 219 uses the register 21 when the DOWN transaction is the read / write of the BIA register.
2 is a circuit for decoding the address 2 and the decoder 220 is D
When the OWN transaction is a PCU register read / write, the PCU number of the register 210 is decoded and I
The circuit for outputting the PCU selection signal (BSELn) on the O bus, the register 221 receives the output of the selector 209 and
This is a circuit for storing the BIA or PCU number of the request source of the error transaction for IU detection.

The register 222 is a circuit for storing the access code of the UP transaction on the BAC line of the IO bus, and the register 223 is a U on the BAD line of the IO bus.
Circuit for storing P transaction data, register 2
24 indicates that the UP transaction is DMARD / DMAWT
When the UP transaction is DMAWT, the buffer 225 receives the register 223 and stores the address of the UP transaction.
A selector 226 is a circuit for storing write data of a transaction, and a circuit for selecting read data at the time of BIA register read or PCU register read.

The register 227 receives the output of the selector 226 and stores the register read data. The selector 228 selects the transaction data of the UP transaction. The IO bus arbitration 229 outputs from the plurality of PCUs according to the instruction from the BIA transfer control 200. Circuit for arbitrating the I / O bus transfer request (BREQn) and determining the PCU that executes the UP transaction on the IO bus, the register 230 for storing the PCU number which is the arbitration result of the IO bus arbitration 229, and the decoder 231 for the register 222 The circuit that decodes the access code of the F / F232 is I
A circuit for receiving the data valid signal of the UP transaction on the BADV line of the O bus and notifying it to the BIA transfer control 200. The F / F 233 is a D output from the BIA transfer control 200.
IO upon receiving data valid signal of OWN transaction
This is a circuit for outputting on the BADV line of the bus.

The selector 234 selects from the register 210, the register 221 and the register 230 according to the instruction of the BIA transfer control circuit, the P in which the error occurred in the transaction.
The circuit for selecting the CU number, the decoder 235 is the selector 2
34 is a circuit for decoding the output of 34, and register 236 is IO
It has the maximum number of bits for the PCU that can be connected to the bus, and sets the bit corresponding to the PCU number in which the transaction has an error according to the decoding result of the decoder 235.
Circuit to output to PCU failure notification (BERRn) of bus,
The parity check circuit 237 is the check circuit of the register 211, and the parity check circuit 238 is the register 210.
Check circuit and parity check circuit 239 are the check circuit of the register 221 and the parity check circuit 240.
Is a check circuit of the register 216, a parity check circuit 241 is a check circuit of the register 217, a parity check circuit 242 is a check circuit of the register 223, a parity check circuit 243 is a check circuit of the register 222, and a parity check circuit 244 is a check circuit of the register 230. , F / F 245 is a circuit indicating that the BIA transfer control 200 has detected a PCU failure, and F / F 246 is a circuit indicating that the BIA transfer control 200 has detected a BIA failure.

The OR circuit 257 receives the BIA common block reset (IOR) received by the CPU port block and the F / F 127.
It is a circuit that logically sums the outputs of a, 127b, 127c. The output of the OR circuit 257 is output to the bus reset signal (BRST) of the IO bus. Driver / Receiver 24
7 to 256 and 258 are IO bus input / output circuits.

The operation will be described below. First, the transaction operation of the internal bus BUS, TRI-INF
The transaction operation of (1) and the transaction operation of IO-BUS will be described.

The transaction operation of the internal bus BUS is performed according to the timing shown in FIG. In FIG. 5, a bus request line SREQn is a bus request signal line when the TIU executes an UP transaction, and is output to a bus master (not shown) to allow the bus grant SGNT.
This SREQn is output until n is received. The bus permission line SGNTn is a transfer permission signal from the bus master for the TIU bus request.

The address valid line SADS is a signal indicating the start of a transaction. The TIU outputs this signal in the UP transaction and the bus master outputs it in the DOWN transaction. The command line STT is a signal indicating the type and data length of the bus transaction, is output at the SADS output timing, and is composed of the commands shown in FIG. Address data line SAD
Outputs transaction address and data 4
This is a byte-wide bus signal.

SREQn is the output of the F / F 50 in FIG. 2, S
GNTn corresponds to the input of the F / F 49, SADS corresponds to the output of the F / F 47 and the input of the F / F 48, STT corresponds to the output of the register 35 and the input of the register 11, and SAD corresponds to the output of the register 32 and the input of the register 12, respectively.

TRI interface (TRI-INF)
The transaction operation is performed according to the timing shown in FIG. In FIG. 6, the transfer request line TREQ
Is the TR of the DOWN transaction output by TIU
This is an I transfer request. The TIU outputs TREQ until the DOWN transaction is completed. The transfer permission line TGNT is a transfer permission signal from the BIA in response to a TIU transfer request. The BIA, once outputting TGNT, continues to output TGNT while the TREQ signal is being output.

The data valid line TADV is a signal indicating that transaction data is being output to the address data line TAD. The BIA outputs this signal at the time of UP transaction, and the TIU at the time of DOWN transaction.
Will output. Address data line TAD outputs transaction access code, address and data 4
This is a bite signal line. FIG. 7 shows a data format transferred on the TAD line.

In FIG. 7, W0 is a format common to all transactions executed by TRI-INF, and consists of transaction access code, transaction information, and error transaction information. The access code field consists of the transaction command shown in FIG. The transaction information field is a field indicating the BIA or PCU number of the transaction request source or execution destination, and stores the UP transaction transaction request source and the DOWN transaction transaction execution destination. The error transaction information field stores the request source of the failed transaction when the TIU detects the failure of the UP transaction.

W1 stores access or data according to a transaction. For DMA read and DMA write transactions, DMA address (memory address), for register read and register write,
Register address is entered. After W2, transfer data is stored according to the transfer data length.

2 is the output of the F / F 46 of FIG. 2 and the input of the F / F 105a of FIG. 3, TGNT is the input of the F / F 45 and the output of the F / F 106a of FIG. 3, and TADV is the output of the F / F 44 of FIG. , F / F 43 input and F / F of FIG.
The output of 104a, the input of F / F 102a, and TAD are shown in FIG.
3 corresponds to the output of the register 17, the input of the register 24, the output of the register 103a in FIG. 3, and the input of the register 101a.

TRI transactions are classified as follows according to the majority decision bits of the BIA (bits of the F / F group 202 of FIG. 4).

CPU subject to majority decision (bit ON of F / F group 202): At the time of UP transaction, BIA simultaneously executes transactions to the target CPU. DOWN
At the time of a transaction, when the number of target CPUs is 3, the majority of transactions is compared, and when the number of transactions is 2, the transaction of one CPU is compared; when the number of CPUs is one, the transaction of this one CPU is executed;

The above is exclusive, and transactions to different CPUs are also executed. These transfer arbitrations are performed by the BIA TRI arbitration circuit 201.
It is realized by the arbitration logic shown in FIG. The transaction determination of the DOWN transaction is performed by the BIA determination circuit 2
At 08, the logic shown in FIG. 12 is executed.

The TRI arbitration circuit 201 is a circuit that determines which CPU subsystem's TIU port a TRI transaction is executed on. Transfer destination C of UP transaction depending on direction of TRI transaction
There are a PU subsystem determination method and a DOWN transaction transfer source CPU subsystem determination method. In either case, the transfer C is performed according to the instruction from the BIA transfer control 200.
Determine the PU subsystem and transfer to the F / F group 203
Set the bit corresponding to the source CPU subsystem.

When determining the transfer destination CPU subsystem of the UP transaction, the F / F group 202 is referred to.
Each bit of the F / F group 202 is a bit indicating whether or not each of the 3 CPU subsystems is a majority voting (VOTING) target, and the CPU subsystem in which this bit (hereinafter referred to as VOTING bit) is set is operating the system. Is shown. TRI arbitration circuit 201
F / F when instructed to arbitrate UP transaction
CP with group 202 VOTING bit set
With U as the transfer destination, the corresponding bit of the F / F group 203 is set.

Source CPU of DOWN transaction
When determining the subsystem, the VOT of the F / F group 202
ING bit and each CPU port unit 100a, 100b,
The transfer source CPU subsystem is determined by referring to the transfer request (TREQ) of the TIU DOWN transaction notified via 100c, and the corresponding bit of the F / F group 203 is set.

Further, the TRI arbitration 201 sets the F / F group 203 and at the same time outputs the transfer permission to the CPU port unit (any one of 100a, 100b and 100c) connected to the transfer source CPU subsystem, and the corresponding CPU port unit. Transfer permission signal (TGN) to the transfer source CPU subsystem via the F / F (one of 106a, 106b, and 106c) of
T) is returned.

The transfer source CPU subsystem decision logic at the time of this DOWN transaction is shown in FIG. "Dc" in FIG. 11 is an abbreviation for don't care, which means that either 0 or 1 may be used. This FIG.
Consists of the following logic.

The DOWN transfer request from the VOTNG target CPU subsystem is a CP for all VOTING targets.
Accepting requests from U subsystems at the same time and permitting transfer; DOW from non-VOTING CPU subsystems
N transfer requests must be individually accepted for each CPU subsystem to allow transfer; When individually accepting transfer requests from VOTING non-target CPUs, the acceptance priority is set to CPUa, CPUb,
In order of CPUc.

All the CPs are numbered from 1 to 3 in FIG.
Each CPU when the U subsystem is not subject to VOTING
This is when there is a DOWN transaction transfer request from the subsystem. For example, when all the bits of the F / F group 202 are not set and the transfer request (TREQ) of the CPUa subsystem is received via the F / F 105a (item No. 1), the CPUb subsystem and the CPUc subsystem are F / F group 20 regardless of request
CPUa subsystem corresponding bit of 3 is set, and the transfer enable signal (TGNT) is sent to the CPU via the F / F 106a.
Notify the TIU of subsystem a.

Item Nos. 4 to 12 are cases in which one CPU subsystem is a VOTING target, and a DOWN transfer request is received from each CPU subsystem during system operation. No. 4 to No. 6 are C
When the PUa subsystem is operating as a VOTING target and the system is operating, items Nos. 7 to 9 are number 1 when the CPUb subsystem is operating as a VOTING target.
From 0 to No. 12, the CPUc subsystem is VOTI
This is the case when the system is being operated with NG targets.

In these cases, if there is a transfer request from the VOTING target CPU subsystem, VOTI
The request of the VOTING target CPU subsystem is preferentially accepted regardless of whether there is a transfer request from the NG non-target CPU subsystem (item number 4, item number 7 and item number 10).

No. 13 to No. 18 are two CPUs
This shows a case where the subsystem is a VOTING target and a transfer request is received from each CPU subsystem during system operation. No. 13 and No. 14 are CPUs
a subsystem and CPUb subsystem are VOTIN
When the system is in operation for G target, Item No. 15 and Item No. 16
Is the CPUb subsystem and the CPUc subsystem is V
This is a case where the system is being operated for the OTING target and item numbers 17 and 18 are being operated for the CPUa subsystem and the CPUc subsystem VOTING target.

In these cases, the VOTING target CPU
If there is a transfer request from the subsystem, VOT
The request from the ING target CPU is preferentially accepted (item number 13, item number 15 and item number 17). No. 19 is all C
This is a case where the PU subsystem is operating as a VOTING target. All the VOTING target CPU subsystems are designated simultaneously as the transfer source CPU subsystem, and the transfer permission is returned.

During normal system operation, all CPU subsystems are VOTING targets. Therefore, the logic shown in item No. 19 operates. The BIA sends a transfer request (TREQ) from the 3CPU subsystem to the F / F 105a, 105b,
The signal is received by 105c and input to the TRI arbitration circuit 201.
At this time, all bits are set in the F / F group 202.
In the TRI arbitration circuit 201, all bits of the F / F group 202 are set and there are transfer requests from three CPUs. Therefore, all bits of the F / F group 203 are set and 3 CPUs are set.
Designate the subsystem as the source CPU subsystem.
It also outputs a transfer permission signal to the CPU port units 100a, 100b, 100c.

Each CPU port unit transfers the transfer permission to the F / F10.
6a, 106b and 106c receive and output to the transfer permission signal line (TGNT) of the TRI interface. The TIU receiving the transfer permission (TGNT) starts a DONW transaction. As shown in FIG. 6, the TGNT line continues to be output until the TIU completes the transfer of transaction data and invalidates the transfer request line (TREQ).

Since the TRI arbitration circuit 201 simultaneously notifies the 3CPU subsystem of transfer permission (TGNT), the 3C
At the same time, the TIU of the PU subsystem can start the DOWN transaction with the transfer permission of the BIA.

BIA is each CPU port unit 100a, 10
0b and 100c TRI interface data lines (TA
D) TRI DOWN transaction data (FIG. 7) received by the input registers 101a, 101b, 101c.
Format) and TRI interface data valid line (TAD
V) is received by the F / Fs 102a, 102b, 102c and a majority decision is made.

This majority decision is performed by comparators 205 and 20 for comparing transaction data between the two CPU subsystems.
6,207 and the determination circuit 208 that determines one of the CPUs based on the comparison result and the CPU designated by the determination result
It comprises a selection circuit 209 for selecting DOWN transaction data of a port. Comparator 205 is CPUa
Comparator for DOWN transaction data of subsystem and CPUb subsystem, comparator 206 is comparator for CPUa subsystem and CPUc subsystem, comparator 2
Reference numeral 07 is a comparator for the CPUb subsystem and the CPUc subsystem.

The determination circuit 208 selects the data of the CPU that was in agreement with the majority result, and the CP that is not in agreement with the majority result.
It has a function of detecting U as a failure, and this decision logic is shown in FIG. Item number 1 to item number 3 in FIG. 12 are the judgment logic when the DOWN transaction is received from the 1CPU subsystem. Since only one CPU subsystem is executing the transfer operation, the comparators 205, 206, 207
The transfer source CPU subsystem shown in the F / F group 203 is always selected regardless of the result of the comparison. The comparison result is meaningless, and the determination circuit 208 does not detect a failure.

Item numbers 4 to 9 in FIG. 12 are cases where the DOWN transaction is simultaneously received from the 2CPU subsystem. Since the TIU of the 2CPU subsystem receives the transfer permission at the same time, the DOWN transaction data is transferred to the BIA at the same time.

Therefore, the 2C which is allowed to transfer in the F / F group 203
The transaction data from the PU is compared with the corresponding comparator. If they match each other, it is determined that the CPU is operating normally, and the CPU subsystems set in the F / F group 203 have a smaller CPU number (CPUa, CPUb,
Then, the selection circuit 209 selects the transaction data. If the comparison results do not match,
The two CPUs are doing different things and one of them is the fault. However, since it cannot be determined which one is the failure, it is detected as a BIA failure. This failure can be a BIA failure or a PCU failure.

Item numbers 10 to 17 are cases in which DOWN transactions are simultaneously received from the 3CPU subsystem. Similar to the case where the transfer is permitted to the 2CPU subsystem, the 3CPU subsystem simultaneously transfers the transaction data in the format of FIG. 7 to the BIA. If the comparison results are all the same, item number 10; if one comparison result is the item number 11 to item number 13, if the two comparison results are the item number 14 to item number 16, all do not match No. 17 is the case.

The three comparators 205, 206 and 207 are redundant, and when one of the three CPUs fails, a different operation is executed and the DO from that CPU subsystem is executed.
If the WN transaction data is different from the others, its C
Two comparators that use the PU subsystem as a comparison input detect a mismatch, and only one comparator that does not compare the failed CPU subsystem will compare and match.

When only one comparison result matches as shown in item number 11 to item 13 in FIG. 12, the determination circuit 208 determines the smallest C among the two CPU subsystems that have been compared and matched.
The PU subsystem number is output to the selection circuit 209, and the CPU subsystem of the inputs common to the two comparators that do not match at the same time is detected as the faulty CPU subsystem.

The phenomenon that the two comparison results of item Nos. 14 to 16 match and the phenomenon that all the comparison results of item No. 17 do not match cannot occur due to one CPU failure, and are inconsistent. It is judged that this is a failure of the comparator, and BI
Detect A failure.

Usually all 3 CPU subsystems are VOTI
When it is an NG target, the BIA sends transaction data sequentially transferred in the format of FIG.
0a, 100b, 100c TRI interface data line (TAD) input registers 101a, 101b, 1
01c to accept TRI interface data valid line (TADV) F / Fs 102a, 102b, 1
Simultaneously with 02c, the comparators 205, 206 and 207 compare. The determination circuit 208 determines the comparison result, and the selection circuit 209 selects the transaction data. The selected data is stored in the registers 210, 211, 212, 213, 221 and the buffer 214 according to the type and timing of the transaction.

When only one of the comparison results matches, for example, the DOWN of the CPUa subsystem of item 11 in FIG.
A case will be described where a comparator that receives transaction data detects a mismatch. At this time, the determination circuit 20
8 is a selection circuit 209 for selecting the CPUb subsystem
To the CPUa subsystem failure. This fault output is the OR circuit 11 of the CPUa port unit 100a.
F / F 107a is set via 1a, and CP is used as the CPU fault notification signal (CPER) of the TRI interface.
The TIU of the Ua subsystem is notified.

Next, the IO-BUS transaction operation will be described. FIG. 10 is a diagram showing an example of the operation timing of the IO bus transaction. In FIG. 10, the bus request line (BREQn) is an IO output from the PCU.
This is a bus request for a bus UP transaction.
The PUC outputs BREQn until the UP transaction of the IO bus is completed. The bus permission line (BGNTn) is a transfer permission signal from the BIA for the IO bus request of the PCU. Once the BIA outputs the BGNTn signal, it continues to output the BGNTn signal while the BREQn signal is being output.

The data valid line (BADV) is a bus signal indicating that transaction data is being output to the address data line (BAD). PCU outputs at UP transaction, BI at DOWN transaction
A outputs. The access code line (BAC) is a bus signal line that outputs an access code for a transaction. The format of the access code is the same as the access code of the TRI interface. Address data line (BA
D) is a 4-byte bus signal line for outputting a transaction address and data.

BREQn is an input signal via the receiver 253 to the IO bus arbitration 229 of FIG. 4, an output signal from the IO bus arbitration 229 of BGNTn via the driver 254, and BA.
DV is F / F233 output and F / F232 input, B of FIG.
AD corresponds to the output of the register 216 and the input of the register 223.

The operation at system startup will be described. When the system is started up, the VOTING bit of the BIA (F / F group 202 in FIG. 4) is in the initial state, and all 3 CPUs are not subject to the majority vote (VOTING). Each C
Processors 1a to 1c of the PU subsystems CPUa to c
F / by register write of BIA via each TIU
The bit corresponding to the own CPU of the F group 202 is set.
After the setting of the F / F group 202 is completed, the BIA starts the majority voting operation and becomes the system operation operation.

The VOTING bit is an F / F group which is initialized when the power of the IO chassis is turned on, and is the CPU of the BIA.
Not initialized by port reset and BIA common block reset.

The operation during system operation will be described.
During system operation, each processor executes a PCU register read / register write issued for IO startup and termination processing and a DMA read / write from the PCU during the IO operation.

The DMA read / write operation from the PCU will be described. In FIG. 4, when the IO bus arbitration unit 229 receives a DMA read / write transfer request from the PCU via the BREQn line of the IO bus, the BIA transfer control 20
0 indicates arbitration of the IO bus and at the same time TRI arbitration 20
1 to instruct the arbitration of the TIU UP transaction.
The IO bus arbitration 229 stores the PCU number that uses the IO bus in the register 230, and returns a transfer permission (BGNTn) to the corresponding PCU. TRI arbitration 201 is F / F group 2
The CPU set as the majority target in 02 is the transfer destination CP
Select U and set the corresponding bit of the F / F group 203.

The PCU (not shown) which has received the transfer permission by the BGNTn signal has the data valid signal on the BADV line, the access code on the BAC line, and the DMA on the BAD line as described above.
It outputs the address. BAD for DMA write
DMA write data is continuously transferred on the line. F / F
When a data valid signal is received at 232, an access code is received at register 222, and a DMA address is received at register 223, B
The IA transfer control 200 causes the decoder 231 to decode the access code of the register 222. When it is found from the decoding result that the transaction is a DMA transaction, the DMA address of the register 223 is stored in the register 224.

In the case of DMA write, subsequent DMA write data is received by the register 223 and sequentially stored in the buffer 225. The BIA transfer control 200 selects TIU UP transaction data by the selector 228, and AN
The data valid signal of the TIU UP transaction is output to the D circuit 204. In the AND circuit 204, the F / F group 2
03, the output for the CPU designated as the transfer destination becomes valid, and as a result, the register 103 of the transfer destination CPU
W of UP transaction from a, 103b, 103c
A valid signal is output to the TIU from the 0 data, F / F 104a, 104b, 104c.

In the selector 228, the access code of the register 224 when the data is W0, the DMA request source PCU number of the register 230, and the DM of the register 224 when the data is W1.
DM of buffer 225 when address A, data W2 or later
A write data is sequentially selected.

The register read / register write operation of the PCU will be described. In FIG. 4, C shown in FIG.
F / F 105a, 105 of PUa, CPUb, CPUc
When the TRI arbitration 201 receives a TRI transfer request (TREQ) for register read / register write from the TIU via the b and 105c, the BIA transfer control 200 instructs the TRI arbitration 201 to arbitrate the DOWN transaction.

The TRI arbitration 201 refers to the F / F group 202, stores the CPU for TRI transfer in the F / F group 203,
Transfer permission (TGNT) is returned to the corresponding CPU. TGN
The TIU which has received the transfer permission by the T signal transmits the data valid signal on the TADV line and the data W on the TAD line as described above.
0 (access code) and W1 (register address) are sequentially output.

In the case of register write, data W2 (register write data) is continuously output on the TAD line.
When the F / Fs 102a, 102b, 102c receive the data valid signal and the registers 101a, 101b, 101c receive the access code, the BIA transfer control 200 determines the decision circuit 2.
At 08, a majority decision is made. The determination circuit 208 refers to the comparison results of the F / F group 203 and the comparators 205, 206 and 207, and uses the selector 209 to CPUa, CPUb and C.
Select data from any of PUc.

When the data W0 is selected, the access code field portion is stored in the register 211, the transaction field portion is stored in the register 210, and the decoder 2
The access code is decoded by 18. If it is found from the decoding result that register read / register write, the register address of W1 is sent to the register 212,
The register write data of W2 is stored in the register 213.

Further, the access code of the register 221 is sent to the register 217 and the register 212 via the selector 215.
The register address of the above is stored in the register 216. The PCU selection signal (BSELn) is output to the register read / register write destination PCU according to the decoding result of the transaction information of the decoder 220, and the IO bus operation is started. In the case of register write, the BIA transfer control 200 subsequently selects the register 213 by the selector 215, and transfers the register write data from the register 216 to the BA of the IO bus.
Output on line D.

The operation when a failure occurs will be described. Faults can be classified into three categories: CPU faults, BIA faults, and PCU faults. First, the CPU failure will be described.

In FIGS. 3 and 4, the CP is activated during system operation.
When the following failure, which is a failure closed to U (a CPU closed failure is a failure in which the failure location that causes the failure affects only the operation of the CPU), is detected, the F / F
108a is set and a CPU fault notification (CPER) signal is output. Further, the VOTING bit of the F / F group 202 is reset.

CPU failure factors include: failure of register 101a for storing input data of TAD line of DOWN transaction (detected by parity check circuit 109a); CPU data compare error failure detected by decision circuit 208; TIU to F / F108a CPU disconnection notification (DISC signal) detection; TIU detection failure and D
The DISC signal is notified by the CPU disconnection instruction from the GU. However, the TRI interface reception register failure detected by the parity check circuit 38 of FIG. 2 is excluded.

If the BIA detects a CPU failure, then AN
TADV of UP transaction by D circuit 112a
Mask the UP transaction by disabling the signal. Further, the AND circuit 127a invalidates the TRI transfer request, and TR of the DOWN transaction
The faulty CPU is not allowed to participate in the I arbitration 201.

The CPU fault notification (CPER) is notified to the DGU via the TIU. The DGU that has received the notification of the CPU failure sends the CPU disconnection signal to all TIs to notify the other BIA in the system that the CPU failure has occurred.
Notify U's F / F 55. The TIU notifies the BIA of the CPU disconnection signal of the TRI via the F / F 53. The diagnostic processor DGU resets the CPU port of the BIA and clears the CPU port fault in the CPU incorporation process. After that, the VOTIN of the F / F group 202 from the MPU
Set the G bit again and incorporate the CPU.

The BIA failure will be described. BIA failure includes a failure detected by BIA and a failure detected by TIU. The BIA disorders detected by BIA are as follows.

If the BIA transfer control 200 detects the following fault during operation in FIGS.
/ F246 is set and the BIA fault is notified to the TIU by the E0 signal line of the TRI interface. When the F / F 246 is set, the BIA transfer control 200 stops the IO bus operation and stops accepting DMA from the PCU. BI
Factors A are as follows.

Failure occurrence of register 210 storing transaction information of DOWN transaction (detected by parity check circuit 238); Failure occurrence of register 221 storing failure information of TIU detection (parity check circuit 239)
(Detected by the parity check circuit 244); Failure of the register 230 that stores the PCU number of the UP transaction (detected by the parity check circuit 244);
Register 211 that stores the access code of the DOWN transaction
Failure occurrence (detected by the parity check circuit 237); the failure transaction information in the register 221 is B
If it shows an IA transaction;
Is a case where the request source or execution destination PCU of an invalid transaction due to a failure cannot be identified. ,
Is a BIA transaction, so it is a case where a failure of a specific PCU cannot be made.

In FIG. 2, the TIU is set to B by the E0 signal.
When the IA failure is received by the interrupt control 33, DMA is sent to a predetermined address (for example, 0x1E000000).
An interrupt is notified to the MPU by executing a write. The MPU that has received the notification of the failure resets the BIA common part, and thus resets the TIU (register 78).
Register write. The TIU notifies the BIA of the BIA common part reset signal (IOR) of the TRI.

In FIGS. 3 and 4, the BIA that has received the BIA common section reset is the CPU port section 100a, 100b,
All parts except 100c and the F / F group 202 are initialized, and a bus reset signal (BRST) is output to the IO bus. 3 CPUs because the F / F group 202 is not reset
Remains a majority vote. F / F246 is cleared by the BIA common part reset, and 3 after the reset is released.
Operate the system in a CPU-synchronized state.

In the BIA failure detected by TIU,
In FIG. 2, when a failure occurs in the TAD line input register 24 of the TRI, the transfer control 10 writes the transaction information of the UP transaction stored in the register 28 to the failed transaction information register 39. Further, when transferring the DOWN transaction to the BIA, the contents of the register 39 are transferred as fault transaction information. Further, the result of decoding the access code of the register 25 by the decoder 29 during the UP transaction is a DMA transaction, and the register 2
When the comparison result of the comparator 40 between the transaction information of 8 and the faulty transaction information of the register 39 matches, the SREQ signal is not output and this DMA transaction is not executed.

In FIGS. 3 and 4, the failure transaction information transferred to the BIA is majority-determined by the decision circuit 208 and stored in the register 221 via the selector 209.
When the failed transaction information is BIA, the BIA transfer control 200 detects the BIA failure. Subsequent operations are BIA
This is the same as the BIA failure of detection. Before writing the TIU reset register 78 register to reset the BIA common part, the MPU clears the TIU fault transaction information register 39 by register write.

The PCU failure will be described. The PCU failure includes a failure detected by BIA and a failure detected by TIU.

In the case of a PCU fault detected by the BIA, if the BIA transfer control 200 detects the following fault during operation in FIGS. 3 and 4, the F / F 245 is set as a PCU fault and the E1 signal line of the TRI interface is used. Notify the TIU of the PCU failure. The PCU failure factors are as follows.

IO bus access code (BAC) input / output registers (register 217 and register 222)
Failure occurrence (parity check circuits 241 and 243 detect failure); failure occurrence of IO bus address data line (BAD) input / output register (register 216 and register 223) (parity check circuits 240 and 242 detect failure); When the transaction information in the register 210 indicates a PCU transaction, a fault occurs in the register 211 that stores the access code of the DOWN transaction (detected by the parity check circuit 237); the fault transaction information in the register 221 is P.
When showing a transaction of a CU.

The BIA transfer control 200 uses the register 210,
The PCU number stored in the register 221 or the register 230 is registered as a faulty PCU in the PCU fault identification register 236 via the selector 234 and the decoder 235. The register 236 has a bit corresponding to the PCU, and the PCU registered in the register 236 has the I bit.
PC of IO bus when executing O bus transaction
The U fault notification line (BERRn) notifies the PCU of the fault.

In FIG. 2, the TIU is set to P by the E1 signal.
When the interrupt control 33 receives a CU failure, DMA to a predetermined address (eg, 0x1E000000)
The processor is notified of the PCU failure by performing a write.

The processor notified of the fault is the faulty PC.
In order to identify U, the BIA PCU failure identification register 236 is read by register read. Processor is BI
The fault identification register 236 of A is cleared by register write. Further, register writing to the faulty PCU is performed to initialize the PCU, and PCU fault handling is performed.

The PCU fault detected by the TIU is the fault of the TAD line input register 24 of the same TRI as the BIA fault. The difference from the BIA failure is that the failed UP transaction request source is the PCU and the PCU number is stored in the transaction information register 28. The operation of TIU is the same as that at the time of BIA failure.
PC for failure transaction information of N transaction
Notify the BIA with the U number. DMA from PCU registered in fault transaction information register 39
Discard the DMA transaction in the TIU when it receives the transaction. The BIA detects a PCU failure when the PCU number is set in the failure transaction information register 221. Subsequent BIA operations are BIA-detected PCUs.
Same as a disability.

The processor notified of the fault is the faulty PC.
In order to identify U, the BIA PCU failure identification register 236 is read by register read. Processor BIA
The fault identification register 236 of the above and the fault transaction information register 28 of the TIU are cleared by register writing. Further, register writing to the faulty PCU is performed to initialize the PCU, and fault handling of the PCU is performed.

13 and 14 are diagrams for explaining the details of the embodiment of the present invention. FIG. 13 shows the TR shown in FIG.
FIG. 6 is a diagram showing a portion of the I arbitration 201 according to an embodiment of the present invention and a peripheral circuit (BIA internal circuit).

In the figure, the TRI arbitration 201 is shown in FIG.
TRI arbitration body 261 for executing the arbitration logic shown in FIG.
And a PCU management table (memory table) that specifies and stores the numbers of CPU subsystems that should execute UP transactions corresponding to each of a plurality of PCUs.
259, and a selector 260 that selectively sets the output from the PCU management table 259 and the arbitration result output from the TRI arbitration main unit 261 to the F / F group 203.

FIG. 14 shows an example of the contents of the PCU management table 259, showing that when the bit "1" is set, DMA transfer which is an UP transaction is performed to the corresponding CPU subsystem. Cage,
"0" indicates that DMA transfer is not performed. Note that a DMA transfer request cannot be issued to a CPU subsystem that is actually operating while being designated as a majority voting target in the F / F group 202 for designating a majority voting target. Only PC
In the U management table 259, "1" is set.

In such a structure, the DOWN transaction request TREQ is sent from the TRI interface (TRI-INF) to the BIA by the three CPU port units 100.
When received by any of a, 100b, 100c, TR
The I arbitration 201 notifies the BIA transfer control 200. BI
The A transfer control 200 instructs the TRI arbitration 201 to arbitrate the DOWN transaction. TRI mediation 201 is F /
The CPU subsystem of the F group 202 subject to the majority decision is read out to carry out the arbitration shown in FIG. Then, under the control of the BIA transfer control 200, the DOWN transaction is received from the TRI interface, and the above-described operation during operation is executed.

When making a DMA request which is an UP transaction from the PCU, it is assumed that the IO bus arbitration 229 receives a DMA request BREQn from PCUn, for example. The IO bus arbitration 229 arbitrates the IO bus transfer request, outputs the transfer PCU number of the arbitration result to the register 230, and notifies the BIA transfer control 200 of the DMA request.

When performing DMA, the BIA transfer control 200
Returns a transfer permission to the IO bus arbitration 229. At this time, BI
The A transfer control 200 uses the PC stored in the register 230 to determine the DMA transfer destination CPU subsystem.
The PCU management table 259 in the TRI arbitration 201 is referred to by the U number. This reference result is set in the F / F group 203 via the selector 260. The transfer destination CPU in this case is the CPU c.

Thereafter, the BIA transfer control 200 executes the IO bus protocol and sends the DMA command to the register 222,
The register 224 receives the DMA address and the buffer 225 receives the DMA data, and the selector 228 and the transfer destination CP
The DMA transaction data is sent to the CPUc via the output register 103c of the CPU port unit 100c connected to the U subsystem.

If the UP transaction is a DMA read, the read response, which is the DMA read result of the CPUc, is sent from the CPUc as a DOWN transaction. In this case, the DOWN transaction request is sent by the TRI arbitration 201 in FIG. Arbitration is performed according to the arbitration logic shown in. In this arbitration logic, CPUc
Only the DMA read response is sent back to the PCUn that issued the DMA read request.

By doing this, CPs not subject to majority voting
Since the DMA operation can be performed also on the U subsystem, for example, when a failure occurs in the CPU subsystem and the failure CPU subsystem is excluded from the majority decision, information on the failure CPU subsystem (memory etc. (Memorized information)
Can be output to peripheral devices (disk, printer, etc.).

The fact that the transaction transfer destination CPU subsystem can be specified by the contents of the PCU management table 259 means that, for example, all of the CPUa to CPUc are excluded from the majority decision, and different OSs are run on each CPU subsystem. It is also possible to allocate a PCU and a peripheral device for each OS (for each CPU subsystem) and divide and operate a plurality of peripheral devices on the same IO bus in a multi-system.

[0128]

As described above in detail, according to the present invention, C
Since the majority function of the PU subsystem is provided in the bus interface adapter device so that the designation of the majority object can be set as desired, the CPU subsystem can be effectively used and resources can be freely allocated to each PCU. , System flexibility by enabling multi-OS operation,
There is an effect that versatility can be achieved.

Bus interface adapter device (BI
In A), when a CPU failure is detected, its CP
It is possible to release U from the majority decision and disconnect it from system operation. In case of failure of BIA itself, instead of disconnecting BIA from the system as in the past, reset the register group in BIA and retry. Let's do the processing. Furthermore, it is reported as a failure of the request source or execution destination PCU of the transaction which is illegal due to the failure, and the PC
Retry processing is performed only for U. This allows BI
There is also an effect that the failure processing time for the failure of A can be shortened.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

2 is a circuit diagram of a specific example of a TIU (triple redundancy interface unit) of the block of FIG.

3 is a specific example circuit diagram of a triple part of a BIA (bus interface adapter device) of the block of FIG.

FIG. 4 is a circuit diagram of a specific example of a single part of BIA.

FIG. 5 is a time chart showing the operation of the internal bus BUS according to the embodiment of the present invention.

FIG. 6 is a time chart showing a TRI interface operation.

FIG. 7 is a diagram showing a data format of a TRI interface.

FIG. 8 is a diagram showing a command format of an internal bus BUS.

FIG. 9A is a TRI access code field,
(B) is a figure which shows a transaction information field, (c) is a figure which shows a failure transaction information field, respectively.

FIG. 10 is a time chart showing the operation of the IO bus.

11 is a diagram showing arbitration logic of the TRI arbitration circuit 201. FIG.

12 is a diagram showing a decision logic of the decision circuit 208. FIG.

FIG. 13 is a diagram for explaining an example of the present invention,
5 is a block diagram of a portion of TRI arbitration 201 of FIG. 4 according to an embodiment of the present invention and a peripheral circuit thereof. FIG.

14 is a diagram showing an example of a PCU management table in FIG.

FIG. 15 is a system block diagram of a conventional fault tolerant system.

[Explanation of symbols]

CPU-a to c Information processing subsystem TIU # 0-a to TIU # N-a Triple redundancy interface unit BIA # 0 to BIA # N Bus interface adapter device PCU peripheral controller BUS-a Internal bus IO-BUS # 0 #N IO bus 1a Processor (MPU) 2a Memory 3a DGU 200 BIA transfer control unit 201 TRI arbitration unit 202 Majority target designation F / F group 203 TRI arbitration F / F group 259 PCU management table 260 Selector

Claims (6)

[Claims] 1. A redundant information processing subsystem, at least three information processing subsystems, an input / output bus, a plurality of peripheral control devices connected to the input / output bus, and a common peripheral control device. A multi-information processing system including a bus interface device that is provided and connects between the information processing subsystem and the input / output bus, wherein the bus interface device determines which subsystem of the information processing subsystem is majority. A majority decision designating unit capable of designating whether to be a target in advance, and selecting from the information processing subsystem designated by the majority decision target designating unit in response to a transaction request from the peripheral control device to the information processing subsystem. First transaction request sending means for sending the transaction request, and the first transaction request A majority decision means for taking a majority decision of the transaction execution result from the information processing subsystem sent in response to the transaction request by the request request sending means, and the majority decision target designating means corresponding to each of the peripheral control devices. A storage unit for pre-designating and storing the information processing subsystem other than the designated majority vote and for which a transaction request is to be transmitted from the corresponding peripheral control apparatus; and a storage unit from the peripheral control apparatus to the information processing subsystem. In response to the transaction request, when the information processing subsystem corresponding to the peripheral control device that generated the transaction request by referring to the storage means is designated, the transaction request is sent to the designated information processing subsystem. And a transaction request sending means of 2. Multi-information processing system according to claim. 2. The majority voting means is further configured to majority vote a transaction request from the information processing subsystem designated by the majority voting target designating means to the peripheral control device. The described multi-information processing system. 3. The bus interface device further sends a transaction execution result from the information processing subsystem, which is sent in response to a sending transaction request by the second transaction request sending means, to the requesting peripheral control device. The multi-information processing system according to claim 1 or 2, further comprising: 4. The bus interface device further comprises means for externally reporting, as a faulty subsystem, an information processing subsystem that has sent a transaction execution result or a transaction request different from the majority voting result by the majority voting means, and responds to this report. 4. The multi-information processing system according to claim 1, further comprising: a means for canceling the majority voting target designation in the majority voting target designation means in accordance with the subsystem disconnection instruction returned. 5. The bus interface device further includes storage means for storing a peripheral control device number indicating a request source corresponding to the transaction request and an execution destination thereof, means for detecting an error in this transaction, and this error detection. 5. The multi-information according to any one of claims 1 to 4, further comprising: means for reporting to a host as a failure of the peripheral control device corresponding to the peripheral control device number stored in the storage means in response to Processing system. 6. Each of the information processing subsystems comprises a processor, a memory, an internal bus connecting the memory and the processor, and a connection between the internal bus and the bus interface device. The interface unit has an interface unit, and when the transaction is received from the bus interface device, the interface unit stores a peripheral control device number indicating a request source or an execution destination of the transaction, and the bus interface. Means for detecting an error in the transaction from the device, and means for, in response to the error detection, adding the peripheral control device number stored in the storage means to the transaction as a failed peripheral control device number. The bus interface device is the interface A majority decision is made by the majority decision means for the faulty peripheral control device number added to the transaction sent from the unit, and an error of the faulty peripheral control device number is detected and reported to the host as a fault of the peripheral control device. The multi-information processing system according to claim 1, wherein the multi-information processing system is configured.