JPH08213907A - A/d converter - Google Patents

Abstract

PURPOSE: To improve the A/D conversion characteristic, especially its integration linearity by forming a resistive element array for dividing a reference voltage with impurity implantation by the ion implantation method so as to eliminate relative dispersion in components in the resistive element array. CONSTITUTION: Relative resistance dispersion between resistive elements is reduced by production of semiconductor resistive elements 12 such as polycrystal silicon elements used for a resistive element array through injection of an impurity 14 with the ion implantation method. Since the adoption of this ion implantation method is independent of the effect of temperature distribution in thermal diffusion, fluctuation due to a thermal cause depending on the position of impurity concentration of the resist elements with respect to the resistive element array is reduced and the relative dispersion in the resistance of the resistive element array is avoided. Then voltage dispersion of a reference voltage depending on the position of the resistive elements in the resistive element array is avoided by reducing the fluctuation in the resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / analog circuit having an analog voltage conversion circuit using a semiconductor resistance element array.
The present invention relates to a digital conversion device.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional method of generating a reference voltage dividing resistor array used in an analog / digital converter. Each resistance element 22 forming the resistance element array is made of polycrystalline silicon by thermal diffusion of N-type impurities such as phosphorus and arsenic or P-type impurities 24 such as boron to a substrate 21 such as polycrystalline silicon in a high temperature atmosphere. It is produced by injection diffusion. Reference numeral 23 is a wiring element such as aluminum which connects between the resistance elements 22.

The operation of the analog / digital conversion device using the semiconductor resistance array element configured as described above will be described with reference to FIG. FIG. 3 has a reference voltage dividing circuit by dividing a semiconductor resistance element array,
2 which is one of the typical examples of analog / digital converters
It shows an example in the case of 4 bits of the step type analog / digital converter.

In FIG. 3, reference numeral 31 is a reference voltage dividing resistor array, 32 is an upper comparator for comparing the analog input of the upper 2 bits and the reference voltage, and 33 is a comparison between the analog input of the lower 2 bits and the reference voltage. A lower comparator for performing the above, 34 is an upper 2 bit encoder for converting an upper comparator output into a higher 2 bit digital value, 35 is a lower 2 bit encoder for converting a lower comparator output into a lower 2 bit digital value, and 36 is Upper 2 bits of digital output, 37 is lower 2 bits of digital output.

Next, the operation will be described. The 2-step type analog / digital converter is divided into upper 2 bits and lower 2 bits for conversion. In the first step, the upper analog comparators CP1 to CP3 are used to input the input analog voltage Vi.
n is compared with reference voltage levels V1, V2, V3.
Now, when Vin> V1, CP1 output is high, CP
2, CP3 output goes low.

In the second step, the switches S1 to S4 are controlled as follows according to the output results of CP1 to CP3.

When Vin> V1, S1 is on. When Vin> V2, S2 is on. When Vin> V3, S3 is on. When Vin <V3, S4 is on. That is, it is supplied to the lower comparator group by the output result of the upper comparator. The comparison reference voltage level from the resistor array is switched.

[0008]

However, in FIG. 3, reference voltages V1, V2 and V for the upper comparators are used.
3 and the output voltages from the switches S1 to S12, which are the reference voltages for the lower comparator, are obtained by dividing the reference voltage Vreft-Vrefb by the resistance array, and therefore are interlocked with the relative variations between the resistance values. do it,
The reference voltages selected by the reference voltages V1, V2, V3 and S1 to S12 vary.

In FIG. 3, it is assumed that variations in the resistance values of the resistance elements R1, R2, ..., R16 forming the resistance array have the following characteristics.

R1>R2>R3> R4 R8>R7>R6> R5 R9>R10>R11> R12 R16>R15>R14> R13 The error in the resistance value depends on the variation in the resistance value in the case of the above characteristics. The analog / digital conversion characteristics are shown in FIG. As described above, the relative resistance value variations of the respective resistance elements show a wave-like conversion characteristic with respect to the ideal conversion characteristic, and deteriorate the integral linearity.

In the conventional method, as shown in FIG. 2, even if a plurality of resistance elements 22 having the same shape are formed, the temperature distribution of heat and the impurity concentration distribution in the heat diffusion device are not uniform. , An error occurs in the resistance value of each resistance element 22. Therefore, when viewed as a whole of the two-dimensionally arranged resistance array, an error distribution occurs in the relative resistance value between the resistance elements, and a plurality of resistance elements in the analog / digital conversion device are generated by the resistance element array. The division value of the reference voltage value is not constant, and an error from the ideal value occurs when converting the analog input value to the digital output value.

The present invention solves the above-mentioned conventional problems, and it is an object of the present invention to eliminate the relative variation in the resistance array and to improve the integral linearity of the analog / digital conversion characteristic.

[0013]

In order to achieve this object, the analog / digital converter of the present invention is formed by uniformly implanting impurities into a wiring resistance element such as polycrystalline silicon by an ion implantation method. The resistance element forms a reference voltage dividing resistance array.

[0014]

According to this ion implantation method, since it has nothing to do with the influence of the temperature distribution on the thermal diffusion, the fluctuation of the impurity concentration of the resistance element due to the thermal factor due to the position of the resistance array is reduced, and the resistance value of the resistance element array is reduced. There is no relative variation in. By reducing the variation of the resistance value, it is possible to eliminate the variation of the reference voltage at the time of analog / digital conversion due to the position of the resistor array, and to obtain good conversion characteristics.

[0015]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 14 is an impurity ion implanted by an ion implantation method, 12 is a semiconductor resistance element such as polycrystalline silicon forming a resistance array, which is generated by the ion implantation method, and 13 is a connection between the resistance elements of the resistance array. The wiring element 11 is made of aluminum or the like, and 11 is a semiconductor substrate made of silicon or the like. In the present invention, the relative resistance value between the resistance elements is reduced by generating the semiconductor resistance elements used in the resistance array by the ion implantation method.

As described above, according to this embodiment, the variation in the relative value of the resistance value between the resistance elements of the resistance array for dividing the reference voltage is reduced, and therefore the comparative reference voltage from the resistance element array is reduced. Since the fluctuation of the division ratio of is small, the error from the theoretical value with respect to the input level at the time of analog / digital conversion is reduced, so that the integral linear characteristic is improved. FIG. 5 shows a diagram of analog / digital conversion characteristics in the embodiment of the present invention.

[0017]

As described above, according to the present invention, in the analog / digital conversion device using the resistance array for dividing the reference voltage, the impurity implantation using the ion implantation method is performed to generate the semiconductor resistance element of the resistance array. As a result, the variation of the relative value of the resistance value is reduced, and the integral linearity characteristic of the analog / digital conversion characteristic is improved.

[Brief description of drawings]

FIG. 1 is a structural diagram showing a method of generating a semiconductor resistance element of an analog / digital converter of the present invention.

FIG. 2 is a structural diagram showing a conventional semiconductor resistance element generation method by impurity implantation by thermal diffusion.

FIG. 3 is a configuration diagram showing an example of an analog / digital conversion device using a semiconductor resistance element array.

FIG. 4 is a diagram showing an analog / digital conversion characteristic using a semiconductor resistance element according to a conventional method.

FIG. 5 is a diagram showing analog / digital conversion characteristics using a semiconductor resistance element according to an embodiment of the present invention.

[Explanation of symbols]

 11 semiconductor substrate 12 polycrystalline silicon resistance element 13 wiring between resistance elements such as aluminum 14 impurity implantation by ion implantation

Claims (1)

[Claims] 1. An analog / based device using a silicon semiconductor device.
In the digital conversion device, a reference voltage division unit having a resistance array, a comparator unit that compares the voltage values of the divided resistance array potential and the input analog potential, and an encoding unit that converts the result output of the comparator into a digital value. In the converter, the analog / digital converter is characterized in that a resistance element array for dividing a reference voltage is generated by ion implantation of impurities.