JPH08213366A - Pattern forming method, pattern forming equipment, manufacture of semiconductor integrated circuit device, and semiconductor manufacturing equipment - Google Patents

Abstract

PURPOSE: To improve elimination capability of a side film which is formed on the side wall of a pattern when it is formed by dry etching. CONSTITUTION: A photoresist pattern 24b formed on a laminated conductor film 23 is used as an etching mask, and a semiconductor substrate 10 is subjected to dry etching. After the laminated conductor film 23 exposed from the photoresist pattern 24b is eliminated by etching. In the state that a high frequency bias voltage is applied to the semiconductor substrate 10, plasma dry etching wherein O2 /SF6 or O2 /CHF3 or O2 /CF based gas is used as etching gas is performed, thereby eliminating a side film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern forming method and a pattern forming apparatus, a semiconductor integrated circuit device manufacturing method and a semiconductor manufacturing apparatus technique, and more particularly to a technique effective when applied to an electrode wiring pattern forming method. It is a thing.

[0002]

2. Description of the Related Art A conventional electrode wiring forming process is, for example, as follows. First, after forming a photoresist pattern on a conductor film for forming an electrode wiring, the conductor film portion exposed from the photoresist pattern is removed by etching by a dry etching method or the like using the photoresist pattern as an etching mask. Form a pattern.

Subsequently, the photoresist pattern which has become unnecessary is formed, for example, with oxygen (O ₂ ), O ₂ / CF ₄ or O _2.
/ CHF ₃ or the like is removed by an ashing process using an ashing gas. At this time, no bias voltage is applied to the semiconductor substrate.

After that, the side wall protective film formed on the side wall of the electrode wiring pattern during the electrode wiring patterning processing is removed by wet etching.

Regarding the removal processing of such a side wall protective film, for example, “Journal of Semiconductor World (Se
miconductor World) October issue "P80-P87.

[0006]

By the way, in recent years, in the technique of forming electrode wirings, in order to realize the processing of anisotropic patterns in order to cope with the miniaturization of patterns and the high aspect ratio, the processing temperature is low. Has become necessary.

However, the present inventor has found that the sidewall protective film becomes stronger as the processing temperature is lowered, and the sidewall protective film cannot be sufficiently removed only by the conventional wet etching treatment.

Further, the ashing process for removing the photoresist pattern has a function of accelerating the curing of the side wall protective film. For example, in the O ₂ / CH ₃ OH plasma treatment, it has been confirmed that the removability of the side wall protective film after the wet etching treatment is lowered due to the extension of the overashing time and the rise of the treatment temperature.

Since such a side wall protective film also contains a conductive component such as aluminum (Al) or copper (Cu) as its component, the side wall protective film must remain between adjacent electrode wirings. Therefore, there arises a problem that a short circuit failure is caused or a wiring connection failure is caused in the connection hole.

Therefore, in order to prevent the occurrence of such a defect, the wet etching process time becomes long, and there is a problem that the throughput of the semiconductor integrated circuit device manufacturing is lowered.

Further, according to the study by the present inventor, when the plasma dry etching treatment using a chlorine (Cl ₂ ) gas is performed to remove the side wall protective film, corrosion of the conductor film is a problem. It turned out to be

An object of the present invention is to provide a technique capable of improving the removability of the side wall protective film.

Another object of the present invention is to provide a technique capable of improving the throughput of pattern formation.

A further object of the present invention is to provide a technique capable of improving the corrosion resistance of the conductor film.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0016]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the pattern forming method of the present invention is
When the predetermined film is formed on the substrate to be processed by processing the film to be processed formed on the substrate to be processed, the following steps are included.

(A) After forming a resist pattern having a predetermined shape on the film to be processed, the substrate to be processed is dry-etched by using the resist pattern as an etching mask to cover and etch the resist pattern. A step of etching away a portion of the film to be processed exposed from the resist pattern with a protective film formed on the side surface of the film to be processed which is not removed.

(B) A step of removing the resist pattern.

(C) O ₂ / S as an etching gas with a high frequency substrate bias voltage applied to the substrate to be processed.
A step of performing a plasma dry etching process using a gas of F ₆ , O ₂ / CHF ₃ or O ₂ / CF system.

(D) A step of performing a wet etching process on the substrate to be processed.

Further, the pattern forming apparatus of the present invention processes the film to be processed formed on the substrate to be processed,
A pattern forming apparatus for forming a predetermined pattern on the substrate to be processed, which has the following components.

(A) A dry etching process is performed on the substrate to be processed by using the resist pattern formed on the film to be processed as an etching mask to etch the film portion exposed from the resist pattern. A main etching processing part for removing and forming the predetermined pattern.

(B) O ₂ / S as an etching gas under the condition that a high frequency substrate bias voltage is applied to the substrate to be processed.
A first sub-etching treatment section for performing plasma dry etching treatment using F ₆ , O ₂ / CHF ₃ or O ₂ / CF gas.

Further, the pattern forming apparatus of the present invention processes the film to be processed formed on the substrate to be processed,
A pattern forming apparatus for forming a predetermined pattern on the substrate to be processed, which has the following components.

(A) Using the resist pattern formed on the film to be processed as an etching mask, dry etching is performed on the substrate to be processed to etch the film to be processed exposed from the resist pattern. A main etching processing part for removing and forming the predetermined pattern.

(B) An ashing treatment function for removing the resist pattern by ashing, and O ₂ / SF ₆ , O ₂ / CHF ₃ or O as an etching gas in a state where a high frequency substrate bias voltage is applied to the substrate to be processed. ₂ /
A processing unit having a first sub-etching processing function for performing plasma dry etching processing using a CF-based gas.

Further, the pattern forming apparatus of the present invention has a carrying function for carrying the substrate to be processed to each processing section, and a vacuum maintaining function for maintaining a vacuum state in a carrying chamber for carrying the substrate to be processed. And a carrying section provided with.

Further, the pattern forming apparatus of the present invention has a structure capable of applying the high frequency substrate bias voltage of 100 V to 300 V, and the temperature of the substrate to be processed during the first sub-etching process can be set to 0 ° C. to 80 ° C. In this structure, the flow rate ratio of SF ₆ , CHF ₃ or CF gas in the etching gas during the first sub-etching process can be set to 1 to 25%.

In the method for manufacturing a semiconductor integrated circuit device of the present invention, the following steps are performed when a predetermined pattern is formed on the semiconductor substrate by processing the film to be processed formed on the semiconductor substrate. Is to have.

(A) After forming a resist pattern having a predetermined shape on the film to be processed, the semiconductor substrate is dry-etched using the resist pattern as an etching mask to cover the resist pattern and remove it by etching. A step of etching and removing the processed film portion exposed from the resist pattern in a state where a protective film is formed on the side surface of the processed film that is left unattended.

(B) A step of removing the resist pattern.

(C) O ₂ / S as an etching gas under the condition that a high frequency substrate bias voltage is applied to the semiconductor substrate.
A step of performing a plasma dry etching process using a gas of F ₆ , O ₂ / CHF ₃ or O ₂ / CF system.

(D) A step of subjecting the semiconductor substrate to a wet etching process.

In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the film to be processed is a conductor film and the predetermined pattern is an electrode wiring pattern.

Further, in the method for manufacturing a semiconductor integrated circuit device of the present invention, the film to be processed is an insulating film and the predetermined pattern is a connection hole pattern.

Further, the semiconductor manufacturing apparatus of the present invention is a semiconductor manufacturing apparatus for forming a predetermined pattern on a semiconductor substrate by processing a film to be processed formed on the semiconductor substrate. It has a constituent part.

(A) By using the resist pattern formed on the film to be processed as an etching mask, a dry etching process is performed on the semiconductor substrate to etch away the film to be processed exposed from the resist pattern. Then, a main etching processing part for forming the predetermined pattern.

(B) O ₂ / S as an etching gas under the condition that a high frequency substrate bias voltage is applied to the semiconductor substrate.
A first sub-etching treatment section for performing plasma dry etching treatment using F ₆ , O ₂ / CHF ₃ or O ₂ / CF gas.

The semiconductor manufacturing apparatus of the present invention is a semiconductor manufacturing apparatus for forming a predetermined pattern on a semiconductor substrate by processing a film to be processed formed on the semiconductor substrate. It has a constituent part.

(A) A dry etching process is performed on the semiconductor substrate using the resist pattern formed on the processed film as an etching mask to etch away the processed film portion exposed from the resist pattern. Then, a main etching processing part for forming the predetermined pattern.

(B) An ashing function for ashing and removing the resist pattern, and O ₂ / SF ₆ , O ₂ / CHF ₃ or O ₂ as an etching gas in a state where a high frequency substrate bias voltage is applied to the semiconductor substrate. /
A processing unit having a first sub-etching processing function for performing plasma dry etching processing using a CF-based gas.

Further, the semiconductor manufacturing apparatus of the present invention has a transfer function for transferring the semiconductor substrate to each processing section, and a vacuum maintaining function for maintaining a vacuum state in the transfer chamber for transferring the semiconductor substrate. A transport section is provided.

Further, the semiconductor manufacturing apparatus of the present invention has a structure capable of applying the high frequency substrate bias voltage of 100 V to 300 V, and the temperature of the semiconductor substrate during the first sub-etching process can be set to 0 ° C. to 80 ° C. Structure and
The flow rate ratio of SF ₆ , CHF ₃ or CF based gas in the etching gas during the first sub-etching process is set to 1
It has a structure that can be set to -25%.

[0045]

According to the present invention described above, plasma using an O ₂ / SF ₆ , O ₂ / CHF ₃ or O ₂ / CF type gas as an etching gas in a state where a high frequency substrate bias voltage is applied to a substrate to be processed. By performing the dry etching process, the protective film formed on the side surface of the film to be processed during the main etching process can be removed by both the chemical action and the physical action. It becomes possible to improve the removability.

Therefore, by using the present invention in the method for manufacturing a semiconductor integrated circuit device, the residual protective film causes a short circuit between adjacent wirings, and the protective film remaining in the connection hole causes wiring connection failure in the connection hole. Since it is possible to reduce the occurrence of such a phenomenon, it is possible to improve the yield and reliability of the semiconductor integrated circuit device.

Further, by performing such a plasma dry etching treatment, it is possible to greatly reduce the wet etching treatment time which has been performed for removing the protective film. Therefore, by using the present invention in a method for manufacturing a semiconductor integrated circuit device, it is possible to improve the throughput of manufacturing a semiconductor integrated circuit device.

By using a gas containing O ₂ as an etching gas in the plasma dry etching process, the surface of the conductor film can be oxidized and passivated during the plasma dry etching process.
By performing such plasma dry etching treatment after the conductor film etching treatment, it becomes possible to improve the corrosion resistance of the conductor film pattern.

By using a gas containing fluorine such as SF ₆ as an etching gas in the plasma dry etching treatment, chlorine on the surface of the conductor film can be replaced with fluorine during the plasma dry etching treatment. Therefore, by performing such plasma dry etching treatment after patterning the conductor film, it becomes possible to improve the corrosion resistance of the conductor film pattern.

Therefore, by using such a pattern forming method in the method of forming the electrode wiring pattern of the semiconductor integrated circuit device, the corrosion resistance of the electrode wiring pattern can be improved and the reliability of the electrode wiring can be improved. Is possible.

Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved. Further, since the time limit for leaving until the wet etching process can be extended, it is possible to improve the workability of the worker in the semiconductor product manufacturing line.

Further, according to the present invention, an ashing treatment function for ashing and removing the resist pattern, and O ₂ / SF ₆ , O ₂ / CHF ₃ as etching gas under the condition that a high frequency substrate bias voltage is applied to the semiconductor substrate are used. Alternatively, the ashing process and the first ashing process can be performed by providing a processing unit having a first sub-etching process function for performing a plasma dry etching process using an O ₂ / CF-based gas.
Since the sub-etching process can be performed almost at the same time in the same processing unit, the number of processing steps can be reduced and the overall processing time can be shortened. Therefore, by using the present invention in a method for manufacturing a semiconductor integrated circuit device,
It is possible to further improve the throughput of manufacturing a semiconductor integrated circuit device.

Further, according to the present invention, the transfer having the transfer function for transferring the substrate to be processed to each processing section and the vacuum maintaining function for maintaining the vacuum state in the transfer chamber for transferring the substrate to be processed. By providing the parts, the transfer part between the processing parts can be evacuated, so that it is possible to further improve the corrosion resistance of the conductor film pattern and the like.

Therefore, by using such a pattern forming method in the method of forming the electrode wiring pattern of the semiconductor integrated circuit device, the corrosion resistance of the electrode wiring pattern can be further improved and the reliability of the electrode wiring can be improved. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved. Further, since the time limit for leaving until the wet etching process can be extended, it becomes possible to improve the workability of the worker in the manufacturing line.

Further, according to the present invention, by setting the high frequency substrate bias voltage to 100 V or more in the first sub-etching process, a sufficient ion attack amount with respect to the protective film can be obtained, so that the removability of the protective film is improved. It becomes possible. Further, at that time, by setting the high frequency substrate bias voltage to 300 V or less, it becomes possible to prevent the base insulating film and the like from being excessively shaved.

By setting the substrate temperature at the time of the first sub-etching process to 0 ° C. to 80 ° C., it is possible to prevent the base insulating film from being excessively shaved, and to prevent peeling of the conductor film and segregation of atoms in the conductor film. It becomes possible to do.

Further, by making the flow rate ratio of SF ₆ , CHF ₃ or CF type gas in the etching gas during the first sub-etching treatment to be 1% or more, the removability of the protective film can be improved. Become. Further, by setting the flow rate ratio of SF ₆ , CHF ₃ or CF type gas in the etching gas to 25% or less, it becomes possible to prevent the conductor film from being over-cut or undercut.

[0058]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is an explanatory view of a semiconductor manufacturing apparatus which is an embodiment of the present invention, FIG. 2 is an explanatory view of a sub-etching processing section in the semiconductor manufacturing apparatus of FIG. 1, and FIG.
Of a modified example of the sub-etching processing unit in the semiconductor manufacturing apparatus of FIG. 4, FIG. 4 is an explanatory view of the semiconductor manufacturing apparatus which is an embodiment of the present invention, and FIG. 5 is a semiconductor integrated circuit device which is an embodiment of the present invention Flow charts showing the manufacturing process, FIGS. 6 to 11,
13 to 22 and FIGS. 31 and 32 are cross-sectional views of the main part of the semiconductor integrated circuit device during the manufacturing process of FIG. 5, FIG. 12 is a graph showing the protective film removal effect under various conditions,
23 to 25 show Cl for removing the side film.
SEM photographs of the wiring pattern around the semiconductor wafer when the plasma dry etching treatment using the ₂ system gas is performed, and FIGS. 26 to 28 are wiring around the semiconductor wafer when the protective film removing treatment of the present invention is performed. 29 is a SEM photograph of the wiring portion when the protective film removing treatment of the present invention is not performed, and FIG. 30 is an SEM photograph of the wiring portion when the protective film removing treatment of the present invention is performed.
It is an EM photograph.

First, the semiconductor manufacturing apparatus of the first embodiment is shown in FIG.
~ It demonstrates by FIG.

A semiconductor manufacturing apparatus 1A of this embodiment shown in FIG.
Is a cluster tool for forming a connection hole in an insulating film on a semiconductor wafer, for example, and a load lock portion 3a, an unloading portion 4a, a main etching processing portion 5a, and a main ashing are provided on the outer periphery of the central transfer portion 2a. Processing unit 6
a, sub-etching processing units 7a and 8a, and sub-ashing processing unit 9a are installed.

The central transfer section 2a is a mechanism section for transferring a semiconductor wafer (not shown in FIG. 1) to each section of the semiconductor manufacturing apparatus 1A, and a semiconductor wafer transfer mechanism (not shown) such as a transfer arm. And a vacuum maintaining function for maintaining a vacuum state in the transfer chamber.

The load lock section 3a is a mechanism section for loading a semiconductor wafer into the semiconductor manufacturing apparatus 1A. The unloading section 4a is a mechanism section for carrying out the semiconductor wafer, for which the connection hole forming process has been completed, to the outside of the semiconductor manufacturing apparatus 1A.

The main etching processing section 5a is an etching processing section for forming a connection hole at a predetermined position of the insulating film by etching away a predetermined portion of the insulating film deposited on the semiconductor wafer, and for example, a parallel etching processing section. A plasma dry etching apparatus having a flat electrode structure is used. As the reaction gas, for example, carbon tetrafluoride (CF ₄ ) gas, trifluoromethane (CHF ₃ ) gas or argon (Ar) gas can be used.

The main ashing processing section 6a is a processing section for removing an unnecessary photoresist film,
In the first embodiment, for example, a downflow type microwave plasma ashing device is used. As the ashing gas, for example, oxygen (O ₂ ) + water (H
It is possible to use a gas obtained by adding a hydroxyl group (OH) to ₂ O) or O ₂ .

The sub-etching portion (first sub-etching portion) 7a is for removing the side film (protective film) adhered to the inner wall surface of the connection hole during the dry etching treatment for forming the above-mentioned connection hole. Is the processing part of
In the first embodiment, for example, ECR (Electron Cycro
toron Resonance) A plasma dry etching apparatus or a plasma dry etching apparatus having a parallel plate type electrode structure is used. Details of the sub-etching processing section 7a will be described later.

The sub-etching portion (second sub-etching portion) 8a was installed to remove the side film deposited on the inner wall surface of the connection hole during the dry etching treatment for forming the above-mentioned connection hole. Is a processing unit,
For example, a wet etching device is used. The sub-etching section 8a is also provided with a drying mechanism for drying the semiconductor wafer after the wet etching processing.

The sub-ashing processing section 9a is a processing section for removing the remaining portion of the photoresist film and the like. In the first embodiment, for example, in order to prevent contamination and damage due to charge-up, ultraviolet rays are used. Light and ozone (O
₃ ) A so-called optical ashing device is used, which uses a gas to oxidatively decompose and remove the photoresist film.

Next, the above-mentioned sub-etching processing portion 7a
As an example of the above, a case of using an ECR plasma dry etching apparatus and a case of using a plasma dry etching apparatus having a parallel plate type electrode structure will be described with reference to FIGS. 2 and 3, respectively.

First, the ECR plasma dry etching apparatus will be described. As shown in FIG. 2, the magnetron oscillator 7a1 which constitutes the sub-etching processing section 7a.
Is, for example, a 2.45 GHz micro (hereinafter referred to as μ)
It is a μ-wave source for generating waves.

The μ-wave generated from the magnetron oscillator 7a1 is passed through an isolator (not shown), a power monitor (not shown), a vent-type waveguide 7a2, etc. to a plasma etching processing section (hereinafter simply referred to as processing). A room)
The structure is such that it is supplied to 7a3.

The processing chamber 7a3 is formed by a discharge tube 7a4. This discharge tube 7a4 is for passing μ waves,
For example, it is made of a dielectric material such as quartz or alumina. A lower electrode 7a5 is installed below the processing chamber 7a3. The above semiconductor wafer W is mounted on the lower electrode 7a5 in an electrically insulated state.

The lower electrode 7a5 is electrically connected to the high frequency power supply 7a6 via a matching unit (not shown). As a result, in the sub-etching processing section 7a,
It is possible to apply a substrate bias voltage to the lower electrode 7a5 during the etching process.

In the first embodiment, the substrate bias frequency is set to, for example, 13.56 MHz, 2 MHz or 80.
It can be set to 0 KHz. Further, the substrate bias voltage can be set to, for example, about 100V to 300V.

Further, the temperature adjusting liquid supply pipe 7a7 supplies the temperature adjusting liquid for setting the temperature of the semiconductor wafer W to the lower electrode 7a.
This is a supply pipe for supplying to the 5 side. In the first embodiment, the temperature of the semiconductor wafer W during the etching process can be set to 0 to 80 ° C., for example.

The reaction gas that contributes to the etching process is supplied into the processing chamber 7a3 through a gas supply pipe (not shown). As the reaction gas, for example, O ₂
/ Sulfur hexafluoride (SF ₆ ), O ₂ / CHF ₃ or O ₂
It is possible to use a fluorocarbon (CF) -based gas. Then, the flow rate ratio of SF ₆ , CHF ₃ or CF type gas can be controlled to 1 to 25%. The reaction product gas generated by the etching process and the reaction gas that does not contribute to the etching process are exhausted through the exhaust port 7a8.

Further, on the outer circumference of the discharge tube 7a4, for example, electromagnets 7a9, which are stacked in two stages so as to surround it,
7a9 is installed. This electromagnet 7a9, 7a9
Is a means for generating an ECR phenomenon by forming a magnetic field orthogonal to the electric field of the .mu.-wave entered into the processing chamber 7a3 during the etching process. This makes it possible to control the electron density distribution and plasma density distribution in the processing chamber 7a3.

Next, a plasma dry etching apparatus having a parallel plate type electrode structure will be described. As shown in FIG. 3, the semiconductor wafer W is placed on the cathode 7a10 that constitutes the sub-etching processing section 7a. The cathode 7a10 is electrically connected to the high frequency power supply 7a12 via the matching unit 7a11. As a result, in the sub-etching processing section 7a, it is possible to apply a substrate bias voltage to the cathode 7a10 during the etching processing.

In the first embodiment, the substrate bias frequency is set to, for example, 13.56 MHz, 2 MHz or 800 K.
It can be set to Hz. Further, the substrate bias voltage can be set to, for example, about 100V to 300V. In the first embodiment, the temperature of the semiconductor wafer W during the etching process is set to 0, for example.
It is possible to set the temperature in the range of ℃ to 80 ℃.

The reaction gas that contributes to the etching process is supplied into the processing chamber 7a13 through a gas supply pipe (not shown). As the reaction gas, for example, O ₂
It is possible to use / SF ₆ , O ₂ / CHF ₃ or O ₂ / CF based gas. And SF ₆ , C
It is possible to control the flow rate ratio of HF ₃ or CF gas to 1 to 25%. The gas in the processing chamber 7a13 is
The air is exhausted through the exhaust port 7a14.

An anode 7a15 is installed above the cathode 7a10 in parallel with the cathode 7a10. The anode 7a15 is electrically connected to the ground portion 7a16. Anode 7a15 and cathode 7
The a10 is insulated by an insulator 7a17 provided between the inner circumference of the lower part of the anode 7a15 and the outer circumference of the lower part of the cathode 7a10.

The semiconductor manufacturing apparatus 1B of the first embodiment shown in FIG. 4 is a cluster tool for forming a wiring pattern on a semiconductor wafer, for example.
A load lock part 3a and an unload part 4 are provided on the outer periphery of a.
a, a main etching processing unit 5b, a main ashing processing unit 6a, a sub etching processing unit 7a, a sub etching processing unit 8a, and a sub ashing processing unit 9a are installed.

The semiconductor manufacturing apparatus 1A is the same as the above-described semiconductor manufacturing apparatus 1A except for the main etching processing section 5b. The main etching processing section 5b is an etching processing section for forming a wiring pattern by etching away a predetermined portion of the conductor film deposited on the semiconductor wafer, and, for example, a microwave plasma dry etching apparatus is used. There is.

The reaction gas varies depending on the material of the conductor film to be etched and cannot be generally stated.
For example, the following reaction gas can be used.

That is, when etching the aluminum (Al) -based conductor film, for example, boron trichloride (B
It is possible to use Cl ₃ ) + chlorine (Cl ₂ ) gas.

Tungsten and titanium Tungsten (Ti
When the conductor film made of W) or the like is etched, it is possible to use, for example, SF ₆ + BCl ₃ gas or a gas obtained by adding nitrogen (N ₂ ) gas thereto.

When etching a conductor film made of titanium nitride (TiN) or the like, for example, SF ₆ + BCl ₃ gas, SF ₆ + BCl ₃ + Cl ₂ gas or BCl ₃ + C is used.
It is possible to use l ₂ gas.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to the flow chart of FIG. 5 with reference to FIGS. 1 to 4 and 6 to 32. In the first embodiment, the present invention is applied to, for example, a 64-Mbit DRAM (Dynami
c Random Access Memory) will be described.

FIG. 6 and FIG. 7 respectively show a memory cell region M and a peripheral circuit region A during the DRAM manufacturing process.
FIG.

Semiconductor substrate 10 constituting a semiconductor wafer
Is made of, for example, p-type silicon (Si) single crystal. A p well 11p is formed in the semiconductor substrate 10 in the memory cell region M. In the peripheral circuit area A,
The p well 11p and the n well 11n are formed so as to be adjacent to each other.

For example, a p-type impurity such as boron is introduced into the p-well 11p, and a p-type channel stopper layer 12p is formed in the p-well 11p.
For example, p-type impurity such as boron is introduced into the channel stopper layer 12p.

On the other hand, for example, an n-type impurity such as phosphorus is introduced into the n-well 11n, and an n-type channel stopper layer 12n is formed in the n-well 11n. The channel stopper layer 12n is doped with, for example, n-type impurity such as phosphorus.

Channel stopper layer 1 in p well 11p
A p-type semiconductor region 14p is formed in the element forming region surrounded by the field insulating film 13 on 2p. For example, p-type impurity such as boron is introduced into the semiconductor region 14p.

On the channel stopper layer 12n in the n well 11n, an n-type semiconductor region 14n is formed in the element forming region surrounded by the field insulating film 13. For example, phosphorus, which is an n-type impurity, is introduced into the semiconductor region 14n. The field insulating film 13 is made of, for example, silicon dioxide (SiO ₂ ).

Semiconductor region 14 in memory cell region M
On p, an n-channel type M constituting the memory cell MC is formed.
An OS • FET (hereinafter simply referred to as nMOS) 15 and a capacitor 16 are formed.

The nMOS 15 is an LDD (Lightly Doped).
Drain) structure, and a pair of semiconductor regions 15a, 15a formed in the semiconductor region 14p and the semiconductor substrate 1
It has a gate insulating film 15b formed on the upper surface of 0 and a gate electrode 15g formed on the gate insulating film 15b.

The pair of semiconductor regions 15a and 15a are made of nM
This is a region for forming the source / drain of the OS 15. Each of the semiconductor regions 15a is composed of an n ⁻ -type semiconductor region 15a1 arranged near the gate electrode 15g and an n ^{+ -type} semiconductor region 15a2 arranged outside thereof.
Both are formed, for example, by introducing n-type impurities such as phosphorus.

One semiconductor region 15 of the nMOS 15
a (semiconductor region 15a in the center of FIG. 6) is one semiconductor region 15 of the nMOS 15 of the other memory cell MC adjacent to it.
It is also a. That is, the semiconductor region 15a at the center of FIG.
Is a common area of the two memory cells MC.

The gate insulating film 15b is made of SiO ₂ , for example. The gate electrode 15g is a part of the word line,
For example, it is made of n-type low resistance polysilicon. The insulating film 17 formed on the gate electrode 15g and the insulating film 18 formed on the side surface of the gate electrode 15g are made of, for example, Si.
It consists of O ₂ . The insulating film 18 is an insulating film for forming an LDD structure.

The capacitor 16 is, for example, a fin-shaped capacitor, and is composed of a lower electrode 16a, an upper electrode 16b around the lower electrode 16a, and a capacitor insulating film 16c formed therebetween.

The lower electrode 16a is made of, for example, n-type low resistance polysilicon and has, for example, three fin portions 16a1 to 16a1.
16a3. The lower electrode 16a is electrically connected to the semiconductor region 15a of the nMOS 15 through a connection hole 20a formed in the insulating film 19a on the semiconductor substrate 10.

The upper electrode 16b is made of, for example, n-type low resistance polysilicon, is electrically connected to a power supply wiring (not shown), and is set to a predetermined potential. In addition, the capacitor insulating film 16c is formed of, for example, silicon nitride (Si ₃ N
₄ ) Alternatively, it is composed of a laminated film of Si ₃ N ₄ and SiO ₂ . The insulating film 19a is made of SiO ₂ , for example.

The semiconductor substrate 10 in the peripheral circuit region A has, for example, an nMOS 21 having an LDD structure and a p-channel type MOS.FET (hereinafter simply referred to as pMOS).
22) is formed.

The nMOS 21 includes a pair of semiconductor regions 21a, 21a formed in the semiconductor region 14p, a gate insulating film 21b formed on the semiconductor substrate 10, and a gate electrode 21g formed on the gate insulating film 21b. have.

The pair of semiconductor regions 21a is composed of the nMOS 21
Region for configuring the source / drain region of
Each semiconductor region 21a is composed of an n ^{− type} semiconductor region 21a1 arranged near the gate electrode 21g and an n ^{+ type} semiconductor region 21a2 arranged outside thereof. However, n ^- the type semiconductor region 21a1, for example, phosphorus is introduced into such an n-type impurity, the n ⁺ type semiconductor region 21a2,
For example, an n-type impurity such as arsenic (As) is introduced.

Further, the pMOS 22 has a semiconductor region 14n.
It has a pair of semiconductor regions 22a and 22a formed therein, a gate insulating film 22b formed on the semiconductor substrate 10, and a gate electrode 22g formed on the gate insulating film 22b.

The pair of semiconductor regions 22a has a pMOS 14
Region for configuring the source / drain region of
Each of the semiconductor regions 22a is composed of a p ⁻ -type semiconductor region 22a1 arranged near the gate electrode 22g and a p ^{+ -type} semiconductor region 22a2 arranged outside the p ⁻ -type semiconductor region 22a1. It is introduced and formed.

The nMOS 21 and pMOS 22 described above
The gate insulating films 21b and 22b are made of, for example, SiO ₂ , and the gate electrodes 21g and 22g are made of, for example, n-type low resistance polysilicon.

An insulating film 19b made of, for example, SiO ₂ is formed on the insulating film 19a, and the upper electrode 16 of the capacitor 16 is formed.
b, nMOS 21 and pMOS 22 are deposited to cover them. On the insulating film 19b, for example, SiO ₂
An insulating film 19c made of is deposited. Further, on the insulating film 19c, an insulating film 19d made of, for example, SiO ₂ is formed.
Have been deposited.

The bit line 23BL is formed on the insulating film 19d in the memory cell region M. Bit line 2
3BL is a connection hole 2 formed in the insulating films 19a to 19d.
NMOS1 through the bit line connecting portion 23BL1 in 0b
5 is electrically connected to the semiconductor region 15a.

The bit line 23BL is formed, for example, by depositing a conductor layer made of tungsten, a conductor layer made of an Al--Si--Cu alloy, and a conductor layer made of tungsten in this order from the lower layer. Also, the bit line connecting portion 23BL1
Is made of, for example, n-type low resistance polysilicon.

The insulating film 19 in the peripheral circuit region A is also used.
A first layer wiring 23L1 forming a peripheral circuit is formed on d.

The first layer wiring 23L1 is, as described later,
For example, a conductor layer made of tungsten and Al-Si-Cu
A conductor layer made of an alloy and a conductor layer made of tungsten are sequentially deposited from the lower layer, and electrically connected to the semiconductor region 21a of the nMOS 21 and the semiconductor region 22a of the pMOS 22 through the connection hole 20c formed in the insulating films 19b to 19d. Has been done.

The wiring width of the first layer wiring 23L1 is in the range of 0.3 μm to 0.5 μm, for example, 0.35 μm.
It is a degree. The wiring interval is, for example, in the range of 0.3 μm to 0.5 μm, and is, for example, about 0.35 μm.

On the insulating film 19d, for example, SiO
_An insulating film 19e made of ₂ is formed, which covers the bit line 23BL and the first layer wiring 23L1. A photoresist pattern 24a for forming a connection hole is formed on the insulating film 19e by a photolithography technique.

After the semiconductor substrate 10 as described above is housed in the load lock portion 3a of the semiconductor manufacturing apparatus 1A of FIG. 1, the semiconductor substrate 10 is subjected to the following etching treatment, so that the insulating film 19e has the first-layer wiring. A connection hole is formed so that a part of 23L1 is exposed.

A process of forming this connection hole will be described with reference to FIGS. 8 to 11 along the flow chart of FIG. FIG. 8 is an enlarged view of a main part of the peripheral circuit area A in FIG. First layer wiring 23L1
As described above, for example, the three conductor films 23L1a-2
3L1c is laminated in order from the lower layer. The lowermost and uppermost conductive films 23L1a and 23L1c are made of, for example, tungsten, and the intermediate conductive film 23L1b is made of, for example, Al—S.
It consists of an i-Cu alloy. Photoresist pattern 24a
From, only the connection hole forming region is exposed.

First, the semiconductor substrate 10 housed in the load lock section 3a is sent to the main etching processing section 5a,
The semiconductor substrate 10 is etched (step 100 in FIG. 5).

In the main etching processing portion 5a, the insulating film 19e portion exposed from the photoresist pattern 24a is removed by etching, for example, by performing plasma dry etching processing on the semiconductor substrate 10 using the photoresist pattern 24a as an etching mask. To do. As the reaction gas at this time, for example, CF ₄ gas,
CHF ₃ gas or Ar gas is used.

As a result, as shown in FIG.
A connection hole 20d is formed in 9e so that a part of the first layer wiring 23L1 is exposed. The size of the connection hole 20d is, for example,
The thickness is about 0.4 μm, and the side film 25a is formed on the inner surface of the connection hole 20d. The side film 25a contains components such as carbon, Si, Al and Cu.

Then, the semiconductor substrate 10 on which such etching processing has been completed is taken out from the main etching processing section 5a and sent to the main ashing processing section 6a, where it is subjected to ashing processing (step 1).
01).

In the main ashing processing section 6a, the unnecessary photoresist pattern 24a is removed by subjecting the semiconductor substrate 10 to plasma ashing processing, for example. As the ashing gas at this time, for example, O ₂ single gas, O ₂ + H ₂ O, or O ₂
A gas to which an OH group is added is used. FIG. 10 shows a cross-sectional view of the main part of the semiconductor substrate 10 after this ashing process. At this stage, the side film 25a in the connection hole 20d is left without being removed.

After that, the semiconductor substrate 10 that has undergone such ashing treatment is taken out from the main ashing treatment portion 6a and sent to the sub-etching treatment portion 7a, where it is subjected to etching treatment (step 10).
2).

In the sub-etching portion 7a, the side film 25a left in the connection hole 20d is removed by etching, for example, by performing plasma dry etching treatment on the semiconductor substrate 10. FIG. 11 shows a cross-sectional view of the main part of the semiconductor substrate 10 after this treatment.

In the first embodiment, the following two processing conditions are set for this etching process.

First, the reaction gas is, for example, O ₂ / SF ₆
Gas, O ₂ / CHF ₃ gas, or O ₂ / CF-based (for example, CF ₄ ) gas is used. That is, in Example 1, the side film 25a can be satisfactorily removed by a chemical action by using an etching gas having a high etching rate for the components forming the side film 25a.

Secondly, in this processing, the semiconductor substrate 10
Lower electrode 7a5 (see FIG. 2) or cathode 7a for mounting
A high frequency voltage is applied to the semiconductor substrate 10 (see FIG. 3).
A bias voltage is applied to. This allows the side film 25a to be removed by a physical action such as a sputtering phenomenon.

As described above, in the first embodiment, since the side film 25a can be removed by both the chemical action and the physical action, the removability of the side film 25a can be improved. It is possible. Therefore, the reliability of the wiring connection in the connection hole 20d can be improved, and the yield and reliability of the semiconductor integrated circuit device can be improved.

Here, the inventor of the present invention, for example, W / Al / W
FIG. 12 shows the results of side film removability under various conditions examined during the processing of laminated wiring.

Condition 1 is a case where the etching process in step 102 is not performed. In this case, the side film 25a
Remains.

The condition 2 is that the reaction gas is, for example, BCl.
_This is the case where ₃ / Cl ₂ gas is used. In this case, the side film 25a remains and the number of corrosions increases significantly. This increase in the number of corrosions is due to Cl left on the wiring sidewalls.

Condition 3 is a case where, for example, only O ₂ gas is used as the reaction gas. Also in this case, the side film 25a remains. That is, it is understood that the side film 25a cannot be removed by the etching process using only O ₂ gas.

Condition 4 is that the reaction gas is, for example, O ₂ /
This is the case when CHF ₃ gas is used. In this case, the side film 25a can be removed. However, in this case, a deposit may be generated due to the carbon component.

The condition 5 is that the reaction gas is, for example, O ₂ /
This is the case when SF ₆ gas is used. In this case, the side film 25a could be removed, and the deposits were not deposited.

Furthermore, in the case of condition 5, the number of corrosions could be greatly reduced. This is considered to be due to the following two reasons. First, the fluorine component in the plasma replaces the Cl component on the side wall of the wiring that induces corrosion. Secondly, the oxygen component oxidizes the passivation surface to passivate it.

According to the results of the study conducted by the present inventor, it was found that it is desirable to set the following conditions for such etching treatment.

First, it is desirable that the flow rate ratio of SF ₆ gas, CHF ₃ gas, CF-based gas or the like be, for example, about 1 to 25%.

When the gas flow rate ratio is less than 1%, the etching process is performed only with O ₂ gas, and as shown in FIG. 12, the side film cannot be removed, and the gas flow rate ratio is 25% or more. Then, the amount of abrasion of the conductor film 23L1c of the first-layer wiring 23L1 increases, and undercutting or the like also occurs.

Secondly, the substrate bias voltage applied to the semiconductor substrate 10 is preferably about 100V to 300V, for example. This is because if the substrate bias voltage is lower than 100V, the ion attack on the side film 25a is insufficient and the side film 25a cannot be removed satisfactorily. If it is higher than 300V, the insulating film 19e and the conductor film 23L1c are also removed. Because it will be removed.

Thirdly, the temperature of the semiconductor substrate 10 during processing is
For example, it is desirable to set the temperature as low as 0 ° C to 80 ° C. This is because if the temperature is too high, the insulating film 19
This is because the removal of e may proceed, the first layer wiring 23L1 may be peeled off, and Cu or Si in the wiring may be segregated.

Next, the semiconductor substrate 10 on which the above side film etching processing has been completed is taken out from the sub-etching processing section 7a, and then the sub-etching processing section 8a.
Then, the semiconductor substrate 10 is subjected to wet etching treatment (step 103).

In the sub-etching portion 8a, the side film 25a left in the wiring side wall and the like is removed by performing a wet etching treatment on the semiconductor substrate 10.

At this time, in the first embodiment, the side film 25 is formed in the sub-etching processing portion 7a.
Since the removal processing of a has already been performed, the side film 2
The side film 25a can be removed easily and in a short time as compared with the case where 5a is removed only by wet etching.

Then, the semiconductor substrate 10 after the wet etching process is taken out from the sub-etching process section 8a and sent to the sub-ashing process section 9a, and the semiconductor substrate 10 is subjected to the ashing process (step 104).

In the sub-ashing processing section 9a, in order to prevent contamination and damage due to charge-up and the like, optical ashing for oxidizing and removing the photoresist by using, for example, ultraviolet light and ozone (O ₃ ) gas is carried out. Apply processing.

After passing through the steps 100 to 104, the semiconductor substrate 10 is taken out from the sub-ashing processing section 9a and sent to the unloading section 4a, and the formation processing of the connection hole 20d is completed.

Then, on the semiconductor substrate 10 in which the connection hole 20d is formed, a conductor layer made of, for example, tungsten, A
A laminated conductor film is formed by sequentially depositing a conductor layer made of an 1-Si-Cu alloy and a conductor layer made of tungsten by sputtering or the like from the lower layer.

Subsequently, the laminated conductor film is patterned by a photolithography technique to form the structure shown in FIG.
And as shown in FIG. 14, the second layer wiring 23L2 is formed on the insulating film 19e. The second layer wiring 23L2 in the peripheral circuit region A has a connection hole 20 formed in the insulating film 19e.
It is electrically connected to the first layer wiring 23L1 through d.

The wiring width of the second layer wiring 23L2 is, for example, in the range of 0.3 μm to 0.5 μm, for example, 0.35 μm.
It is a degree. The wiring interval is, for example, in the range of 0.3 μm to 0.5 μm, and is, for example, about 0.35 μm.

Then, for example, SiO 2 is formed on the insulating film 19e.
After covering the second layer wiring 23L2 by depositing an insulating film 19f made of ₂ by the CVD method or the like, the insulating film 1
A connection hole is formed in 9f so that a part of the second layer wiring 23L2 is exposed in the same manner as described above.

Next, as shown in FIGS. 15 and 16, a conductor film 23L3a made of, for example, tungsten and a conductor film 2 made of an Al--Si--Cu alloy are formed on the insulating film 19f.
The laminated conductor film 23 is formed by depositing the conductor film 23L3c made of 3L3b and tungsten sequentially from the lower layer by a sputtering method or the like. As shown in FIG. 15, a connection hole 20e is formed in the insulating film 19f so that a part of the second layer wiring 23L2 is exposed.

Subsequently, a photoresist pattern 24b for wiring formation is formed on the laminated conductor film 23 by a photolithography technique, and then the laminated conductor film exposed from the photoresist pattern 24b is used as an etching mask. By removing 23 by etching, as shown in FIG. 17 and FIG.
The third layer wiring 23L3 is formed.

The process of forming the third layer wiring 23L3 will be described below with reference to FIGS. 19 to 22 along the flow chart of FIG.

FIG. 19 is an enlarged view of a main part of FIG. FIG.
As shown in FIG. 9, the laminated conductor film 23, as described above,
For example, it is composed of three conductor films 23L3a to 23L3c. A photoresist pattern 24b for wiring formation is formed on the upper surface of the laminated conductor film 23.

First, after the semiconductor substrate 10 having such a photoresist pattern 24b formed thereon is housed in the load lock portion 3a of the semiconductor manufacturing apparatus 1B shown in FIG.
The semiconductor substrate 10 is sent to the main etching processing section 5b and is subjected to etching processing (step 100 in FIG. 5).

In the main etching processing section 5b, the portion of the laminated conductor film 23 exposed from the photoresist pattern 24b is exposed by performing the plasma dry etching treatment on the semiconductor substrate 10 using the photoresist pattern 24b as an etching mask. Remove by etching. Examples of the reaction gas at this time are as follows.

That is, when the conductor film 23L3c of the third layer is etched and the conductor film 23L3c is tungsten or TiW, for example, SF ₆ + BCl ₃ gas is used. When the conductor film 23L3c is TiN, for example, S
F ₆ + BCl ₃ gas or SF ₆ + BCl ₃ + Cl ₂ gas is used.

When the second-layer conductor film 23L3b is etched, the conductor film 23L3b is Al or Al--Si--Cu.
When it is made of an alloy, for example, BCl ₃ + Cl ₂ gas is used.

Further, when the conductor film 23L3a of the first layer is tungsten or TiW when the conductor film 23L3a of the first layer is etched, for example, SF ₆ + BCl ₃ gas is added to N ₂ gas.
Is used. In addition, the conductor film 23L3a is made of Ti.
In the case of N, for example, BCl ₃ + Cl ₂ gas is used.

By such etching treatment, as shown in FIG.
As shown in, the third layer wiring 23L3 is formed on the insulating film 19f. At this time, a side film 25b is formed on the side surface of the third layer wiring 23L3. Side film 2
5b contains components such as carbon, Si, Al and Cu.

The wiring width of the third layer wiring 23L3 is, for example, in the range of 1.0 μm to 0.25 μm, and is 0.35 μm, for example.
m. The wiring interval is, for example, 1.0 μm to 0.25 μm.
The range is m, for example, about 0.35 μm.

Then, the semiconductor substrate 10 after the main etching treatment is taken out from the main etching treatment portion 5b and sent to the main ashing treatment portion 6a, and the semiconductor substrate 10 is subjected to the ashing treatment (step 101).

In the main ashing processing portion 6a, the photoresist pattern 24b which has become unnecessary is removed by performing plasma ashing processing on the semiconductor substrate 10. The ashing gas at this time, for example, O ₂ + H ₂ O or O ₂ in the gas or O ₂ + CF-based gas with the addition of gas containing OH groups are used. FIG. 21 shows a cross-sectional view of the main part of the semiconductor substrate 10 after this ashing process. At this stage, the side film 25b is not removed but left on the side surface of the third layer wiring 23L ₃ .

After that, the semiconductor substrate 10 for which the main ashing process has been completed is taken out from the main ashing process section 6a, and then sent to the sub-etching process section 7a, where the semiconductor substrate 10 is subjected to etching processing (step 102).

In the sub-etching portion 7a, the side film 25b left on the side surface of the third layer wiring 23L3 is removed by etching the semiconductor substrate 10 by plasma dry etching.
FIG. 22 shows a cross-sectional view of the main parts of the semiconductor substrate 10 after this treatment.

In the first embodiment, the following two processing conditions are set for this etching process.

First, the reaction gas is, for example, O ₂ / SF ₆
Gas, O ₂ / CHF ₃ gas or O ₂ / CF (eg C
F ₄ ) gas is used. That is, in Example 1, the side film 25b can be satisfactorily removed by a chemical action by using an etching gas having a high etching rate for the component forming the side film 25b.

Secondly, in this process, the semiconductor substrate 10
Lower electrode 7a5 (see FIG. 2) or cathode 7a for mounting
A high frequency voltage is applied to the semiconductor substrate 10 (see FIG. 3).
A bias voltage is applied to. This allows the side film 25b to be removed by a physical action such as a sputtering phenomenon.

As described above, in the first embodiment, since the side film 25b can be removed by both the chemical action and the physical action, the removability of the side film 25b can be improved. It is possible. Therefore, the reliability of the third layer wiring 23L3 can be improved, and the yield and reliability of the semiconductor integrated circuit device can be improved.

The result of the side film removability in this case is the same as that in FIG. That is, when the etching process of step 102 is not performed, the side film 25b
Remains.

As the reaction gas, for example, BCl ₃ /
When Cl ₂ gas is used, the side film 25b remains and the number of corrosions increases significantly. Here, the SEM (Scanning) of the wiring pattern around the semiconductor wafer when plasma dry etching treatment using a Cl ₂ -based gas is performed to remove the side film 25b
Electron Microscope) Photographs are shown in FIGS.
In this case, it was observed that the plasma SiN / CVD tungsten in the upper layer was scraped off, and the shoulder of the Al wiring was scraped off.

The side film 25b cannot be removed when O ₂ gas alone is used as the reaction gas.

As the reaction gas, for example, O ₂ / CH
When F ₃ gas is used, the side film 25b can be removed. However, in this case, a deposit may be generated due to the carbon component.

Further, as a reaction gas, for example, O ₂ / S is used.
When F ₆ gas was used, the side film 25b could be removed, and there was no deposition of deposits. Furthermore, in this case, the number of corrosions could be significantly reduced. This is considered to be due to the following two reasons. First, the fluorine component in the plasma replaces the Cl component on the surface of the third layer wiring 23L3 that induces corrosion. Secondly, the oxygen component oxidizes the passivation surface to passivate it. 22 of FIG.
Reference numeral 6 indicates this oxide film.

26 to 2 are SEM photographs of the wiring pattern around the semiconductor wafer when the plasma dry etching process using O ₂ / SF ₆ gas is performed.
8 shows. In this case, it was observed that the upper layer plasma SiN / CVD tungsten was slightly scraped, but the Al wiring was not scraped.

Further, FIG. 29 shows an SEM photograph when such etching treatment is not performed. In FIG. 29, it was possible to observe that the side film 25b peeled off during the wet etching treatment for removing the side film or the like was redeposited on the wiring. Side film 2
Since 5b also contains a conductive component such as Al, there is a risk of a short circuit in the wiring.

On the other hand, FIG. 30 shows an SEM photograph when such an etching process is performed. In FIG. 30, it could be observed that the side film was completely removed. Moreover, in this case, it was observed that the corrosion did not increase even if it was left in the atmosphere for 24 hours.

With respect to such an etching process, according to the result of examination by the present inventor, it was found that it is desirable to set the following conditions.

First, it is desirable that the flow rate ratio of SF ₆ gas, CHF ₃ gas, CF type gas or the like be, for example, about 1 to 25%. This is because if the gas flow rate ratio is less than 1%, only the O ₂ gas is used for etching and the side film cannot be removed. If the gas flow rate ratio is 25% or more, the conductor film 23L3c of the third layer wiring 23L3 is formed. This is because the amount of shavings increases and undercuts and the like occur.

Secondly, the substrate bias voltage applied to the semiconductor substrate 10 is preferably about 100V to 300V, for example. This is because if the substrate bias voltage is lower than 100V, the ion attack on the side film 25b is insufficient and the side film 25b cannot be removed satisfactorily. If it is higher than 300V, the insulating film 19f and the conductor film 23L3c are also removed. Because it will be removed.

Thirdly, the temperature of the semiconductor substrate 10 during processing is
For example, it is desirable to set the temperature as low as 0 ° C to 80 ° C. This is because if the temperature is too high, the insulating film 19
This is to prevent the removal of f, the peeling of the third layer wiring 23L3, and the segregation of Cu or Si in the wiring.

Next, the semiconductor substrate 10 after such etching treatment is taken out from the sub-etching treatment portion 7a and sent to the sub-etching treatment portion 8a, and the semiconductor substrate 10 is subjected to etching treatment (step 103).

In the sub-etching processing portion 8a, the side film remaining on the semiconductor substrate 10 is removed by etching by performing the wet etching processing on the semiconductor substrate 10.

At this time, in the first embodiment, the side film 25 is formed in the sub-etching processing portion 7a described above.
Since the removal process of b has already been performed, the side film 2
The side film 25a can be removed easily and in a short time, as compared with the case where 5b is removed only by wet etching.

Subsequently, the semiconductor substrate 10 after such etching processing is taken out from the sub-etching processing portion 8a and sent to the sub-ashing processing portion 9a, and the semiconductor substrate 10 is subjected to ashing processing (step 104).

In the sub ashing processing section 9a, in order to prevent contamination and damage due to charge-up, for example, an optical ashing processing is performed to oxidatively decompose and remove the photoresist by using, for example, ultraviolet light and O ₃ gas. .

After passing through the above steps 100 to 104, the semiconductor substrate 10 is taken out from the sub ashing processing section 9a and sent to the unloading section 4a, and the third layer wiring 23
The L3 forming process is ended.

Finally, as shown in FIGS. 31 and 32, a surface protective film 27 made of, for example, SiO ₂ is deposited on the insulating film 19f by the CVD method or the like to cover the third layer wiring 23L3. .

As described above, according to the first embodiment, the following effects can be obtained.

(1). After the dry etching treatment for patterning the connection hole and the wiring, for example, O ₂ / SF ₆ gas, O ₂ / CHF ₃ gas or O ₂ / CF (for example CF).
₄ ) In dry etching treatment for patterning connection holes and wirings by performing plasma dry etching treatment on the semiconductor substrate 10 using a system gas and applying a substrate bias voltage to the semiconductor substrate 10. The removability of the side films 25a and 25b formed on the inner surface of the connection hole and the side surface of the wiring can be significantly improved.

(2) Since the above (1) can improve the reliability of the wiring connection in the connection hole, the yield and reliability of the semiconductor integrated circuit device can be improved.

(3). Due to the above (1), it is possible to reduce wiring short-circuit defects due to the peeled side film 25b, so that it is possible to improve the reliability of wiring.
It is possible to improve the yield and reliability of the semiconductor integrated circuit device.

(4) Due to the above (1), the wet etching time after the dry etching processing for patterning the connection hole and the wiring can be significantly shortened. Therefore, the throughput of the semiconductor integrated circuit device can be improved.

(5). After the dry etching treatment for patterning the connection hole and the wiring, for example, O ₂ / SF ₆ , O
_{By using 2} / CHF ₃ gas or O ₂ / CF (for example, CF ₄ ) based gas, and subjecting the semiconductor substrate 10 to a plasma dry etching treatment with a substrate bias voltage applied, Since the fluorine component in the plasma replaces the Cl component on the surface of the wiring that causes corrosion and the oxygen component oxidizes the surface of the wiring to passivate it, it is possible to significantly reduce the wiring corrosion.
Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.

(6). By the above (5), the time limit for leaving the semiconductor substrate 10 until the wet etching process can be extended. Further, by performing main etching treatment, main ashing treatment, and sub-etching treatment using O ₂ / SF _6, etc. under continuous vacuum, the semiconductor substrate 1
Since the anticorrosion property of 0 can be further improved, the time limit for leaving the semiconductor substrate 10 thereafter can be further extended. For this reason, it is possible to improve the workability of the worker in the semiconductor manufacturing line, such as simplifying the management of the semiconductor substrate 10.

(7) The main etching process, the main ashing process, the sub-etching process, and the sub-ashing process can be performed in different processing parts, respectively, so that the generation of foreign matters such as reaction products generated during the etching process. Can be reduced, and stable processing can be realized.

(Embodiment 2) FIG. 33 is a flow chart showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.
FIG. 34 is an explanatory view of a semiconductor manufacturing apparatus used in this embodiment, and FIGS. 35 to 38 are cross-sectional views of essential parts in the manufacturing process of the semiconductor integrated circuit device of this embodiment.

In the second embodiment, the main ashing process (step 101) and the sub-etching process (step 102) shown in FIG. 5 of the first embodiment are reversed as shown in FIG.

In this case as well, the semiconductor manufacturing apparatuses 1A and 1B used in the first embodiment (see FIGS. 1 and 4) may be used, but in the second embodiment, for example, the semiconductor manufacturing as shown in FIG. The device 1C is used.

That is, in this semiconductor manufacturing apparatus 1C, one sub-etching processing section 7b has a structure capable of performing sub-etching processing for removing the side film and main ashing processing for removing the photoresist. ing.

This has a structure in which a substrate bias voltage can be applied to an electrode on which a semiconductor substrate is mounted in an ashing apparatus, and a reaction gas used in side film etching processing can be supplied into the processing chamber. It is configured by

The manufacturing method of the semiconductor integrated circuit device according to the second embodiment will be described below with reference to FIGS. 34 to 38 along the flow chart of FIG. 33 by taking the wiring forming method as an example.

FIG. 35 is an enlarged view of a main part of FIG. FIG.
As shown in FIG. 5, the laminated conductor film 23, as described above,
For example, it is composed of three conductor films 23L3a to 23L3c. A photoresist pattern 24b for wiring formation is formed on the upper surface of the laminated conductor film 23.

First, the semiconductor substrate 10 on which such a photoresist pattern 24b is formed is housed in the load lock portion 3a of the semiconductor manufacturing apparatus 1C shown in FIG. 34, and then sent to the main etching processing portion 5b to be transferred to the semiconductor substrate. 1
0 is subjected to an etching process (step 200 in the figure).

In the main etching processing portion 5b, the semiconductor substrate 10 is subjected to plasma dry etching processing using the photoresist pattern 24b as an etching mask to remove the portion of the laminated conductor film 23 exposed from the photoresist pattern 24b. Remove by etching. The reaction gas at this time is, for example, as follows.

That is, when the third conductive film 23L3c is etched and the conductive film 23L3c is tungsten or TiW, for example, SF ₆ + BCl ₃ gas is used. When the conductor film 23L3c is TiN, for example, S
F ₆ + BCl ₃ gas or SF ₆ + BCl ₃ + Cl ₂ gas is used.

When the second-layer conductor film 23L3b is etched, the conductor film 23L3b is Al or Al-Si-Cu.
When it is made of an alloy, for example, BCl ₃ + Cl ₂ gas is used.

Further, when the conductor film 23L3a of the first layer is tungsten or TiW when the conductor film 23L3a of the first layer is etched, for example, SF ₆ + BCl ₃ gas is added with N ₂ gas.
Is used. In addition, the conductor film 23L3a is made of Ti.
In the case of N, for example, BCl ₃ + Cl ₂ gas is used.

As a result of such etching treatment, FIG.
As shown in, the third layer wiring 23L3 is formed on the insulating film 19f. At this time, a side film 25b is formed on the side surface of the third layer wiring 23L3. Side film 2
5b contains components such as carbon, Si, Al and Cu.

The wiring width of the third layer wiring 23L3 is, for example, in the range of 1.0 μm to 0.25 μm, and is 0.35 μm, for example.
m. The wiring interval is, for example, 1.0 μm to 0.25 μm.
The range is m, for example, about 0.35 μm.

Subsequently, the semiconductor substrate 10 after the main etching treatment is taken out from the main etching treatment portion 5b and then sent to the sub-etching treatment portion 7b to perform the etching treatment on the semiconductor substrate 10 (step 201).

In the sub-etching portion 7b, the side film 25b left on the side surface of the third-layer wiring 23L3 is removed by etching the semiconductor substrate 10 by plasma dry etching.
FIG. 37 shows a cross-sectional view of the main parts of the semiconductor substrate 10 after this treatment.

In the second embodiment, the following two processing conditions are set for this etching process.

First, the reaction gas is, for example, O ₂ / SF ₆
Gas, O ₂ / CHF ₃ gas or O ₂ / CF (eg C
F ₄ ) gas is used. That is, in the second embodiment, the side film 25b can be satisfactorily removed by the chemical action by using the etching gas having a high etching rate for the component forming the side film 25b.

Secondly, in this process, the semiconductor substrate 10
Lower electrode 7a5 (see FIG. 2) or cathode 7a for mounting
A high frequency voltage is applied to the semiconductor substrate 10 (see FIG. 3).
A bias voltage is applied to. This allows the side film 25b to be removed by a physical action such as a sputtering phenomenon.

As described above, also in the second embodiment, since the side film 25b can be removed by both the chemical action and the physical action, the removability of the side film 25a can be improved. It is possible. Therefore, the reliability of the third layer wiring 23L3 can be improved, and the yield and reliability of the semiconductor integrated circuit device can be improved.

The result of the side film removability in this case is the same as that in FIG. That is, when O ₂ / CHF ₃ gas, for example, is used as the reaction gas, the side film 25b can be removed. However,
In this case, a deposit may be produced due to the carbon component.

Further, as the reaction gas, for example, O ₂ / SF is used.
_{When 6} gas was used, the side film 25b could be removed, and no deposits were deposited. Further, in the case of SF ₆ , since carbon is not contained, the amount of abrasion of the underlying insulating film 19f could be reduced. Furthermore, in this case, the number of corrosions could be significantly reduced. This is considered to be due to the following two reasons. First, the fluorine component in the plasma replaces the Cl component on the surface of the third layer wiring 23L3 that induces corrosion. Secondly, the oxygen component oxidizes the passivation surface to passivate it. Reference numeral 26 in FIG. 37 shows this oxide film.

According to the results of the study conducted by the present inventor on such an etching process, it was found that it is desirable to set the following conditions.

First, it is desirable that the flow rate ratio of SF ₆ gas, CHF ₃ gas, CF gas or the like be, for example, about 1 to 25%. This is because if the gas flow rate ratio is less than 1%, only the O ₂ gas is used for etching and the side film cannot be removed. If the gas flow rate ratio is 25% or more, the conductor film 23L3c of the third layer wiring 23L3 is formed. This is because the amount of shavings increases and undercuts and the like occur.

Secondly, the substrate bias voltage applied to the semiconductor substrate 10 is preferably about 100V to 300V, for example. This is because if the substrate bias voltage is lower than 100V, the ion attack on the side film 25b is insufficient and the side film 25b cannot be removed satisfactorily. If it is higher than 300V, the insulating film 19f and the conductor film 23L3c are also removed. Because it will be removed.

Third, the temperature of the semiconductor substrate 10 during processing is
For example, it is desirable to set the temperature as low as 0 ° C to 80 ° C. This is because if the temperature is too high, the insulating film 19
This is to prevent the removal of f, the peeling of the third layer wiring 23L3, and the segregation of Cu or Si in the wiring.

After the etching process is completed, ashing process is performed on the semiconductor substrate 10 in the processing chamber (step 202).

That is, in this process, the semiconductor substrate 10 is subjected to the plasma ashing process to remove the unnecessary photoresist pattern 24b. As the ashing gas at this time, for example, O
₂ / SF ₆ gas, O ₂ / CHF ₃ gas or O ₂ / CF
(For example, CF ₄ ) -based gas may be used as it is, or those gases may be once exhausted and, for example, O ₂ + H ₂ O or a gas obtained by adding a gas containing an OH group to O ₂ may be used. However, in this case, since the purpose is normal photoresist ashing, for example, the high frequency substrate bias voltage is not applied.

Next, the semiconductor substrate 10 after such etching treatment is taken out from the sub-etching treatment portion 7b and sent to the sub-etching treatment portion 8a, and the semiconductor substrate 10 is subjected to the etching treatment (step 203).

In the sub-etching processing portion 8a, the side film left on the semiconductor substrate 10 is removed by etching by performing the wet etching processing on the semiconductor substrate 10.

At this time, in the second embodiment, the side film 25 is formed in the sub-etching portion 7b described above.
Since the removal process of b has already been performed, the side film 2
The side film 25b can be removed easily and in a short time as compared with the case where 5b is removed only by wet etching. FIG. 38 shows a cross-sectional view of the main part of the semiconductor substrate 10 after this treatment.

Subsequently, the semiconductor substrate 10 after such etching treatment is taken out from the sub-etching treatment portion 8a and sent to the sub-ashing treatment portion 9a, and the semiconductor substrate 10 is subjected to ashing treatment (step 204).

In the sub ashing processing section 9a, in order to prevent contamination and damage due to charge-up, for example, an optical ashing processing is performed to oxidatively decompose and remove the photoresist by using, for example, ultraviolet light and O ₃ gas. .

After passing through the above steps 200 to 204, the semiconductor substrate 10 is taken out from the sub ashing processing section 9a and sent to the unloading section 4a, and the third layer wiring 23
The L3 forming process is ended. The subsequent processing is the same as that in the first embodiment.

As described above, according to the second embodiment, the following effects can be obtained in addition to the effects obtained in (1) to (6) of the first embodiment.

That is, by performing the plasma dry etching process for removing the side film 25b and the ashing process for removing the photoresist in the same processing section, it is possible to reduce the number of manufacturing steps of the semiconductor integrated circuit device, and to improve the overall process. Since the semiconductor manufacturing time can be shortened, the throughput of manufacturing the semiconductor integrated circuit device can be further improved.

(Embodiment 3) FIG. 39 is a flow chart showing a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 40 is an explanatory diagram of a semiconductor manufacturing apparatus used in this embodiment, and FIGS. 41 to 44 are cross-sectional views of essential parts in the manufacturing process of the semiconductor integrated circuit device of this embodiment.

In the third embodiment, as shown in FIG. 39, the dry etching process for removing the side film is the final process of the pattern forming process.

In this case as well, the semiconductor manufacturing apparatuses 1A and 1B used in the first embodiment (see FIGS. 1 and 4) may be used, but in the third embodiment, for example, a semiconductor manufacturing apparatus as shown in FIG. The device 1D is used.

In this semiconductor manufacturing apparatus 1D, in one main etching processing section 5c, main etching processing for forming a pattern of connection holes and wiring,
The structure is such that a main ashing process for removing the photoresist can be performed.

The method for manufacturing the semiconductor integrated circuit device according to the third embodiment will be described below with reference to FIGS. 40 to 44 along the flow chart of FIG. 39 by taking the wiring forming method as an example.

FIG. 41 is an enlarged view of a main part of FIG. FIG.
As shown in FIG. 1, the laminated conductor film 23, as described above,
For example, it is composed of three conductor films 23L3a to 23L3c. A photoresist pattern 24b for wiring formation is formed on the upper surface of the laminated conductor film 23.

First, after the semiconductor substrate 10 having such a photoresist pattern 24b formed therein is housed in the load lock portion 3a of the semiconductor manufacturing apparatus 1D shown in FIG. 40, it is sent to the main etching processing portion 5c and the semiconductor substrate 1
An etching process is performed on 0 (step 300 in the figure).

In this main etching processing portion 5c, the semiconductor substrate 10 is subjected to plasma dry etching processing using the photoresist pattern 24b as an etching mask to remove the portion of the laminated conductor film 23 exposed from the photoresist pattern 24b. Remove by etching. Examples of the reaction gas at this time are as follows.

That is, when the third conductor film 23L3c is etched and the conductor film 23L3c is tungsten or TiW, for example, SF ₆ + BCl ₃ gas is used. When the conductor film 23L3c is TiN, for example, S
F ₆ + BCl ₃ gas or SF ₆ + BCl ₃ + Cl ₂ gas is used.

When the second-layer conductor film 23L3b is etched, the conductor film 23L3b may be Al or Al-Si-Cu.
When it is made of an alloy, for example, BCl ₃ + Cl ₂ gas is used.

Further, when the conductor film 23L3a of the first layer is made of tungsten or TiW when the conductor film 23L3a of the first layer is etched, for example, SF ₆ + BCl ₃ gas is added with N ₂ gas.
Is used. In addition, the conductor film 23L3a is made of Ti.
In the case of N, for example, BCl ₃ + Cl ₂ gas is used.

By the etching treatment as described above, FIG.
As shown in, the third layer wiring 23L3 is formed on the insulating film 19f. At this time, a side film 25b is formed on the side surface of the third layer wiring 23L3. Side film 2
5b contains components such as carbon, Si, Al and Cu.

The wiring width of the third layer wiring 23L3 is, for example, in the range of 1.0 μm to 0.25 μm, and is 0.35 μm, for example.
m. The wiring interval is, for example, 1.0 μm to 0.25 μm.
The range is m, for example, about 0.35 μm.

Then, after such etching process is completed, the gas in the process chamber of the main etching process section 5c is exhausted, and the semiconductor substrate 10 is subjected to the ashing process in the process chamber (step 301).

That is, at this time, by performing the plasma ashing process on the semiconductor substrate 10,
The unnecessary photoresist pattern 24b is removed. As the ashing gas at this time, for example, O ₂ + H
A gas obtained by adding a gas containing an OH group to ₂ O or O ₂ is used.

After that, the semiconductor substrate 10 after the ashing process is taken out from the main etching process part 5c,
The semiconductor substrate 10 is sent to the sub-etching section 8a and is subjected to etching processing (step 302).

In this sub-etching process portion 8a, the side film 2 on the semiconductor substrate 10 is processed by performing the wet etching process on the semiconductor substrate 10.
5b is removed by etching. Semiconductor substrate 1 after this treatment
43 is a sectional view showing the main part of No. 0.

At this time, in the third embodiment, since the plasma dry etching process for removing the side film 25b is finally performed, the wet etching process is performed as compared with the case where the side film 25b is removed only by the wet etching process. It is possible to shorten the time.

Next, the semiconductor substrate 10 after such etching treatment is taken out from the sub-etching treatment portion 8a and sent to the sub-ashing treatment portion 9a, and the semiconductor substrate 10 is subjected to ashing treatment (step 303).

In the sub ashing processing section 9a, in order to prevent contamination and damage due to charge-up, for example, an optical ashing processing is performed to oxidatively decompose and remove the photoresist using, for example, ultraviolet light and O ₃ gas. .

Subsequently, the semiconductor substrate 10 on which such sub-ashing processing has been completed is sent to the sub-etching processing section 7a, and the semiconductor substrate 10 is subjected to etching processing (step 304).

In the sub-etching portion 7a, the side film 25b left on the side surface of the third layer wiring 23L3 is removed by etching by performing plasma dry etching treatment on the semiconductor substrate 10.
FIG. 44 shows a cross-sectional view of the main parts of the semiconductor substrate 10 after this treatment.

In this third embodiment, the following two processing conditions are set for this etching process.

First, the reaction gas is, for example, O ₂ / SF ₆
Gas, O ₂ / CHF ₃ gas or O ₂ / CF based gas is used. That is, in the second embodiment, the side film 25 is formed by using the etching gas having a high etching rate for the components forming the side film 25b.
It is possible to favorably remove b by a chemical action.

Secondly, in this processing, the semiconductor substrate 10
Lower electrode 7a5 (see FIG. 2) or cathode 7a for mounting
A high frequency voltage is applied to the semiconductor substrate 10 (see FIG. 3).
A bias voltage is applied to. This allows the side film 25b to be removed by a physical action such as a sputtering phenomenon.

As described above, in the third embodiment, since the side film 25b can be removed by both the chemical action and the physical action, the removability of the side film 25b can be improved. It is possible. Therefore, the reliability of the third layer wiring 23L3 can be improved, and the yield and reliability of the semiconductor integrated circuit device can be improved.

The results of the side film removability in this case are the same as those in FIG. That is, when O ₂ / CHF ₃ gas, for example, is used as the reaction gas, the side film 25b can be removed. However,
In this case, a deposit may be produced due to the carbon component.

The reaction gas may be, for example, O ₂ / SF.
_{When 6} gas was used, the side film 25b could be removed, and no deposits were deposited. Further, since SF ₆ does not contain carbon, the amount of abrasion of the underlying insulating film 19f could be reduced. Furthermore, in this case, the number of corrosions could be significantly reduced. This is considered to be due to the following two reasons. First, the fluorine component in the plasma replaces the Cl component on the surface of the third layer wiring 23L3 that induces corrosion. Secondly, the oxygen component oxidizes the passivation surface to passivate it. Reference numeral 26 in FIG. 44 shows this oxide film.

According to the results of the study conducted by the present inventor on such an etching process, it was found that it is desirable to set the following conditions.

First, it is desirable that the flow rate ratio of SF ₆ gas, CHF ₃ gas, CF type gas or the like be, for example, about 1 to 25%. This is because if the gas flow rate ratio is less than 1%, only the O ₂ gas is used for etching and the side film cannot be removed. If the gas flow rate ratio is 25% or more, the conductor film 23L3c of the third layer wiring 23L3 is formed. This is because the amount of shavings increases and undercuts and the like occur.

Secondly, the substrate bias voltage applied to the semiconductor substrate 10 is desirably about 100V to 300V, for example. This is because if the substrate bias voltage is lower than 100V, the ion attack on the side film 25b is insufficient and the side film 25b cannot be removed satisfactorily. If it is higher than 300V, the insulating film 19f and the conductor film 23L3c are also removed. Because it will be removed.

Thirdly, the temperature of the semiconductor substrate 10 during processing is
For example, it is desirable to set the temperature as low as 0 ° C to 80 ° C. This is because if the temperature is too high, the insulating film 19
This is to prevent the removal of f, the peeling of the third layer wiring 23L3, and the segregation of Cu or Si in the wiring.

After passing through the above steps 300 to 304, the semiconductor substrate 10 is taken out from the sub ashing processing section 9a and sent to the unloading section 4a, and the third layer wiring 23
The L3 forming process is ended. The subsequent processing is the same as that in the first embodiment.

As described above, according to the third embodiment, it is possible to obtain the same effects as the effects obtained in (1) to (6) of the first embodiment.

Although the invention made by the present inventor has been specifically described based on the above embodiments, the present invention is not limited to the above first to third embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the first embodiment, the case where each processing unit is provided separately has been described, but the present invention is not limited to this, and for example, a structure in which the main etching process and the main ashing process can be performed in the same processing unit. Also good.

The main ashing process and the dry etching process for removing the side film may be performed in the same processing section. In this case, for example, O ₂ / SF ₆ , O ₂ / CHF, or O ₂ / CF-based (for example, CF ₄ ) gas is used as a processing gas in both the ashing process and the dry etching process, and the high frequency substrate bias is used in the ashing process. The process is performed without applying a voltage. In this case, by performing the ashing process and the dry etching process at the same time in the same processing chamber, the manufacturing process of the semiconductor integrated circuit device can be reduced and the overall manufacturing time of the semiconductor integrated circuit device can be shortened. It is possible to improve the throughput of device manufacturing.

In the second embodiment, the case where the dry etching process for removing the side film and the main ashing process are performed in the same processing part has been described, but the present invention is not limited to this. ,
For example, the main etching process and the dry etching process for removing the side film may be performed in the same processing unit.

Further, as in the semiconductor manufacturing apparatus 1E of FIG. 45, the sub-etching processing section 7a for performing the plasma dry etching processing for removing the side film may be prepared separately from the cluster tool. In this case, the conventional pattern forming cluster tool can be used as it is.

Further, in the first to third embodiments, the case where the semiconductor manufacturing apparatus having the structure in which the process chamber is arranged around the central transfer section is used has been described, but the present invention is not limited to this. As shown by 46, the semiconductor manufacturing apparatus 1 having a structure in which the main etching processing section 5a, the main ashing processing section 6a, the sub etching processing sections 7a and 8a, and the sub ashing processing section 9a are arranged on a straight line.
You may use F. The processing units are mechanically connected to each other via the transport unit 2b.

In the first to third embodiments, the case where the present invention is applied to the case of patterning a metal film has been described, but the present invention is not limited to this. For example, in the case of patterning a polysilicon film. Can also be applied.

In the first to third embodiments, the case where the present invention is applied to the method for manufacturing the semiconductor integrated circuit device having the MOS • FET has been described. However, the present invention is not limited to this and various applications are possible. It is possible, for example, a method for manufacturing a semiconductor integrated circuit device having a bipolar transistor, a BiCMOS (Bipolar Compliment) which is a combination of a MOS • FET and a bipolar transistor.
The present invention can be applied to a method of manufacturing a semiconductor integrated circuit device having an (ary MOS) circuit.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
The case where the method is applied to the method of manufacturing a semiconductor integrated circuit device having M has been described, but the present invention is not limited to this and can be variously applied. For example, a semiconductor integrated circuit device having an SRAM (Static RAM), a semiconductor integrated circuit having a logic circuit. It can also be applied to a method of manufacturing a device, a method of manufacturing another semiconductor integrated circuit device such as a method of manufacturing a semiconductor integrated circuit device having a logic circuit such as a memory with logic, and a memory circuit.

[0276]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) According to the present invention, an O ₂ / SF ₆ , O ₂ / CHF ₃ or O ₂ / CF based gas is used as an etching gas in a state where a high frequency substrate bias voltage is applied to the substrate to be processed. By performing the plasma dry etching process, the protective film formed on the side surface of the film to be processed at the time of the main etching process can be removed by both the chemical action and the physical action. It becomes possible to improve the removability of the protective film.

(2) According to the above (1), by using the present invention in the method for manufacturing a semiconductor integrated circuit device, the residual protective film may short-circuit adjacent wirings, or the protective film remaining in the connection hole may be eliminated. Since it is possible to reduce the occurrence of wiring connection failure in the connection hole, it is possible to improve the yield and reliability of the semiconductor integrated circuit device.

(3). By performing the plasma dry etching treatment of the above (1), it is possible to greatly reduce the wet etching treatment time which has been performed for removing the protective film.

(4) According to the above (3), by using the present invention in the method for manufacturing a semiconductor integrated circuit device, the throughput of manufacturing the semiconductor integrated circuit device can be improved.

(5). By using a gas containing O ₂ as an etching gas in the plasma dry etching treatment of the above (1), the surface of the conductor film can be oxidized and passivated during the plasma dry etching treatment. Therefore, the corrosion resistance of the conductor film pattern can be improved.

(6). By using a gas having fluorine such as SF ₆ as an etching gas in the plasma dry etching treatment of the above (1), chlorine on the surface of the conductor film is changed to fluorine during the plasma dry etching treatment. Since it can be replaced with, it is possible to improve the corrosion resistance of the conductor film pattern.

(7) According to the above (5) and (6), by using the present invention for the method for forming the electrode wiring pattern of the semiconductor integrated circuit device, the corrosion resistance of the electrode wiring pattern can be improved and the electrode wiring pattern can be improved. It is possible to improve the reliability of the wiring.

(8). Due to the above (7), the yield and reliability of the semiconductor integrated circuit device can be improved.

(9). Because of the above (7), it is possible to extend the leaving time limit until the wet etching treatment.
It is possible to improve workability of a worker in a semiconductor product manufacturing line.

(10). According to the present invention, an ashing treatment function for ashing and removing the resist pattern, and O ₂ / SF ₆ and O ₂ / O ₂ / O ₂ as etching gas in a state where a high frequency substrate bias voltage is applied to the semiconductor substrate are used. By providing a processing unit having a first sub-etching processing function for performing plasma dry etching processing using CHF ₃ or O ₂ / CF-based gas, the ashing processing and the first
Since the sub-etching process can be performed simultaneously in the same processing unit, the number of processing steps can be reduced and the overall processing time can be shortened.

(11) According to the above (10), by using the present invention in the method for manufacturing a semiconductor integrated circuit device, the throughput of manufacturing the semiconductor integrated circuit device can be further improved.

(12) According to the present invention, the transfer function for transferring the substrate to be processed to each processing section and the vacuum maintaining function for maintaining the vacuum state in the transfer chamber for transferring the substrate to be processed are provided. By providing the transporting part, the transporting part between the processing parts can be placed under vacuum, so that the anticorrosion property of the conductor film pattern or the like can be further improved.

(13) From the above (12), by using the present invention for the method of forming an electrode wiring pattern of a semiconductor integrated circuit device, the corrosion resistance of the electrode wiring pattern can be further improved, and the reliability of the electrode wiring can be improved. Since the reliability can be improved, the yield and reliability of the semiconductor integrated circuit device can be improved.

(14). Due to the above (12), it is possible to extend the leaving time limit until the wet etching process, so that it is possible to improve the workability of the worker in the manufacturing line.

(15) According to the present invention, by setting the high frequency substrate bias voltage to 100 V or more during the first sub-etching treatment, a sufficient ion attack amount to the side film can be obtained. It becomes possible to improve. Further, at that time, by setting the high frequency substrate bias voltage to 300 V or less, it becomes possible to prevent the base insulating film and the like from being excessively shaved.

(16). By setting the substrate temperature at the time of the first sub-etching process to 0 ° C. to 80 ° C., it is possible to prevent the base insulating film from being excessively shaved, and also to separate the conductive film and segregate atoms in the conductive film. Can be prevented.

(17). The removability of the protective film can be improved by setting the flow rate ratio of SF ₆ , CHF ₃ or CF based gas in the etching gas during the first sub-etching treatment to 1% or more. It will be possible. Further, by setting the flow rate ratio of SF ₆ , CHF ₃ or CF type gas in the etching gas to 25% or less, it becomes possible to prevent the conductor film from being over-cut or undercut.

(18). From the above (15) to (17), by using the present invention in the method for manufacturing a semiconductor integrated circuit device, it is possible to further improve the yield and reliability of the semiconductor integrated circuit device. .

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a semiconductor manufacturing apparatus that is an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a sub-etching processing unit for removing a protective film of the semiconductor manufacturing apparatus of FIG.

FIG. 3 is an explanatory diagram of a modified example of a sub-etching processing unit for removing a protective film of the semiconductor manufacturing apparatus of FIG.

FIG. 4 is an explanatory diagram of a semiconductor manufacturing apparatus that is an embodiment of the present invention.

FIG. 5 is a flowchart showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

6 is a cross-sectional view of essential parts of the semiconductor integrated circuit device in a manufacturing process of the semiconductor integrated circuit device of FIG.

7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing process of the semiconductor integrated circuit device of FIG.

8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIGS. 6 and 7;

9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIG. 8;

10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIG. 9;

11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIG. 10;

FIG. 12 is a graph showing the removability of a protective film according to the method for manufacturing a semiconductor integrated circuit device of the present invention.

13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during the manufacturing process of the semiconductor integrated circuit device of FIG. 5 subsequent to FIG. 11;

14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIG. 11;

15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during the manufacturing process of the semiconductor integrated circuit device of FIG. 5 subsequent to FIGS. 13 and 14;

16 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIGS. 13 and 14;

17 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIGS. 15 and 16;

18 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIGS. 15 and 16;

19 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIGS. 17 and 18;

20 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIG. 19;

21 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5, following FIG. 19;

22 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIG. 21;

FIG. 23 is an SEM (Scanning Electron Microscope) photograph when the protective film on the sidewall of the conductor film is removed by plasma dry etching using a Cl ₂ -based gas.

FIG. 24 is an SEM photograph when the protective film on the sidewall of the conductor film is removed by plasma dry etching using a Cl ₂ -based gas.

FIG. 25 is an SEM photograph when the protective film on the sidewall of the conductor film is removed by plasma dry etching using a Cl ₂ -based gas.

FIG. 26 is an SEM photograph when the protective film on the side wall of the conductor film is removed by plasma dry etching using O ₂ / SF ₆ system gas.

FIG. 27 is an SEM photograph when the protective film on the side wall of the conductor film is removed by plasma dry etching using O ₂ / SF ₆ system gas.

FIG. 28 is an SEM photograph when the protective film on the side wall of the conductor film is removed by plasma dry etching treatment using O ₂ / SF ₆ system gas.

FIG. 29 is an SEM photograph of a wiring portion before the protective film removing process of the present invention is performed.

FIG. 30 is an SEM photograph of a wiring portion after the protective film removing process of the present invention is performed.

31 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during the manufacturing process of the semiconductor integrated circuit device of FIG. 5 subsequent to FIG. 22;

32 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 5 subsequent to FIG. 22;

FIG. 33 is a flowchart showing manufacturing steps of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 34 is an explanatory diagram of a semiconductor manufacturing apparatus used in another embodiment of the present invention.

FIG. 35 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

36 is a cross-sectional view of essential parts in the process of manufacturing the semiconductor integrated circuit device of FIG. 33 subsequent to FIG. 35.

37 is a cross-sectional view of essential parts in the process of manufacturing the semiconductor integrated circuit device of FIG. 33, which is subsequent to FIG. 36.

38 is a cross-sectional view of essential parts in the process of manufacturing the semiconductor integrated circuit device of FIG. 33 subsequent to FIG. 37.

FIG. 39 is a flowchart showing manufacturing steps of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 40 is an explanatory diagram of a semiconductor manufacturing apparatus used in the manufacturing process of FIG. 39.

41 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step of the semiconductor integrated circuit device of FIG. 39. FIG.

42 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during the manufacturing process of the semiconductor integrated circuit device of FIG. 39, which is subsequent to FIG. 41;

43 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during the manufacturing process of the semiconductor integrated circuit device of FIG. 39, which is subsequent to FIG. 42;

44 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during the manufacturing process of the semiconductor integrated circuit device of FIG. 39, which is subsequent to FIG. 43;

FIG. 45 is an explanatory diagram of a semiconductor manufacturing apparatus that is another embodiment of the present invention.

FIG. 46 is an explanatory diagram of a semiconductor manufacturing apparatus according to another embodiment of the present invention.

[Explanation of symbols]

1A to 1F Semiconductor manufacturing equipment 2a Central transfer section 2b Transfer section 3a Load lock section 4a Unload section 5a, 5b, 5c Main etching processing section 6a Main ashing processing section 7a, 7b Sub etching processing section (first sub etching processing section) 7a1 Magnetron Oscillator 7a2 Vent Waveguide 7a3 Plasma Etching Processing Section 7a4 Discharge Tube 7a5 Lower Electrode 7a6 High Frequency Power Supply 7a7 Temperature Control Liquid Supply Tube 7a8 Exhaust Port 7a9 Electromagnet 7a10 Cathode 7a11 Matching Machine 7a13 Plasma Processing Power Supply 7a11 7a14 Exhaust port 7a15 Anode 7a16 Ground part 7a17 Insulator 8a Sub-etching part 9a Sub-ashing part 10 Semiconductor substrate 11p p-well 11n n-well 12p, 12n Channel stopper layer 13 Field insulating film 14p, 14n Semi-conducting Region 15 n-channel type MOS · FET 15a semiconductor region 15a1 n ^- type semiconductor region 15a2 n ⁺ type semiconductor region 15b a gate insulating film 15g gate electrode 16 capacitors 16a lower electrode 16a1 ～16A3 fin portion 16b upper electrode 16c capacitor insulating film 17 insulating film 18 insulating film 19a~19f insulating film 20a~20e connection hole 21 n channel type MOS · FET 21a semiconductor region 21a1 n ^- type semiconductor region 21a2 n ⁺ type semiconductor region 21b a gate insulating film 21g gate electrode 22 p-channel type MOS · FET 22a semiconductor region 22a1 p ^- type semiconductor region 22a2 p ⁺ type semiconductor region 22b a gate insulating film 22g gate electrode 23 laminated conductor film 23BL bit line 23BL1 bit line connection unit 23L1 first layer wiring 23L1a~23L1c conductors 23L2 second layer wiring 23L3 third layer wiring 23L3a~23L3c conductive film 24a, 24b photoresist pattern 25a, 25b side film (protective film) 26 oxide film 27 surface protective film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Zenzo Torii 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Michio Nishimura 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan Texas Instruments Incorporated (72) Inventor Go Matsui 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Nihon Textus Instruments Co., Ltd.

Claims (19)

[Claims] 1. A pattern forming method comprising the following steps in forming a predetermined pattern on a substrate to be processed by processing a film to be processed formed on a substrate to be processed. (A) After a resist pattern having a predetermined shape is formed on the film to be processed, a dry etching process is performed on the substrate to be processed using the resist pattern as an etching mask, so that the resist pattern is covered and is not removed by etching. A step of etching away a portion of the film to be processed exposed from the resist pattern in a state where a protective film is formed on the side surface of the film to be processed left over. (B) A step of removing the resist pattern. (C) O ₂ / SF ₆ , O ₂ / O ₂ as etching gas in the state where a high frequency substrate bias voltage is applied to the substrate to be processed.
A step of performing a plasma dry etching process using a CHF ₃ or O ₂ / CF gas. (D) A step of performing a wet etching process on the substrate to be processed. 2. A pattern forming apparatus for forming a predetermined pattern on a substrate to be processed by processing a film to be processed formed on the substrate to be processed, comprising: A pattern forming device. (A) dry etching the substrate to be processed by using the resist pattern formed on the film to be processed as an etching mask to etch away the film to be processed exposed from the resist pattern; A main etching processing part for forming the predetermined pattern. (B) said as an etching gas in a state of applying a high-frequency substrate bias voltage to the substrate to be processed _{O 2 / SF 6, O 2} /
A first sub-etching processing section for performing a plasma dry etching process using a CHF ₃ or O ₂ / CF gas. 3. The pattern forming apparatus according to claim 2, further comprising an ashing processing unit for ashing and removing the resist pattern. 4. A pattern forming apparatus for forming a predetermined pattern on a substrate to be processed by processing a film to be processed formed on the substrate to be processed, comprising the following components. A pattern forming device. (A) dry etching the substrate to be processed by using the resist pattern formed on the film to be processed as an etching mask to etch away the film to be processed exposed from the resist pattern; A processing unit having a main etching processing function for forming the predetermined pattern and an ashing processing function for ashing and removing the resist pattern. (B) said as an etching gas in a state of applying a high-frequency substrate bias voltage to the substrate to be processed _{O 2 / SF 6, O 2} /
A first sub-etching processing section for performing a plasma dry etching process using a CHF ₃ or O ₂ / CF gas. 5. A pattern forming apparatus for forming a predetermined pattern on a substrate to be processed by processing a film to be processed formed on the substrate to be processed, comprising the following components. A pattern forming device. (A) dry etching the substrate to be processed by using the resist pattern formed on the film to be processed as an etching mask to etch away the film to be processed exposed from the resist pattern; A main etching processing unit for forming the predetermined pattern. (B) An ashing processing function for ashing and removing the resist pattern, and O as an etching gas in a state where a high frequency substrate bias voltage is applied to the substrate to be processed
A processing unit having a first sub-etching processing function for performing plasma dry etching processing using a ₂ / SF ₆ , O ₂ / CHF ₃ or O ₂ / CF gas. 6. The pattern forming apparatus according to claim 2, further comprising a second sub-etching unit for performing a wet etching process on the substrate to be processed. Pattern forming device. 7. The pattern forming apparatus according to claim 2, wherein a transfer function for transferring the substrate to be processed to each processing section and a transfer chamber for transferring the substrate to be processed are provided. A pattern forming apparatus comprising: a transfer unit having a vacuum maintaining function for maintaining a vacuum state. 8. The pattern forming apparatus according to claim 2, wherein the high frequency substrate bias voltage has a structure capable of applying 100 V to 300 V, and the substrate to be processed at the time of the first sub-etching process. Temperature 0 ℃ ~
The structure can be set up to 80 ° C., and SF ₆ , CHF ₃ in the etching gas at the time of the first sub-etching process are used.
Alternatively, a pattern forming apparatus having a structure capable of setting a flow rate ratio of a CF-based gas to 1 to 25%. 9. A semiconductor integrated circuit device comprising the following steps when forming a predetermined pattern on the semiconductor substrate by processing a film to be processed formed on the semiconductor substrate: Production method. (A) After a resist pattern having a predetermined shape is formed on the film to be processed, the semiconductor substrate is dry-etched using the resist pattern as an etching mask so that the resist pattern is covered and is not removed by etching. A step of etching away a portion of the processed film exposed from the resist pattern with a protective film formed on the side surface of the remaining processed film. (B) A step of removing the resist pattern. (C) O ₂ / SF ₆ , O ₂ / as etching gas under the condition that a high frequency substrate bias voltage is applied to the semiconductor substrate.
A step of performing a plasma dry etching process using a CHF ₃ or O ₂ / CF gas. (D) A step of performing a wet etching process on the semiconductor substrate. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein the film to be processed is a conductor film and the predetermined pattern is an electrode wiring pattern. Method. 11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the conductor film comprises a refractory metal film or a silicide film thereof, an aluminum-based metal film, and a refractory metal film or a silicide film thereof. A method of manufacturing a semiconductor integrated circuit device, which is a laminated metal film formed by depositing layers in order from the lower layer. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the film to be processed is an insulating film and the predetermined pattern is a connection hole pattern. Method. 13. A semiconductor manufacturing apparatus for forming a predetermined pattern on a semiconductor substrate by processing a film to be processed formed on a semiconductor substrate, comprising the following components. Semiconductor manufacturing equipment. (A) A dry etching process is performed on the semiconductor substrate using the resist pattern formed on the processed film as an etching mask to etch away the processed film portion exposed from the resist pattern. A main etching processing unit for forming a predetermined pattern. (B) O ₂ / SF ₆ and O ₂ / O ₂ as etching gas with a high frequency substrate bias voltage applied to the semiconductor substrate
A first sub-etching processing section for performing a plasma dry etching process using a CHF ₃ or O ₂ / CF gas. 14. The semiconductor manufacturing apparatus according to claim 13, further comprising an ashing processing section for ashing and removing the resist pattern. 15. A semiconductor manufacturing apparatus for processing a film to be processed formed on a semiconductor substrate to form a predetermined pattern on the semiconductor substrate, comprising the following components. Semiconductor manufacturing equipment. (A) A dry etching process is performed on the semiconductor substrate using the resist pattern formed on the processed film as an etching mask to etch away the processed film portion exposed from the resist pattern. A processing unit having a main etching processing function for forming a predetermined pattern and an ashing processing function for ashing and removing the resist pattern. (B) O ₂ / SF ₆ and O ₂ / O ₂ as etching gas with a high frequency substrate bias voltage applied to the semiconductor substrate
A first sub-etching processing section for performing a plasma dry etching process using a CHF ₃ or O ₂ / CF gas. 16. A semiconductor manufacturing apparatus for processing a film to be processed formed on a semiconductor substrate to form a predetermined pattern on the semiconductor substrate, comprising the following components. Semiconductor manufacturing equipment. (A) A dry etching process is performed on the semiconductor substrate using the resist pattern formed on the processed film as an etching mask to etch away the processed film portion exposed from the resist pattern. A main etching processing part for forming a predetermined pattern. (B) An ashing treatment function for ashing and removing the resist pattern, and O as an etching gas in a state where a high frequency substrate bias voltage is applied to the semiconductor substrate.
A processing unit having a first sub-etching processing function for performing plasma dry etching processing using a ₂ / SF ₆ , O ₂ / CHF ₃ or O ₂ / CF gas. 17. The semiconductor manufacturing apparatus according to claim 13, further comprising a second sub-etching unit for performing a wet etching process on the semiconductor substrate. Semiconductor manufacturing equipment. 18. The semiconductor manufacturing apparatus according to claim 13, wherein a transfer function for transferring the semiconductor substrate to each processing section and a transfer chamber for transferring the semiconductor substrate are in a vacuum state. A semiconductor manufacturing apparatus characterized in that a transfer section having a vacuum maintaining function for maintaining the above is provided. 19. The semiconductor manufacturing apparatus according to claim 13, wherein the high-frequency substrate bias voltage has a structure capable of applying 100 V to 300 V, and the temperature of the semiconductor substrate during the first sub-etching process. 0
° C. and configurable structure to ~80 ℃, SF _6, CH etching gas during the first sub-etching process
A semiconductor manufacturing apparatus having a structure capable of setting a flow rate ratio of F ₃ or CF type gas to 1 to 25%.