JPH08212147A - Channel processor - Google Patents

Abstract

PURPOSE: To maintain the reliability of an information processing system by dynamically changing a logical channel number and a physical channel number by means of hardware. CONSTITUTION: Input/output devices 6n are composed of channel processors (CHP) 7n [(n) is IOP number) for performing the selection and management of channels and plural channel devices (CH) 7nm [(n)=IOP number and (m)=from 00 to 63) for performing the control of one channel bus. When any fault is generated at the CH7n(m-1), for example, the fault is reported from the broken down CH7n(m-1) to the high-order CHP7n and at the high-order CHP7n, it is retrieved whether the CH not used by an operating system(OS) 1 exists under its own control or not. When such a CH exists, the physical channel number and logical channel number of that CH (CH7nm, for example), are dynamically exchanged with the physical channel number and logical channel number of the broken down CH7b(m-1) by hardware processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention manages and controls a channel path for selectively transmitting and receiving information between a central processing unit and any one of a plurality of input / output devices. The present invention relates to a channel processing device.

[0002]

2. Description of the Related Art Generally, in an information processing system,
A channel processing device for managing and controlling a channel path for selectively transmitting and receiving information between the central processing unit and any one of the plurality of input / output devices is arranged.

This channel processing device is provided with a plurality of channel devices to which physical channel numbers corresponding to the mounting positions are assigned, and information is individually transmitted and received to / from an input / output device connected to each channel device in accordance with a predetermined protocol. It is configured to send and receive.

In this configuration, the central processing unit (specifically, operating system) recognizes each channel device by the logical channel number set in each channel device, and specifies the input / output destination by this logical channel number. On the other hand, the channel processor selects the channel path to the input / output device by the physical channel number. Therefore, the channel processing unit holds the logical channel number and the physical channel number in association with each other, and by cross-referencing the logical channel number and the physical channel number, the channel between the central processing unit and the input / output unit is held. It is designed to form a path.

Conventionally, a logical channel number and a physical channel number, which are in a one-to-one correspondence with each other, can be manually changed by using a service processor provided in an information processing system. If any of these causes an unrecoverable failure, manually remap the logical channel number for the failed channel device to match the physical channel number of a channel device that is not in use by the system. By doing so, a channel path to the input / output device can be secured.

By the way, it is usual to set a plurality of channel paths for important input / output devices. Therefore, even if one channel path has an unrecoverable failure, if another channel path can operate, the operating system can access the I / O device. However, it is not preferable that the number of channel paths for accessing the input / output device is decreased forever because of the reliability of the system. Therefore, it is necessary to replace the failed channel device and restore the number of channel paths accessible to the input / output device at an appropriate time, such as when the system is brought down by inspection of the system.

However, a troublesome problem arises when there is no replacement channel device for maintenance. That is, when the operator knows that a certain channel device has reached an unrecoverable failure, the operator searches for a channel device not used by the operating system and uses the service processor provided in the information processing system to detect the failure. The logical channel number corresponding to the channel device is changed to the physical channel number of the unused channel device searched by the operator. Then, the operator changes the connection of the input / output device connected to the faulty channel device to the channel device searched by the operator.

By the operator performing such work, the operating system can reuse the logical channel number assigned to the failed channel device.

However, since the work of the operator includes the work of connecting the cables, the work time is on the order of several hours, during which the operating system cannot use the logical channel number. So if one channel device goes into an unrecoverable failure,
The cumbersome problem of taking a considerable amount of time and effort from the operating system to use the logical channel number corresponding to the failed channel device again occurs.

In this case, "IBM Enterprise Systems Arch
By using a switching mechanism (director) that supports itecture / 390 ESCON I / O Interface (SA22-7202) ", there is no need to perform cable connection switching work. That is, the route is dynamically selected between the channel device and the input / output device.

[0011]

However, even if the above switching mechanism is used, the logical channel number of the failed channel device and the physical channel number of the replacement channel device are still the service processor provided in the system. It is necessary for the operator to manually correspond. Therefore, the burden on the operator is heavy, and the logical channel number assigned to the failed channel device cannot be used while the association is being changed, which impairs the reliability of the information processing system. There's a problem.

It is an object of the present invention to associate a logical channel number of a failed channel device with a physical channel number of a replacement channel device without operator intervention so that the reliability of an information processing system can be maintained. It is to provide a processing device.

[0013]

To achieve the above object, the present invention provides a logical channel number set for each channel device so that a central processing unit (operating system) selectively uses each channel device. And a storage unit that stores the physical channel number of each channel device in association with each other, a detection unit that detects the failed channel device, and a plurality of other channel devices that can replace the failed channel device. A channel for exchanging an alternate channel search means for searching from among channel devices, and a physical channel number and a logical channel number of the channel device in which a failure has occurred and the channel device searched by the alternate channel search means, stored in the storage means. The main feature is to have a number exchange means.

[0014]

In one physical channel path, there are a physical channel number which is a channel path number indicating a mounting position in the hardware and a logical channel number which is a channel path number recognized by the operating system. These two channel numbers are used for different purposes, respectively, but since they represent one channel path, they must be associated with each other.

The information of this association is stored and held in the information processing system after power-on. As an initial value of this association, usually, the respective channel numbers are associated in an ascending order and always have a one-to-one relationship. These correspondences can be changed using the service processor provided in the information processing system as described above, and are changed even when one channel device has an unrecoverable failure.

The channel processing device of the present invention, which manages and controls a plurality of channel devices, detects a failure of the channel device and retrieves a logical channel number or a physical channel number assigned to the channel device. Then, a replacement channel device that can newly assign a logical channel number corresponding to the failed channel device is searched. The conditions in this case are (1) the operating system is unused, (2) the channel type has the same attributes as the failed channel device, and (3) the input / output connected to the failed channel device. The device and the channel device for which a new logical channel number is to be associated are connected to the same switching mechanism.

As a result of the search, if there is an alternate channel device satisfying such a condition, the physical channel number related to the failed channel device corresponds to the logical channel number associated with the searched channel device. The physical channel number relating to the attached or searched channel device is re-associated with the logical channel number relating to the failed channel device.

After that, by giving a channel online instruction to the retrieved alternate channel device, the logical channel number can be accessed again from the operating system.

As described above, since the logical channel number and the physical channel number are dynamically changed by hardware, the change processing time is remarkably faster than the conventional one, and the reliability of the system is not impaired. Further, the intervention of the operator is not necessary, and the burden on the operator is eliminated.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of a main part of an information processing system equipped with a channel processing device of the present invention.
P) 60 to 6n (n = IOP number) are provided.

The configuration of 6n of the input / output devices 60 to 6n will be described as a representative. The input / output device 6n is a channel processing device (hereinafter, referred to as C
HP) 7n (n = IOP number) and a plurality of channel devices (hereinafter, CH) 7nm for controlling one channel path
(N = IOP number, m = 00 to 63).

A logical channel number CHPID, which is a channel path number recognized by the operating system 1, and a physical channel number P_CH, which represents a hardware mounting position, are assigned to each CH 7 nm to 7 n0.

For example, CH7nm is assigned a logical channel number CHPID = x and a physical channel number P_CH = n_m, and CH7n (m-1) is assigned a logical channel number CHPID = x-1 and a physical channel number P_CH.
= N_m-1 is assigned, and CH7n0 is assigned a logical channel number CHPID = x-m and a physical channel number P_CH = n_0.

These CHP7n and CH7nm to 7n
Reference numeral 0 is connected to the service processor 2, the basic processing device 3, and the storage control device 4 that controls the main storage device 5.

The main storage device 5 includes the service processor 2 and the basic processing device 3 as well as the CHP 7n inside each IOP 6n and each CH 7nm via the storage control device 4.
It is accessible from 7n0.

On the other hand, the operating system (hereinafter,
The OS 1 can use each resource of the information processing system via the basic processing device 3.

Each CH 7 nm to 7 n0 is connected to a plurality of input / output devices (hereinafter, IO) 90 to 92 via a switching mechanism (hereinafter, SW) 8. SW8 is provided with ports 81 to 86 that connect to CHs 7nm to 7n0 and IOs 90 to 92, respectively.
The fixed port numbers (a to f) are assigned to ~ 86.

In FIG. 1, the route shown by the dotted line is system defined. That is, CH7n
(M-1) is connected to port number = b, and IO90 and port number = connected to port number = d
The path to IO91 connected to e is CH7n (m-
It means that it is defined in 1).

Similarly, CH7n0 has port number = c
I connected to port number = f
This indicates that the path to O92 is defined.

On the other hand, CH7nm is connected to the port number = a, but indicates that there is no IO that defines the route.

Between these respective ports, port numbers to be an input port and an output port are added to the data,
By transmitting and receiving this in accordance with a predetermined protocol, it is possible to transmit and receive data between ports whose routes are defined.

"A" is assigned to SW8 as a switch number SW_NO (or SWN) used for identifying the switching mechanism. This switch number SW_
The information of NO is stored in the entry corresponding to the logical channel number in the logical channel number area (CHW) holding the information for each logical channel number CHPID, and the switching mechanism to which the channel device of the logical channel number CHPID is connected is It can be identified by CHPID.

On the other hand, each IOP 6n is set and identified by an IOP number n according to its connection position. And since there is only one CHP7n in IOP6n,
It is identified by the IOP number. CH7nm is the physical channel number P_C that represents the mounting position inside the hardware.
It is identified by H and a logical channel path number CHPID which is a channel path number recognized by OS1.

As the information processing system, it is necessary to associate the physical channel number P_CH with the logical channel number CHPID. This physical channel number P_CH
And the logical channel number CHPID are held in a dedicated hardware area (described later) in the main storage device 5,
It can be referred to from the basic processing device 3, CHP 7n, and each CH 7nm.

The physical channel number P_CH is shown in FIG.
It is represented by 2 bytes as shown in, and the upper byte is "0".
~ N "IOP number 21 and the lower byte is set to the physical channel number 22 of" 0-63 "according to the mounting position of the channel path (channel device) in the IOP 6n.

The logical channel number CHPID is represented by 2 bytes as shown in FIG. 2B, the upper byte is "0", and the lower byte is the logical channel number 23 of "0 to 255". It

FIG. 3 is a block diagram showing a detailed configuration of the CHP 7n. The CHP 7n accesses the main storage device 5 via the BPU_IF unit 7n1 that processes communication with the basic processing device 3 and the storage control device 4. A memory access unit 7n2 for controlling the CHP 7n, a control storage 7n5 for storing a microprogram for controlling the CHP 7n itself,
A processor unit 7n3 that controls the CHP 7n according to the microprogram, a CH_IF unit 7n4 that processes communication with each CH 7nm to 7n0, and a work memory unit 7n6 that is used when the microprogram performs processing.
And the SVP that handles communication with the service processor P2
_IF unit 7n7.

Between the BPU_IF unit 7n1 of the CHP 7n and the basic processing device 3, the CHP 7n → the basic processing device 3,
Basic processing device 3 → CHP 7n 2 with different directions
The signal line 31 of the book is connected. The logical value of this signal line 31 is normally "0", and when requesting processing from the CHP 7n to the basic processing device 3, "1" is sent to the signal line for CHP 7n → basic processing device 3, CHP7n
If the processing request from the basic processing device 3 can be processed, the basic processing device 3 responds by sending "1" to the signal line for the basic processing device 3 → CHP 7n. When the CHP 7n recognizes the positive response to the processing request, it returns the signal line for the CHP 7n → basic processing device 3 to “0”.

The basic processing device 3 recognizes that the signal line for the CHP 7n → the basic processing device 3 has returned to “0”, and returns the signal line for the basic processing device → the CHP 7n to “0”. C
When the HP 7n confirms that the signal line for the basic processing device → CHP 7n has returned to “0”, it writes the request content in the BPU-CHP communication area (see FIG. 6) in the main storage device 5 and writes it. After that, CHP7n is again CHP7n
→ Set the signal line for the basic processing unit 3 to "1".

The basic processing unit 3 confirms that the signal line has become "1", and after reading the request content from the CHP 7n from the BPU-CHP communication area in the main memory 5,
The signal line for the basic processing device 3 → CHP 7n is set to "1". CHP7n checks it and sets the signal line for CHP7n → basic processing unit 3 to “0”. Also, by this, the basic processing device 3 sets the signal line for CHP7n to "0".
To

When the basic processing device 3 requests the CHP 7n for processing, the sequence is reversed.

The communication method between the CHP 7n and the service processor 2 is also the same as the above-mentioned processing by the basic processing unit 3.
CHP7n → service processor 2 and service processor 2 → CHP are connected by two signal lines 32 in different directions. Then, the processing request content is the CHP in the main storage device 5.
-It is designed to be written in the communication area for SVP.

The communication method between the CHP 7n and the CHs 7nm to 7n0 is the same as the above-mentioned processing by the basic processing unit 3. However, CHP7n is not
7n → CH and CH → CHP 7n are provided with two signal lines 33 in different directions.

Further, at power-on, channel path online, channel path offline, etc., CHP
The signal line 34 for operating or stopping the microprogram of the subordinate CH from 7n is C for the subordinate CH.
One is connected for each H. When this signal line 34 is "1", the CH becomes operable, and the microprogram held in the CH starts operating from address 0. When the signal line 34 becomes "0", the operation of the CH is stopped. Hereinafter, this signal line 34 will be referred to as an operation start signal line.

Further, each CH has one failure report signal line 35 which is always "1" when each CH fails.
To CHP7n above it. The CHP 7n can recognize which channel under the IOP 6n is broken from the signal line 35 for reporting the failure.

The signal line 35 for reporting the failure becomes "1" only when the CH has an unrecoverable failure,
A failure report is sent to the upper CHP 7n.

The CHP-CH communication area in the main memory 5 exists in IOP units.

FIG. 4 is a block diagram showing a detailed configuration of CH7nm. CH7nm is a control storage 7nm3 for storing a microprogram for controlling CH7nm itself and CH7nm according to the microprogram.
via the processor unit 7nm1 for controlling the nm, the work memory unit (hereinafter, WM) 7nm2 used for the processing by the microprogram, the CHP_IF unit 7nm4 for processing the communication with the CHP7n, and the storage controller 4. Memory request unit 7nm5 for accessing main memory 5 and data transfer unit 7 for handling data transfer with IO
IO_I for interface processing between nm6 and IO
It consists of the F part 7 nm 7.

The format of WM7nm2 in CH7nm is shown in FIG. IO information area 51 for WM7nm2
And a CHPID area 52.

The IO information area 51 includes areas 510, 511, ... In IO device address (UA) units.
Each area is stored with a valid / invalid flag of in-area information, input / output device information (SBCH), port number of SW8 to which the IO is connected, and IO device address (UA). .

The IO information in this IO information area 51 is I
It is referred to by the device address (UA) of O and the port number of SW8 to which the IO is connected. That is, in the present embodiment, since the maximum number of SW8 ports is 6, "IO
Information area pointer IOINFO + port number x 25
“6 × 6 + UA × 16” is used to obtain the address of the IO information relating to the IO, and the I of the corresponding IO is obtained using this address.
Refer to O information.

FIG. 6 is a diagram showing the storage structure of the main storage device 5, in which a user area 61 used by programs including the OS 1 and areas 62 to 70 used by hardware.
Can be divided into

In this embodiment, the hardware pointer HP
The upper address side from TR is an area used by hardware.

The hardware pointer HPTR is set at the time of power-on, and changes depending on the input / output information assigned to the system. Further, the information belonging to the input / output relationship is the position of the relative address determined from the point of the hardware pointer HPTR (HPTR + in the figure).
It is stored from the area indicated by the pointer (hardware IO address pointer HIOA) stored in t).

Hardware IO address pointer HIO
A directory information area 62 is provided at the position A, where relative pointers (addresses when the value of HIOA is ZERO) SSBCH, SIO of various information are provided.
TBL, SCHPTBL, SCHW, SBPU, SIO
P and SSVP are stored.

Basic processing unit 3, each CHP 7n, each CH 7
The nm to 7n0 update or refer to necessary input / output information and the like from these pointers.

Input / output device information (SBCH) is stored in area 66 indicated by relative pointer SSBCH, and input / output table IOTBL is stored in area 65 indicated by SIOTBL.

Further, the channel path table CHPTBL is stored in the area 64 indicated by SCHPTBL, and the logical channel number information CHW is stored in the area 67 indicated by SCHW. In addition, SBP
Area 68 indicated by U is the basic processing unit 3 and the CHP 7n.
It is set in the communication area with.

The area 69 indicated by SIOP is C
It is set in the communication area of HP7n and CH7nm-7n0 under it. The communication area 69 is C
It is divided into H units, and each divided area is accessed by “HIOP + SIOP + IOP number × 256”.

The area 70 indicated by SSVP is
It is set in the communication area between the service processor 2 and the IOP 6n.

FIG. 7 shows the details of the input / output device information area 66. This area 66 is further subdivided for each SBCH number, and the divided area 661 corresponding to each SBCH number is included in the area. Flag FLG indicating the validity / invalidity of information, device address UA of IO, SBCH
The number and the path information indicating the channel path connected to the IO are stored.

FIG. 8 shows the details of the area 65 of the input / output device table IOTBL.
Is re-divided into areas 651 for each logical channel number CHPID. In each divided area 651, a flag FLG indicating whether the information in the area is valid or invalid, a port number and an SBCH number to the SW8 of the IO connected to the CH. Is stored. Further, the flag FLG is configured to store a bit indicating the validity / invalidity of the port number in addition to the bit indicating the validity / invalidity of the information in the area.

FIG. 9 shows the channel path table CHPTB.
The details of the area 64 of L are shown. The area 64 includes a conversion table 641 for converting a logical channel number CHPID into a physical channel number P_CH and a conversion table 642 for converting a physical channel number P_CH into a logical channel number CHPID. It consists of

The conversion table 641 is divided into logical channel number CHPID units, and in each divided area 6411, the physical channel number P_CH corresponding to the logical channel number CHPID is stored in the format shown in FIG. 2A. , “HIOA + SCHPTBL + CHPID ×
2 "to access.

Further, the conversion table 642 is divided into units of physical channel numbers P_CH, and each divided area 6412 is divided.
2B shows the logical channel number CHPID corresponding to the physical channel number P_CH in the format shown in FIG.
Is stored, and “HIOA + SCHPTBL + 512 +
(IOP number × 64 + CH number) × 2 ”.

FIG. 10 shows the logical channel number information area 6
7, the area 67 is divided into logical channel number CHPID units, and each divided entry 671 has a flag FLG indicating whether or not the logical channel is in the online state, Channel type CHTYP indicating attribute, logical channel number CHP
The ID and the number SWN of SW8 are stored. Further, the flag FLG is configured to store a bit CONFIG indicating whether or not the configuration is defined, in addition to the bit ONLINE indicating whether or not the state is online.

Next, the operation of the embodiment configured as described above will be described. In this case, CH7n (m-1) fails, and the unused channel CH7nm is CH1 from OS1.
An operation for enabling the IO 90 and 91 connected to the port numbers = d and e from CH7nm by shifting the assignment of PID = x-1 and bringing the channel online of CH7nm will be described with reference to the flowchart of FIG. To do.

Now, in the information processing system shown in FIG. 1, it is assumed that CH7n (m-1) has reached an unrecoverable failure. Then, the signal line 35 for failure reporting from CH7n (m-1) shown in FIG. 3 becomes "1".

The processor section 7n3 of CH7n is CH_
Although the signal line 35 for failure report of each CH 7nm to 7n0 is monitored via the IF 7n4, this failure occurs because the signal line 35 for report failure from CH7n (m-1) becomes "1". The channel number in the IOP 6n of the selected CH7n (m-1) is recognized as (m-1).

Since it has been found that the channel number in the IOP 6n of the failed channel device is "m-1",
The processor unit 7n3 of CH7n detects the physical channel number P_CH of the failed channel device (step 11).
11).

Specifically, since the CHP 7n detects it, the IOP number = n.

Therefore, it is detected that the physical channel number P_CH of the failed CH is "n_ (m-1)".

Next, the logical channel number CHPID is detected from the physical channel number P_CH of "n_ (m-1)" (step 1112).

Specifically, the "HIOA" in the main memory 5 is
Channel path table CHPTBL from area "+8"
After obtaining the pointer SCHPTBL of the
Calculate "HIOA + SCHPTBL" from CHPTBL. The address obtained there is the channel path table C.
This is the area of HPTBL64.

As shown in FIG. 9, the channel path table CHPTBL64 has two tables, a conversion table 641 for converting CHPID → P_CH and a conversion table 642 for converting P_CH → CHPID.

Therefore, the CHP 7n uses P_CH → CHPI.
The logical channel number CHPID corresponding to the physical channel number P_CH = n_ (m-1) of the failed CH is obtained from the conversion table 642 of D. For details, see "HIOA + S
CHPTBL + 512 + [IOP number (= n) × 64 +
CH number (= m−1)] × 2 ”is calculated. The value obtained thereby is the area 6412 for storing the CHPID corresponding to the failed CH7n (m-1).

Therefore, the logical channel number CHPID = x-1 of the failed CH is read from this area 6412.

Next, information about the failed CH is provided to the logical channel number information area (CHW) 67 in the main storage device 5.
Find more. For that purpose, first, "H" in the main memory 5
The pointer SCHW of the logical channel number information area (CHW) 67 is obtained from the area of “IOA + 12”.

Then, "HIOA + SCHW + CHPI
The content of the information entry (CHW entry) 671 related to the failed channel path is read by "D × 8".

The CHW entry 671 is made up of 8 bytes as shown in FIG. 10 and contains O indicating whether or not the channel path is online.
NLINE bit 6711 and CONFIG bit 671 indicating whether or not the channel path is defined.
2 and CHTYP67 indicating the attribute of the channel type
13, a logical channel number CHPID6714, and an identifier SWN6715 of SW8 to which the CH is connected.

CH corresponding to CHPID = x-1
“A” is stored in the SWN 6715 of the W entry 671. If the CHW entry is a channel for which the configuration is not defined, the SW identifier connected by the operator via the service processor 2 is input.

Therefore, attribute information relating to the failed channel path is read by the logical channel number CHPID = x-1 of the failed CH7n (m-1) (step 11).
13). The CHP 7n holds the attribute information obtained there in the work memory unit 7n6.

Next, the CHP 7n is an alternate CH that can exchange the logical channel number CHPID for the failed CH.
Is searched (step 1114).

In this case, the search conditions are that the channel path is not defined, that it is connected to the same SW8 as the failed channel path or the input / output device group connected to the failed channel path, and that it has the same attributes. Is the channel of. CH the channel path that satisfies this condition
Search from the channel paths under the control of P7n.

In the search method, the logical channel number CHPID corresponding to each physical channel number P_CH is searched by the above-mentioned method, and the information about each channel path is searched by the logical channel number CHPID in the logical channel number information area (CHW Area 67, and compares it with the information about the failed channel path that was previously acquired.

As a result, if the replacement CH is not found, the BPU-IF 7n is sent to the basic processing unit 3.
Via 1 the logical channel number CHPID and the physical channel number P_CH relating to the failed channel path, as well as the fact that one channel path has become an unrecoverable failure is notified.

When the basic processing device 3 receives this notification,
The IOP number that has received the failure notification is stored, and both the logical channel number CHPID and the physical channel number P_CH related to the failed channel path for another CHP group (not shown in FIG. 1) can be dynamically assigned. To search for.

When another CHP group cannot search for such a channel path, it responds to the basic processing device 3 to that effect. When the response of the search failure is returned from all the CHP groups, the basic processing device 3 judges that the dynamic allocation of the logical channel number CHPID regarding the failed channel path can no longer be performed, and the first report is issued. C
HP7n is instructed to that effect. Then, the CHP 7n performs the conventional fixed failure processing of the channel path.

However, when a dynamically assignable logical channel number CHPID is found in the CHs in the CHP 7n, or when a dynamically assignable channel path is found by the instruction of the basic processing unit 3, the CHP 7n concerned. Is the logical channel number CHPID and the physical channel number P_CH
The association with and is dynamically changed (step 1115).

In the example of this embodiment, CH7nm is recognized as a dynamically assignable channel path. CH7nm
Is a logical channel number CHPID = x and a physical channel number P_CH = n_m.

Therefore, the CHP 7n changes the correspondence between the logical channel number CHPID and the physical channel number P_CH by directly updating the channel path table 64 (CHPTBL).

More specifically, the CHPID → P_CH conversion table 6411 and the P_CH → CHPID conversion table 64.
In each of 12, the entry 64 obtained by the logical channel number CHPID = x, x−1 corresponding to the failed channel and the channel path for which dynamic allocation is to be performed.
11, change of the physical channel number P_CH, and physical channel numbers P_CHn_m, n_m-corresponding to the failed channel and the channel path to be dynamically allocated.
The logical channel number CHPID in the entry 6412 obtained in 1 is changed.

Specifically, although P_CH = n_m was stored in the entry for CHPID = x of the channel path table CHPTBL64 of CHPID → P_CH, it is changed to "n_m-1". Similarly, CH
The entry for PID = x-1 has P_CH = n_m
-1 was stored, but it is changed to "n_m".

Further, the entry of the channel path table CHPTBL64 of P_CH → CHPID is also changed. That is, CHPID = x stored in the entry relating to P_CH = n_m is changed to “x−1”, and P_CH = n
CHPID = x stored in the entry for _m-1
Change -1 to "x".

From the above, the logical channel number CHPID
Will be dynamically associated with the physical channel number P_CH.

Next, since the channel path dynamically allocated as described above is unused by the operating system 1 according to the search condition, the channel is not online. Therefore, the CHP 7n sets the operation start control line 34 to "1" for the CH 7nm and issues a channel online instruction (step 1116). this is,
This is possible because the physical channel number P_CH that can be dynamically allocated is already known.

As a result, CH7nm starts operating.

Next, the CHP 7n indicates the logical channel number CHPID = x-1 of the CH 7nm to the CHP 7nm by using the CH-IF 7n4.

CHP7nm is the logical channel number C
When HPID = x-1 is received, the logical channel number CHPID = x-1 is assigned to the work memory unit 7 in CH7nm.
Store in nm2. Then, the logical channel number CH
Input / output information connected to the channel path is searched using PID = x−1, and the information obtained there is taken into the work memory unit 7 nm2 inside the CH 7 nm. These pieces of information use CHPID = x−1 to input / output device table (I
OTBL) 65 and input / output device information (SBCH).

The input / output device information (SBCH) can be specified by the SBCH number 6512 included in the entry of the input / output device table (IOTBL) 65 for the logical channel number CHPID = x-1 shown in FIG.
The input / output device information (SBCH) is addressed from the port number 6511 of the SW 8 to which the IO is connected and the device address (UA) of the IO, and is used as the work memory unit 7
It is stored in nm2.

As a result, the failed CH7n (m-
The port number 6511 of SW8 used in 1) is taken over by the replacement CH7nm.

In this way, CH7nm becomes accessible to IOs 90 and 91 with the logical channel number CHPID = x-1. The operating system 1 can also use the logical channel number CHPIDx-1 without distinguishing it from the case where the physical channel number P_CH = n_m-1 is the logical channel number CHPID = x-1.

As described above, in this embodiment, CH7
When n (m-1) fails, the failed CH7n (m-
From 1), the upper CHP 7n is caused to report a failure, and the upper CHP 7n searches for whether or not there is a CH that is not used by OS1 under its own control, and if there is, that CH (CH7nm in the explanation example). The physical channel number and logical channel number of the CH7n (m-1) that has failed and the physical channel number and the logical channel number of the failed CH7n (m-1) are dynamically exchanged by hardware processing. A normal channel path can be formed without any intervention.

As a result, the reliability of the system can be prevented from being impaired and the reliability can be maintained.

[0106]

As described above, according to the present invention, when one channel path has an unrecoverable failure, the physical channel number related to the failed channel path and the logical channel number corresponding to the physical channel number are associated with each other. , Because the hardware dynamically exchanges the physical channel number and the logical channel number for the channel path not used by the operating system without operator intervention, 1
Even if one of the channel paths has an unrecoverable failure, the processing time for changing the physical channel number and the logical channel number is much faster than before, and the reliability of the system is not impaired. Further, there is an effect that the intervention of the operator is not necessary and the burden on the operator is eliminated.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of an information processing system using a channel processing device of the present invention.

FIG. 2 is a configuration diagram of physical channel numbers and logical channel numbers.

FIG. 3 is a block diagram showing a detailed configuration of a channel processing device (CHP) in the embodiment.

FIG. 4 is a block diagram showing a detailed configuration of a channel device (CH) in the embodiment.

FIG. 5 is a work memory unit (W) in a channel device (CH).
It is a storage block diagram of M).

FIG. 6 is an information storage configuration diagram of a main storage device (MS).

FIG. 7 is an information storage configuration diagram of input / output device information (SBCH).

FIG. 8 is an information storage configuration diagram of an input / output device table (IOTBL).

FIG. 9 is a configuration diagram of information storage of a channel path table.

FIG. 10 is an information storage configuration diagram of a logical channel number (CHPID) information area (CHW).

FIG. 11 is a schematic flowchart showing a procedure for changing a physical channel number and a logical channel number.

[Explanation of symbols]

1 ... Operating system (OS), 2 ... Service processor (SVP), 3 ... Basic processing unit (BPU),
4 ... Storage control unit (SCU), 5 ... Main storage unit (M
S), 6n ... Input / output processing device (IOP), 7n ... Channel processing device (CHP), 7n1 ... BPU-IF unit, 7n
2 ... Memory request unit, 7n3 ... Processor unit, 7n
4 ... CH-IF section, 7n5 ... control storage,
7n6 ... Work memory unit, 7n7 ... SVP-IF unit, 7
nm ... Channel device (CH), 7 nm1 ... Processor section, 7 nm2 ... Work memory section (WM), 7 nm3 ... Control storage (CS), 7 nm4 ... CHP-I
F part, 7 nm 5 ... Memory request part, 7 nm 6 ... Data transfer part, 7 nm 7 ... IO-IF part, 8 ... Switching mechanism (SW), 64 ... Channel path table, 65 ... Input / output device table, 66 ... Input / output information area, 67 ... Logical channel number information area, 81-86 ... Port of switching mechanism, 90-92 ... Input / output device (IO).

Claims (1)

[Claims] 1. A plurality of channel devices to which physical channel numbers corresponding to mounting positions are assigned, a plurality of input / output devices for transmitting / receiving information individually to / from each channel device according to a predetermined protocol, and the plurality of channel devices. A switching mechanism that is connected between the I / O devices and performs dynamic route selection between each channel device and each I / O device, and management and control of the channel path between the central processing unit and each channel device A channel processing device of an information processing system including a channel processing device for performing, wherein a logical channel number set for each channel device for the central processing device to selectively use each channel device and a channel processing device for each channel device. Storage means for storing the physical channel number in association with each other; detection means for detecting a failed channel device; Alternate channel searching means for searching for another channel device that can replace the channel device from a plurality of channel devices; faulty channel device stored in the storage means; and channel device searched by the alternate channel searching means. And a channel number exchanging means for exchanging the physical channel number and the logical channel number.