JPH0821087B2 - Three-dimensional shadow image generation processing method - Google Patents

Description

Detailed Description of the Invention

TECHNICAL FIELD The present invention relates to a processing method for generating a three-dimensional shadow image based on shape data of a three-dimensional object represented by numerical values. (Prior Art) In recent years, a technique for creating a three-dimensional shadow image by observing it from an arbitrary position by numerical calculation using a computer based on the shape data of a three-dimensional object represented by numerical values. Is attracting attention. This has come to be used as an effective means for designing and simulating products in various industries and industries, or as an effective image creating means for TV broadcasting and movies. However, in order to create a shadow image from the shape data of an object, enormous numerical calculation processing is required, and there are problems that the processing time is too long and a high-speed large computer is required. This kind of problem is also a major factor in lowering the efficiency of the work when designing the above-mentioned products and creating images and increasing the equipment cost. Along with the recent development of hardware technology centering on computers, a three-dimensional shadow image generation apparatus that executes this kind of processing at high speed has been developed. An apparatus for generating a shadow image at a high speed based on a particularly simple processing method has been rapidly put into practical use and can be used at a low price. For example, a workstation used in the fields of CAD and CAM can also generate and display a shadow image while inputting data. Many conventional devices employ image generation processing methods called depth buffer method and canline method. These methods require a relatively small amount of processing and can generate images at high speed, but have drawbacks such as limited object shape and optical development such as reflection and refraction. As a more realistic and accurate shadow image generation method, there is a processing method called a ray tracing method. According to this method, it is possible to generate an image that does not have the drawbacks of the above method, but search for the point where the virtual ray emitted from each pixel of the image to be created intersects with the object and determine the brightness of the pixel. Since the calculation is performed, an order of magnitude more calculation is required as compared with the above method. 2. Description of the Related Art Conventionally, research and development has been conducted on a dedicated device intended to execute the above ray tracing method at high speed. The configuration of this type of device is roughly classified into a configuration in which a large number of microprocessors are connected in parallel, and a configuration in which high-speed computation is possible by using a floating-point arithmetic dedicated LSI. However, in the former device, since the capacity of each processor is small, it is necessary to use many processors to speed up processing.
There is a problem that the scale of the device becomes large. In the latter device, the floating-point arithmetic LSI can execute the arithmetic operation at high speed. However, for this purpose, it is necessary to perform high-speed processing such as setting of the object shape data used for the calculation and judgment of the calculation result. However, the combination of the floating point arithmetic unit and the processor for performing this type of processing is required. There was a problem that it was not sufficient and high-speed calculation was not always possible as a whole. (Object of the Invention) The present invention has a multiprocessor configuration in which processing units are connected in parallel in order to enable high-speed processing such as ray tracing processing capable of generating a real and precise shadow image at high speed. The data is transferred at high speed among the four floating point arithmetic units to each arithmetic unit, and its purpose is to perform the three-dimensional vector arithmetic operation and matrix arithmetic operation that appear intricately in the above-mentioned shadow image generation processing. The four floating-point arithmetic units are executed in parallel, and the arithmetic logic unit is used to perform processing such as determination of arithmetic results, thereby performing high-speed three-dimensional shadow image generation processing. (Structure and Operation of the Invention) FIG. 1 is a structural example of a three-dimensional shadow image generation device having a multiprocessor structure in which a plurality of processing units are connected in parallel. The configuration of the multiprocessor device is known as a configuration method capable of performing enormous amounts of processing in parallel without using a specially high-speed device. For example, the conventional device described above has a similar configuration. There is. In FIG. 1, PU is a processor unit,
A processing unit that is connected to the system bus 10 and performs processing independently. DC is a data collector for collecting the image data created by each processor unit PU, DM is a display memory for storing the collected image data and displaying it on the display, and CRT is for displaying the image. The display device and MP are main control units that control the entire device. Generally, to operate a device configured in this way,
First, the main control unit MP loads object shape data used for image generation and a necessary processing program to each processor unit PU. Next, each processor unit PU creates an image according to the loaded program and data, and transfers the image data to the display memory DM via the data collector DC to display the image on the display. Each processor unit PU shares the creation of a part of the screen, and simultaneously executes image generation. In the apparatus configured as described above, in order to perform image generation at high speed, there are a method of increasing the number of processor units and a method of improving the processing capability of each processor unit. However, in the former case, there is a problem that the scale of the device becomes enormous and its control becomes difficult, so it is not realistic to unnecessarily increase the number of processor units. With the latter method, the scale of the entire device can be small, and with the recent advancement in the functionality of various LSIs,
This is a more realistic method. FIG. 2 is an embodiment of the present invention, and is an example of the configuration of a processor unit PU applied to the three-dimensional shadow image generating apparatus having the multiprocessor configuration of FIG. In the figure, IF is an interface with the system bus 10, DBMs # 1 to # 4 are data memories for storing object shape data and processing parameters used for image generation processing, and FPU.
# 1 to # 3 are floating-point arithmetic units, FAPU floating-point arithmetic units and arithmetic units that are connected in parallel, and 20 is a high-speed unit that connects DBM # 1 to # 4 and FPUs # 1 to # 3 and FAPU. Data bus, DC is a data collector for collecting the image data created by the arithmetic unit and writing it in the display memory DM shown in FIG. 1, WCS is a program for storing instructions for controlling each arithmetic unit, memory and logic circuit. A memory, SEQ is a sequencer for fetching instructions stored in the program memory WCS, and ADG is an address generator for generating a physical address of DBM from a memory addressing instruction among the instructions fetched by SEQ. For the processor unit of FIG. 2, as described above, the main control unit MP of FIG. 1 generates a processing program in the program memory WCS and an image in the data memory DBM via the system bus 10 and the bus interface unit IF. 3 required for
The three-dimensional object shape data and processing parameters such as observation positions are loaded. After that, the sequencer SEQ sequentially fetches instructions from a predetermined location of the program memory WCS, controls each unit according to the instructions, and executes the processing. FIG. 3 shows a specific configuration example of the arithmetic unit in FIG. 2, that is, the arithmetic unit FAPU in which the floating point arithmetic units FPU # 1 to # 3 and the floating point arithmetic unit and the arithmetic logic arithmetic unit are connected in parallel. Is. In FIG. 3, FPPs # 1 to # 4 are floating point arithmetic units, A
LU is an arithmetic logic unit, MPX is a data multiplexer that selects one of many data, REG # 1 to # 4 are data registers that store the operation data, and LUT is a function that calculates functions such as square root and trigonometric functions at high speed. Is a reference table that stores parameters for As shown in FIG. 3, three floating point arithmetic units FPP #
The output of the data register and the output of the adjacent floating-point arithmetic unit are connected to each of the input terminals 1 to # 3 via the data multiplexer MPX. That is, the output of FPP # 1 is output to FPP # 2 and # 3, and the output of FPP #
2 output to FPP # 1 and # 3, FPP # 3 output to FPP
# 2 and # 1 are connected in a cross-shaped fashion so that they can be input. Further, the FPP # 4 and the arithmetic logic operation unit ALU are connected in parallel, and the outputs of the three floating point arithmetic units FPP # 1 to # 3 are connected to the input terminals via the data multiplexer MPX, and The output of the set of arithmetic units is FPP # 1 to #
It is connected to the input terminal 3 of 3 via the data multiplexer MPX. Since the arithmetic units are configured in this way and each of the arithmetic units operates independently, for example, if the floating point arithmetic units FPP # 1 to # 4 are used, four types of floating point arithmetics can be performed in parallel. , It is possible to efficiently perform pipeline operation using the Tasukuge connection. Such an operation is suitable for efficiently performing coordinate conversion processing, which often appears in three-dimensional image generation processing. For example,

[X'Y'Z'W '] =

[X Y Z W]

[T]
(1) is a 4-by-4 transformation matrix for points (X, Y, Z, W) on homogeneous coordinates

It is a homogeneous coordinate transformation that transforms into points (X ', Y', Z ', W') by [T]. FIG. 4 shows the processing steps when this is executed by the arithmetic unit of FIG. However, the coordinate values (X, Y,
Z, W) and transformation matrix

It is assumed that the elements T _ij (i, j = 1 to 4) of [T] are stored in advance in the data registers REG # 1 to # 4 of each arithmetic unit. To calculate the equation (1), 16 multiplications and 12 additions are required, which can be performed in 12 steps as shown in FIG. 4 according to the arithmetic unit of FIG. . Therefore, as compared with a general-purpose computer that performs sequential processing, half or less of step (1) can be calculated. That is, even if the calculation time required for one step is the same, high-speed calculation more than double that of a general-purpose computer becomes possible. Here, FIG. 4 is a diagram showing a calculation process of the homogeneous coordinate conversion processing by the calculation unit of FIG. 3, a in FIG. 4 shows the contents of the data register of the calculator, and b shows the execution calculation step. Next, a ray tracing method, which is a typical three-dimensional shadow image generation processing method, will be briefly described. The ray tracing method is known, and the outline of the processing is as shown in FIGS. 5 and 6. First, in FIG. 5, a viewpoint V _p to be observed and a virtual screen S are defined. Next, a vector (this is called a ray vector) is defined through the viewpoint V _p and one point P on the virtual screen S. Next, the fifth
As shown in FIGS. 6 and 6, this vector is a three-dimensional object O
If it intersects, the intersection point Q is obtained. If intersections Q exist for a plurality of objects, it is checked whether the object does not intersect the vector 'from the intersection Q closest to the viewpoint to the light source L, and if they do not intersect, the reflectance of the objects is used to determine the intersection Q. Calculate the brightness. The above process is repeated for all points on the virtual screen S. The above ray tracing method processing includes many three-dimensional vector operations and the like. In particular, the process of determining the intersection between the ray vector and the object O and calculating the intersection Q needs to be repeated the number of times proportional to the number of objects and the number of pixels of the screen to be created, and thus requires the most calculation. . The operation when this type of processing is performed by the arithmetic unit of FIG. 3 will be described. The ray vector is expressed by the following equation using a unit direction vector from the viewpoint V _p to a point on the screen and a position vector of the viewpoint V _p with t as a parameter. = * T + (2) First, it is assumed that the object O is a plane represented by the following equation. a * X + b * Y + c * Z + d = O (3) From equations (2) and (3), the intersection Q between the ray and the object is given by tq that satisfies the following equation. tq =-(a * Vx + b * Vy + c * Vz + d) / (a * Ux + b * Uy + c * Uz) (4) where (Ux, Uy, Uz) and (Vx, Vy, Vz) are the unit vector and the viewpoint V _p, respectively. Represents the elements of the position vector of. Similar to FIG. 4, the arithmetic unit of FIG. 3 can perform the denominator and the numerator of equation (4) in three steps. However, since the division of equation (4) cannot be calculated directly by the floating point arithmetic unit, the reciprocal of the denominator is calculated using the reference table LUT of the floating point arithmetic unit FPP # 4 in FIG. It will be calculated by finding the product of Although the reciprocal calculation requires several steps, the equation (4) can be calculated in about 12 steps. Since it is difficult to represent a curved surface object only by the plane represented by Expression (4), in order to represent various object shapes, the object is often represented by a combination of quadric surfaces represented by the following expression. Has been done. Where (X, Y, Z) are three-dimensional coordinates on the curved surface, and m _ij (i, j ＝
1,2,3) are coefficient matrix elements of the surface equation. Equation (5)
The coordinate (* tq +) of the intersection Q between the quadric surface and the ray vector represented by is obtained by substituting the equation of the ray vector of the equation (1) into the equation (5), and obtains a variable tq satisfying the following equation. It can be calculated by Atq ² = 2Btq + C = O (6) However, the coefficients A, B, and C of the equation (6) are given by the following equations. ^{A = m11 * Ux 2 + m22} * Uy 2 + m33 * Uz 2 + 2 * (m12 * Ux * Uy + m33 * Uy * Uz + m31 * Uz * Ux)
(7) B = (m11 * Ux * Vx + m22 * Uy * Vy + m33 * Uz * Vz) + (m12 * Ux * Vy + m23 * Uy * Vz + m13 * Uz * Vx) + (m12 * Uy * Vx + m23 * Uz * Vy + m13 * Ux * Vz)
(8) C = m11 * Vx 2 + m22 * Vy 2 + m33 * Vz 2 + 2 * (m12 * Vx * Vy + m23 * Vy * Vz + m31 * Vz * Vx)
-2 (9) From the above, the condition that the ray vector intersects the quadric surface object is that the quadratic equation (6) regarding tq has a real root. That is, if the following equation holds, there will be an intersection. D = B ² −A * C ≧ O (10) Although detailed calculation process is omitted, if the calculation parameter is set in the register REG of the calculation unit in FIG. 3, FPP # 1
8 steps for calculating A from Expression (7) using
The coefficients A, B, and C of the quadratic equation (6) can be calculated in a total of 26 steps for calculating B and C from the expressions (8) and (9), respectively, in 26 steps. Since the equation (10) can be calculated in two steps from the result, it is possible to determine the intersection between the object represented by the quadric surface and the measurement line vector in 28 steps. Therefore, also in this case, it is possible to perform the calculation in less than half the steps as compared with the general-purpose computer of the serial processing type. Further, the above processing is performed by the floating point arithmetic unit FPP # of FIG.
Since it can be performed using only 1 to # 3, while performing this operation, the arithmetic logic operation unit ALU takes out the data necessary for the above operation from the data memory and stores it in the data register of each operation unit. With this operation, it is possible to ignore the instruction execution time such as data loading from the memory to the register. Therefore, the actual processing time can be reduced to a fraction or less as compared with a general-purpose computer or the like. The above is the main operation when the processor unit in FIGS. 2 and 3 performs the three-dimensional shadow image generation processing by the ray tracing method, but when applying another three-dimensional shadow image generation processing method Also, this type of processing can be executed at high speed in order to perform the processing such as coordinate conversion represented by the equation (1). The typical operation of the arithmetic unit of FIG. 3 has been described above.
These operations were performed after the data used for the calculation was stored in the data register. In general, since a scene including many objects is often targeted, it is necessary to provide a large-capacity data memory for storing three-dimensional shape data and the like necessary for calculation, as shown in FIG. Therefore, it is necessary to take out the data required for the operation from this type of data memory and transfer it to the data register of the operation unit in FIG. 3 at high speed. In order to solve this, the data memory in FIG.
The high-speed data bus 20 connecting the DBM and each arithmetic unit is configured so that data can be collectively transferred in parallel between the data memories DBM # 1 to # 4 and the arithmetic units. On the other hand, a memory address is given to the data memory, and by designating the corresponding data storage area by this address, data can be written or read in the corresponding area. In the processing program for operating this type of device, it is desirable to specify the area in the data memory by the relative displacement address value from the viewpoint of ease of program creation. Therefore, it is necessary to convert this into a physical address of the data memory. FIG. 7 shows an embodiment of the address generator ADG in FIG. 2, which is the program memory WC of the processor unit.
It has a function of decoding an address command of the data memory DBM included in the processing program stored in S and converting it into a physical address of the data memory DBM. In the figure, WCS and SEQ are the program memory and program sequencer shown in FIG. 2, respectively, the instruction register is a register for storing an instruction to be executed, the base address register is a register for storing a base address value, and the index register is a base. The register that stores the relative address value from the address, the attribute register is the register that stores the parameter value that specifies the conditions for address generation (one-dimensional access or two-dimensional access specification, access unit specification, etc.), and SUM is added Circuit, M
UX is a data multiplexer. In addition, the two-dimensional address generation circuit uses (x, y) 2 when the two-dimensional access is specified by the attribute register.
The byte address generation circuit is a circuit that converts a relative address specified by a dimension into a one-dimensional address, and the byte address generation circuit is a circuit that generates a byte address in the address unit specified by the attribute register. With this configuration, the program memory WC
The relative displacement address value DA in the instruction extracted from S is converted into the physical byte address value AA of the data memory as follows. That is, when one-dimensional access is designated by the attribute register, AA = (IR + DA) * n + BR (11). Here, IR is a relative address value in the index register, a base address value in the BR base register, and n is an integer power of 2 indicating an address unit. For example, if n = 4, it indicates a 4-byte unit access. In the case of two-dimensional access designation, AA = [{IR (x) + DA (x)} + {IR (y) + DA
(Y)} * N] * n + BR (12) The physical byte address of the data memory is generated. Here, IR (x) and IR (y) are the relative address value in the x direction and the relative address value in the y direction indicated by the index register. For example, when the index register is 32 bits, the upper 16 bits are the y address. , Lower 16 bits are defined like x address. Similarly, DA (x) and DA (y) are the x-direction relative displacement address value and the direction relative displacement address value of the relative displacement address in the instruction register. N is a positive integer that determines the size in the x direction, and an integer power of 2 is generally selected. As described above, the base address register, the attribute register, and the index register respectively have the base address BR, the access type and the address unit n, N,
By storing the relative address IR in advance,
After that, the physical address of the data memory according to the condition can be generated only by expressing the instruction in the processing program by the relative displacement address DA. Moreover, since the present address generator can be configured with only a simple logic circuit, the above address calculation can be executed at high speed. For example, it becomes possible to perform address calculation in about 1/3 to 1/6 time as compared with the case where this is performed by a general-purpose arithmetic logic operation unit. By the above two-dimensional address calculation, data expressed in tabular form and two-dimensional image data can be accessed only by specifying the position in the x and y directions, which is extremely effective for high-speed access of these data. is there. (Effects of the Invention) As described above, according to the present invention, three-dimensional vector operations and matrix operations that are included in a large amount in three-dimensional shadow image generation processing are performed in parallel or by three or four floating-point arithmetic units. Of the data such as the object shape that can be executed in a pipeline and stored in the data memory,
It can be generated at high speed by the memory address generator of the data used for the operation, and the corresponding data can be supplied to the arithmetic unit via the high-speed data bus, so that the use efficiency of the floating point arithmetic unit is not reduced, There is a feature that image generation processing can be executed. Therefore, it is possible to significantly speed up the process of generating a realistic three-dimensional shadow image by the ray tracing method capable of simulating optical properties such as reflection and refraction, and to use another simple method. Image generation processing can also be performed at higher speed. As a result, in a device having a multiprocessor configuration, the number of processing units required to obtain a desired processing capacity can be significantly reduced, and there is an advantage that the device can be downsized and control can be facilitated. . Further, the processor unit of the present invention does not use a special element, and a general-purpose general-purpose LSI can be used for an element such as a floating-point arithmetic unit or an arithmetic logic arithmetic unit. Even if a kind of LSI has higher performance, these elements can be applied to achieve higher performance without significantly changing the configuration of the present invention. Alternatively, by using recent more advanced LSI technology, a part or all of the arithmetic unit, the address generator and the like of the processor unit may be made into an LSI to make a smaller and more sophisticated device.

[Brief description of drawings]

FIG. 1 is a general configuration diagram of a three-dimensional shadow image generation apparatus having a multiprocessor configuration, FIG. 2 is a configuration example of a processor unit according to the present invention, and FIG. 3 is a detailed configuration example of a calculation unit in FIG. FIG. 4 is a diagram showing a calculation process of a homogeneous coordinate conversion process by the calculation unit of FIG. 3, and FIGS. 5 and 6 are explanatory diagrams of a ray tracing method which is a typical three-dimensional shadow image generation processing method. FIG. 7 shows an example of the configuration of an address generator for converting a data memory address instruction in a processing program into a physical address. 10 …… system bus, 20 …… high-speed data bus, PU …… processor unit, DC …… data collector, MP …… main control unit, DM …… display memory, CRT …… display device, IF …… interface unit, DBM ... Data memory, FPU ... Floating point arithmetic unit, FAPU ... Arithmetic unit, WCS ... Program memory, SEQ ... Sequencer, ADG ... Address generator, FPP ... Floating point arithmetic unit, ALU ... Arithmetic logic Operation unit, MPX ... Data multiplexer, REG ... Data register, LUT ... Reference table,
_Vp ... viewpoint, S ... virtual screen, Q ... intersection, L ... light source.

Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location G06F 15/347 M (56) Reference JP-A-59-194242 (JP, A) IEICE Transactions '86 / 3 Vol. J 69-D No. 3PP. 474-476 Information Processing Society of Japan, Computer 3-Technical Research Group Report, 58-6

Claims (2)

[Claims] 1. A processor unit of a three-dimensional shadow image generation processing apparatus having a multiprocessor structure, wherein a group of four arithmetic units is connected in parallel, and the output of each arithmetic unit is the input of an arithmetic unit other than itself. When the vector operation represented by f = a * x + b * y + c * z + d * w is performed, the first, second, third, and fourth calculation steps are performed. , A * x, b * y, c * z, d * w are calculated respectively, and in the second calculation step, outputs of the first and second calculation elements of the first calculation step are calculated. And outputs of the third and fourth arithmetic units to the first and second arithmetic units respectively.
The inputs of either one of the third and fourth arithmetic units are used to perform addition, and in the third calculation step, the outputs of the two arithmetic units of the second calculation step are used in either one of the arithmetic units. Is performed as an input, and the vector operation f is performed in a total of three calculation steps. 2. In a processor unit of a three-dimensional shadow image generation processing device having a multiprocessor configuration, a set of four arithmetic units is connected in parallel, and the output of each arithmetic unit is the input of an arithmetic unit other than itself. In order to perform the matrix operation represented by [X ', Y', Z ', W'] = [X, Y, Z, W] [T] [T] is a matrix of 4 rows and 4 columns represented by Tij (ij = 1 to 4)) In the first calculation step, the first, second, third, and fourth arithmetic units are used, and T11 * X, T21 * Y, T31 * Z, T41 * W are calculated, and in the second calculation step, the outputs of the first and second calculators in the first calculation step and the third and fourth calculations The output of the calculator to the first or second arithmetic unit
The input of any one of the third and fourth arithmetic units is performed, and the addition is performed respectively. In the third calculation step, the outputs of the two arithmetic units of the second calculation step are compared with those of one of the arithmetic units. Addition is performed as an input, and in the fourth calculation step, T12 * X, T22 * Y, T32 * Z, T42 * W are calculated using the first, second, third, and fourth arithmetic units, respectively. Then, in the fifth calculation step, the outputs of the first and second arithmetic units and the outputs of the third and fourth arithmetic units of the fourth calculation step are respectively output to one of the first and second arithmetic units. The inputs of the arithmetic unit and any one of the third and fourth arithmetic units are used to perform addition, and in the sixth calculation step, the outputs of the two arithmetic units of the fifth calculation step are used. The addition is performed as an input of the arithmetic unit, and in the seventh calculation step, the first, second, third, and fourth arithmetic units are To calculate T13 * X, T23 * Y, T33 * Z, T43 * W, respectively, and in the eighth calculation step, the outputs of the first and second calculators and the third calculation step in the seventh calculation step. The output of the fourth arithmetic unit is output to the one of the first and second arithmetic units, respectively.
The input of any one of the third and fourth arithmetic units is performed, and the addition is performed respectively. In the ninth calculation step, the outputs of the two arithmetic units of the eighth calculation step are output from one of the arithmetic units. Addition is performed as an input, and in the tenth calculation step, T14 * X, T24 * Y, T34 * Z, T44 * W are calculated using the first, second, third, and fourth arithmetic units, respectively. Then, in the eleventh calculation step, the outputs of the first and second calculators and the outputs of the third and fourth calculators of the tenth calculation step are respectively calculated by one of the first and second calculations. Vessel and first
The inputs of any one of the third and fourth arithmetic units are added, and the respective additions are performed. In the twelfth calculation step, the outputs of the two arithmetic units of the eleventh calculation step are output from one of the arithmetic units. A three-dimensional shadow image generation processing method characterized by performing addition as an input and performing X ', Y', Z ', W'in a total of 12 steps.