JPH08210876A - Absolute encoder device - Google Patents

Abstract

PURPOSE: To reduce the size of the main body of the encoder of an absolute encoder device. CONSTITUTION: An absolute encoder device is constituted of an absolute encoder section which outputs M sequences of absolute serial data and receiving circuit section 50 which receives the absolute serial data. The section 50 is provided with a serial-to-parallel converter 57 which receives the absolute serial data from the absolute encoder section and converts the received data into parallel data, error detector 61 which detects the error of the M sequences of absolute serial data based on M sequences of encoding systems, and conversion table 63 which converts the output of the converter 57 into binary data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute encoder device to which an M series is applied, and particularly to miniaturize an absolute encoder portion which is an encoder body.

[0002]

2. Description of the Related Art One embodiment of a conventional absolute encoder device is an absolute encoder device applying an M series, which has an absolute detecting means 21 and an incremental detecting means 27 as shown in the block diagram of FIG. In many cases, the absolute encoder unit 10 has a conversion means such as a conversion table for converting the M-sequence into binary data, and outputs the absolute data as binary data to the outside.

Further, the absolute encoder section 10
In order to reduce the number of connection lines between the receiver circuit unit 50 (hereinafter simply referred to as encoder unit 10), binary data is converted into serial data by a parallel-serial conversion circuit, and
An encoder that also has a CRC circuit that adds error detection bits such as a CRC check for outputting as serial data, and a circuit such as a modem that adds redundant bits such as a start bit and a stop bit for synchronization as an encoder body The serial binary data based on the absolute data output by the absolute detection means 21 is sequentially output by the modem provided inside the unit 10.

Further, the receiving circuit section 50 on the side of the receiving device receives the serial data sequentially output from the encoder section 10, detects a start bit and a stop bit, and converts the serial data into parallel data. Further, an error detection circuit such as a CRC check is provided, and a reversible counter that stores the value of absolute data and performs up-counting or down-counting with an incremental signal to output a pseudo-absolute signal is often provided.

In this absolute encoder device, as shown in FIG. 14, for example, an absolute track 13 having a pattern of a 4-bit M series is applied.
The encoder section 10 has a code plate 11 on which is formed, and the absolute track 13 is formed as a pattern in which 0 is added to the head of the 4-bit M sequence represented by the primitive polynomial of (Equation 1). .

[0006]

[Equation 1]

Further, the absolute detecting means 21 for detecting the absolute track 13 is usually composed of a plurality of detectors 23 for detecting 7 bits even when detecting a 4-bit M series. That is, a detector for detecting 4 bits is generally sufficient for detecting a 4-bit M-sequence pattern, but a detector 23 for 7 bits is used to detect an error. It is equipped.

Further, the code plate 11 has an incremental track 15 side by side with the absolute track 13, and an incremental detecting means 27 for detecting the rotation of the code plate 11 is provided.
, Two incremental detectors 29a and 29b are provided to form the A-phase output of the incremental signal and the B-phase output of the incremental signal. Then, the absolute detecting means 21 uses two detectors per bit to prevent a detection error at a signal change point, and a detector 23-1a which is a set of two detectors by phase A output of the incremental signal, 23-1b, 23-2a, 23-2b, 23-3a, 23
Since one of -3b, ..., Is selected and used, a total of 14 detectors 23 are used as the absolute detecting means 21.

The absolute detection means 21
The absolute data from is converted to binary data by the conversion table, and further sent as the absolute serial data by the parallel-serial converter to the receiving circuit section 50 by one signal line, and returned to the parallel signal by the serial-parallel conversion circuit and converted into various absolute data. In some cases, arithmetic control is performed, pseudo absolute data is formed from the absolute data and the incremental signal, and the pseudo absolute data is used as the absolute data.

[0010]

As described above, in the configuration of the conventional absolute encoder device, the number of electric circuits incorporated in the encoder section, which is the encoder body, increases, and there is a restriction on miniaturization of the encoder body. It is the current situation of giving. The present invention has been made in view of the above-mentioned problems, and deletes a conversion table and a circuit for error detection from the encoder body, and these circuits are conventionally provided in a receiving circuit unit on the receiving device side. It is an object of the present invention to reduce the number of electric circuits in the encoder body and provide a small-sized encoder section by making it a part of.

[0011]

In order to solve the above problems, according to the present invention, an encoder section for outputting M-sequence absolute serial data and a receiving circuit section for receiving the absolute serial data from the encoder section are provided. The receiving circuit section comprises: a serial-parallel converter for converting absolute serial data into parallel data; error detecting means for detecting an error in the previous M-series absolute serial data based on an M-series encoding formula; An absolute encoder device having a conversion table for converting the output of the serial-parallel converter into binary data.

The encoder section outputs an incremental signal together with the absolute serial data, and the absolute serial data is output in synchronization with the signal change of the incremental signal.
Further, the receiving circuit section may be provided with a receiving section timing generating means for detecting a change in the incremental signal from the encoder section and operating the serial / parallel converter when the incremental signal changes.

Further, the receiving circuit section may be provided with a reversible counter for loading the first data of the binary data after the power is turned on as an initial value and counting the incremental signal input from the encoder section. The encoder unit includes a code plate having a track on which an absolute pattern is formed and a track on which an incremental pattern is formed, an incremental detection unit that reads the incremental pattern of the code plate, and a change in the output of the incremental detection unit. Then, the absolute detection means that reads the absolute pattern into parallel data, the parallel-to-serial converter that outputs the absolute data to the outside as serial data, and the change in the output of the incremental detector are detected, and the The encoder unit is configured by the timing generation unit that operates the parallel-to-serial converter when the output changes.

Furthermore, the encoder section may be provided with an initial operating means for forcibly changing the incremental signal when the power is turned on. Then, the receiving circuit unit may be provided with a power supply control means for turning on the power of the absolute encoder again when the absolute serial data first sent from the absolute encoder when the power is turned on is not valid.

[0015]

[Operation] In the absolute encoder of the present invention, the data read from the M-series absolute pattern is output as it is, and the conversion means for the M-series absolute pattern is provided on the receiving circuit side. Since it is not necessary to provide any means, and the receiving circuit section has a detector for detecting an error in the M-sequence pattern itself, it is necessary to provide a circuit for adding an error detection bit such as a CRC check in the encoder section. Absent.

An absolute section is provided with an encoder section for outputting serial data in synchronization with a change in the incremental signal, and a receiving section timing generating means for detecting a change in the incremental signal and operating the serial / parallel converter in the receiving circuit section. Since the encoder device outputs absolute serial data in synchronization with the incremental signal and can use the incremental signal as a clock signal, it is not necessary to add a synchronization bit such as a start bit to the data, and synchronization can be performed in the receiving circuit section. It is possible to read the absolute serial data accurately, and there is no need to provide a circuit for adding an additional bit therefor in the encoder section.

Further, if a reversible counter for counting the incremental signal is provided in the receiving circuit section, a value based on the absolute data is appropriately preset in the reversible counter and the pseudo absolute data can be formed by counting the incremental signal. . When the initial operating means is provided, the incremental signal can be forcibly changed even when the code plate is stationary when the power is turned on, and the parallel-serial converter is activated by the incremental signal. Immediately after the power is turned on, absolute data can be output from the encoder section to know the absolute position of the encoder.

Further, when the power supply control means for turning on the power of the encoder unit again when the absolute serial data first sent from the encoder unit when the power is turned on is invalid, it is possible to accurately perform the operation when the power is turned on. If the absolute data with a different value is not output, the power can be turned on again and the absolute data can be read again.

[0019]

EXAMPLE An example of an encoder section in an absolute encoder apparatus according to the present invention uses a 4-bit M-sequence code plate 11 as shown in FIG. 14, and as shown in FIG. Detecting means 27, absolute detecting means 21, and parallel-serial converter
37, and an initial actuation means 41 and a timing generation means 31.

As described above, the absolute track of the code plate 11 is represented by the primitive polynomial of (Equation 1).
It is formed by a pattern in which 0 is added to the head of the M series of bits, and is provided with a 7-bit detector 23 for error detection, and to prevent a detection error at a signal change point,
Each detector 23-1a, using two detectors per bit,
The selection and use of 23-1b, 23-2a, 23-2b, 23-3a, 23-3b, ... With the incremental signal A-phase output is the same as the conventional one.

When the S input is H, the data selector 25 of the absolute detecting means 21 selects the input from the input terminals 1A to 7A from 7 of the 14 detectors, and A Each signal input from the input terminal is output from the Q output terminal, and when the S input is L, seven 1B to
The data selector 25 outputs each signal input from the 7B input terminal from the Q output terminal.

Further, when the start signal from the timing generating means 31 is input, the parallel-serial converter 37 sequentially switches the D1 to D7 inputs in synchronism with the clock input, and outputs the signals of the respective inputs as serial data SO. Is output from. The power supply voltage detection circuit 42, the delay circuits 43 and 44, and the logic gates 45 and 46 serve as an initial actuating means 41 that forcibly produces a change in the incremental signal when the power is turned on. 33
The logic gate 34 serves as a timing generating means 31 which detects a change in the incremental signal A phase output when the incremental signal B phase output is L and outputs a start signal to the parallel-serial converter 37.

In the absolute detecting means 21, as shown in the timing chart of FIG. 2, the changing points of Q1 to Q7 are synchronized with the changing points of the incremental detector 29a by the operation of the data selector 25. To take. Incidentally, FIG. 3 shows a timing chart of the encoder output signal at low speed rotation. At this time, the absolute serial data is output in synchronization with the A-phase output of the incremental signal.

Further, FIG. 4 shows a timing chart of encoder output signals during high speed rotation. At this time, the absolute serial data is output in synchronization with the output of the A phase of the incremental signal, but since the cycle of the A phase of the incremental signal is shorter than the transmission time of the absolute serial data, 7-bit data cannot be output. It will be. This will be dealt with by forming a pseudo absolute signal by the reversible counter 67 or the like on the receiving device side, as described later.

FIG. 5 shows an incremental detector.
The output of 29a is L, and the incremental detector 29
The encoder output signal timing chart when the power is turned on when the output of b is H is shown in FIG. 6, when the output of the incremental detector 29a is H and the output of the incremental detector 29b is L, when the power is turned on. 6 is a timing chart of the encoder output signal in FIG.

Normally, when the power is turned on, the encoder is often stationary, and the incremental signal does not change. Therefore, the absolute data is not output from the encoder section 10. However, in this embodiment, the power supply voltage detection circuit 42 used as the initial actuation means 41, the two delay circuits 43 and 44, and the logic gates 45 and 46 force the incremental signal B phase output to be L and the incremental signal A. A state in which the phase output changes is created, a start signal is input to the parallel-serial converter 37, and absolute serial data at power-on is output from the parallel-serial converter 37.

With this initial operating means 41, absolute serial data can be output from the encoder section 10 even if the encoder is stationary when the power is turned on. Further, as shown in FIG. 7, the receiving circuit section 50 on the receiving apparatus side includes a receiving section timing generating means 51, a serial / parallel converter 57, an error detector 61, and a conversion table 6.
3, a latch 65, a reversible counter 67, a data read control means 71, and the like.

The differentiating circuit 52, the inverter 53, and the logic gate 54 detect a change in the incremental signal A phase output when the incremental signal B phase output is L, and output a start signal to the serial / parallel converter 57. The timing generating means 51 is the same circuit as the timing generating means 31 provided in the encoder section 10. When the start signal is input, the serial-parallel converter 57 synchronizes the serial data input to SD in synchronization with the clock with Q7 to Q.
Converted to 1-bit 7-bit parallel data. However, if the cycle of the incremental signal becomes shorter than the conversion time at this time, the next start signal is generated before all the serial data is received, and accurate absolute data cannot be received. For this,
The serial-parallel converter 57 outputs an END signal from the serial-parallel converter 57 indicating that all 7-bit data has been received, and the received data is valid only when the END signal is output. The absolute data converted from data to binary data is read into the latch 65 and the reversible counter 67.

The contents of this conversion table 63 are shown in FIG.
The conversion table 63 converts the received M-series data into binary data in ascending / descending order and outputs it.
The latch 65 is a 4-bit latch circuit that holds the output of the conversion table 63, and the reversible counter 67 is a reversible counter 67 with a data loading function, and when a load signal is input, D1 to D7. Data is read and preset, and the preset value is sequentially up-counted or down-counted by an up signal and a down signal.

The up signal and the down signal are formed by the direction discriminating pulse converting circuit 69, and the incremental signal A phase output and B are output to the direction discriminating pulse converting circuit 69.
The phase output pulse input circuit 69 receives the phase output, generates the direction discrimination signal and the pulse signal based on the incremental signal, and causes the reversible counter 67 to output the up signal or the down signal.

Further, the error detector 61 is a detector as an error detecting means for detecting an error in the data by comparing the received 7-bit M-sequence absolute data with the primitive polynomial of (Equation 1). 9 shows an example of the error detector 61 on the receiving device side. Note that in FIG. 9, a detection circuit for a portion (data in which four 0s continue) in which the primitive polynomial of (Equation 1) does not hold is also added. Further, in the circuit example shown in FIG. 9, there are three sets of similar circuits, but this is for processing 7-bit data in parallel, and one set can be carried out by processing serially. Then, not only a combination of logic circuits as shown in FIG. 9 but also an element for detecting an error by program processing can be used.

Further, the logic gates 72, 73, 74 and the D-flip-flop 75 output enable and load signals when valid data can be received and output the conversion table 63 to the reversible counter 67 and the latch 65. Data read control means 71 for reading a signal, and when the error detector 61 does not output an error signal when the serial / parallel converter 57 outputs an END signal, the load signal is latched by the reversible counter 67 or the latch. It is output to 65, and the enable signal is raised in accordance with the output of the first load signal.

Further, the inverter 82 and the logic gates 83 and 84 are the error detector 61, which is the power supply control means 81 which outputs an OFF-ON signal to the encoder power supply 87 when an error signal is generated. When the error detector 61 outputs an error signal while the data reading control means 71 does not output the enable signal due to the incremental signal,
The encoder power supply 87 is once turned off, and the power of the encoder unit 10 is turned on again.

Therefore, in the receiving circuit section 50, the serial / parallel converter 57 receives the serial data Q7 input to the SD in synchronization with the clock when the start signal is input.
When the serial-to-parallel converter 57 receives all the 7-bit data and outputs Q7 to Q1, the END signal terminal also outputs the END signal. Then, the Q7 to Q1 outputs of the serial-parallel converter 57 are input to the error detector 61, it is determined whether the data is correct or not by comparing with the primitive polynomial, and when the END signal is output, the error detector 61 outputs If no error signal signal is output, the data read control means 71 outputs a load signal or an enable signal, and the load signal output by the data read control means 71 causes the latch 65 or the reversible counter 67 to output the conversion table 63. By reading the binary data and validating the received data, the absolute data based on the 7-bit data can be used accurately.

As the enable signal, when the serial / parallel converter 57 outputs the END signal after the timing signal from the receiver timing generating means 51 is input, the error detector 61 outputs the H level error signal signal. If it is not output, it is output from the data read control means 71 and continues until the power is turned off. Further, in the present embodiment, the absolute serial data received by the signal receiving unit 50 is such that only the continuous 4 bits necessary for obtaining the absolute data are input to the conversion table 63. In FIG. 4 bits are used.

FIG. 10 shows a timing chart of OFF-ON signals to the serial / parallel converter 57, the error detector 61, and the encoder power supply 87 when data is received without error. Further, FIG. 11 shows OFF-ON for the serial / parallel converter 57, the error detector 61, and the encoder power supply 87 when the data is erroneously received.
The timing chart of a signal is shown.

In such a case, the serial / parallel converter
When the start signal is input, 57 converts the serial data input to SD in synchronization with the clock into 7-bit parallel data of Q7 to Q1. When the END signal is output, the error detector 61 outputs an H level error signal signal. Therefore, the encoder power supply 87 is turned off and on according to the END signal and the error signal, and the encoder unit 10
To retransmit the data and receive the data again.

Further, when the cycle of the incremental signal is shorter than the conversion time, the next start signal is generated before all the serial data is received, and accurate absolute data cannot be received. On the other hand, the END signal indicating that all the 7-bit data has been received from the serial-parallel converter 57 is not output, and the receiving circuit section 50 outputs the END signal as described above, and this If the error signal is not output at this time, the received data is assumed to be valid, so the inaccurate absolute data output from the serial / parallel converter 57 and output from the conversion table 63 at this time is not latched by the latch 65 or reversible. Nothing is input to the counter 67.

FIG. 12 shows a timing chart of the entire receiving device side. When valid data is received after the power is turned on, the reversible counter 67 loads the first valid binary data converted by the conversion table 63 as an initial value, and thereafter when the incremental signal B-phase output is L. Is counted up at the rising edge of the incremental signal A-phase output, and is down-counted at the falling edge of the incremental signal A-phase output when the incremental signal B-phase output is L. Since the edge of the incremental signal A phase output when the incremental signal B phase output is L and the changing point of the absolute data match, the count data of the reversible counter 67 always matches the absolute position of the encoder. The count data of the reversible counter 67 is used as pseudo absolute data.

As described above, by outputting the pseudo absolute data based on the count value of the reversible counter 67, even if the encoder rotates quickly and the absolute serial data is not correctly output from the encoder section 10, the You can always get the absolute position of the encoder. Also a reversible counter
The 67 loads the absolute data at that time every time valid data is received regardless of the count value even during operation, and matches the pseudo absolute data value with the absolute data value. If so, if the encoder's speed is correct, the absolute data can be loaded to keep the pseudo-absolute data value correct and the last valid data received is also held in latch 65. Will be done.

As shown in FIG. 12, the changing point of the absolute data and the changing point of the incremental signal are synchronized, and the incremental signal can be divided into four absolute positions within one cycle, so the resolution is four times as high. Absolute data, that is, 6-bit absolute data can be obtained. In addition, if it is a multi-rotation type absolute encoder, it is possible to output multi-rotation data together with M-sequence data, and it is also possible to output information such as an alarm at the same time.

In the above embodiment, the 4-bit M series absolute data is used. However, the absolute data is not limited to 4 bits and may be a M series having a larger number of bits. As described above, in the encoder unit 10 in the present embodiment, the data read from the M-series absolute pattern recorded on the first track is output as it is, so that the conversion table 63 or the like is converted in the encoder body. No means is required, and a circuit for adding an error detection bit such as a CRC check is not required in the encoder unit 10 as the encoder body by utilizing the error detection capability of the M-sequence pattern itself.

Further, since the serial data is output in synchronization with the change of the incremental signal, it is not necessary to add a bit for synchronization such as a start bit to the data, and the circuit therefor is also the encoder unit 10 which is the encoder body. There is no inside. Therefore, the number of electric circuits in the encoder body is small, and a small encoder unit 10 can be provided.

Further, when the power is turned on, the absolute detecting means 21 is operated by forcibly changing the incremental signal so that the absolute data is output even if the encoder is stationary. The absolute position of the encoder can be known immediately after turning on the power. Thus, the present embodiment, the incremental detection means 29, the absolute detection means 21 to read the absolute pattern in parallel data in synchronization with the output change of the incremental detection means 29,
The encoder section 10 is configured by the parallel-serial converter 37 that outputs absolute data as serial data to the outside, and the timing generation means 31 that operates the parallel-serial converter 37. Further, the conversion table 63 and the error detection means are provided. By providing the error detector 61, the receiving section timing generating means 51, etc. as a part of the receiving circuit section 50 on the receiving device side, it is possible to delete the converting means and the redundant bit addition circuit from the encoder body. Thus, it is possible to provide an absolute encoder device in which the encoder unit 10 as the absolute encoder body is downsized.

In the above embodiment, the encoder section 10 is provided with the timing generating means 31, the receiving circuit section 50 is provided with the receiving section timing generating means 51, and the encoder section 10 and the receiving circuit section 50 are provided with reference to the incremental signal. Even if the start of serial data is matched, the encoder unit 10
From the parallel serial-to-serial converter 37 in the encoder unit 10 according to the start reference signal that is output only from the absolute serial data and output from the receiving circuit unit 50.
It is also possible to synchronize the serial-parallel converter 57 in the receiving circuit section 50 with that.

In this case, the encoder section 10 and the receiving circuit section
Since the absolute data line and the start reference signal line are used as two signal lines with 50, there is an advantage that the encoder unit 10 can be further downsized. However, in this case, the serial transmission speed may limit the use of the high-speed rotation of the encoder.

[0047]

As described above, the absolute encoder device according to the present invention includes an encoder unit for outputting M series of absolute serial data, a serial / parallel converter for receiving the absolute serial data and converting it into parallel data. Since it is configured with a receiving circuit section having an error detecting means for detecting an error in the M-series absolute serial data based on the M-series encoding formula, the receiving circuit section can read correct absolute data, and the encoder The number of circuits incorporated in the unit can be reduced, and the encoder unit can be downsized.

The absolute encoder device outputs absolute serial data in synchronization with the incremental signal, and the receiving circuit portion is provided with the receiving portion timing generating means. The absolute encoder device uses the incremental signal used in combination with the absolute data. The absolute serial data can be easily read accurately by synchronizing with the receiving circuit section.

Further, the absolute encoder device provided with the reversible counter in the receiving circuit section can form the pseudo absolute data by preset-loading the value based on the absolute data into the reversible counter and counting the incremental signal. Even if the absolute serial data is not accurately output from the encoder unit due to the high speed rotation of the encoder, the correct rotation position can always be detected by the pseudo absolute data formed in the receiving circuit unit.

Further, a code plate on which an absolute pattern or an incremental pattern is formed, an absolute detection means, an incremental detection means, and a parallel / serial converter or a parallel output which outputs the parallel output of the absolute detection means to the outside as serial data. The encoder unit having the timing generating means for activating the serial converter can easily form the absolute serial data synchronized with the incremental signal, and the encoder unit that outputs the incremental signal and the absolute serial data synchronized with the incremental signal is provided. It can be easily manufactured in a small size.

The encoder section having the initial operation means for forcibly generating the change in the output of the incremental detecting means when the power is turned on has the incremental signal and the absolute serial data even if the encoder is not rotating when the power is turned on. Can be output, and the rotational position can always be detected by the receiving circuit unit when the power is turned on.

Further, the absolute encoder device provided with the power supply control means in the receiving circuit section for re-turning on the power when the absolute serial data is not valid when the power is turned on can always make a correct start-up by re-turning on.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an encoder section in an embodiment of an absolute encoder device according to the present invention.

FIG. 2 is a timing chart of encoder output in the absolute encoder device according to the present invention.

FIG. 3 is a timing chart of an encoder output signal at low speed rotation in the absolute encoder device according to the present invention.

FIG. 4 is a timing chart of encoder output signals during high-speed rotation in the absolute encoder device according to the present invention.

FIG. 5 is a timing chart of an encoder output signal when the power is turned on in the absolute encoder device according to the present invention.

FIG. 6 is a timing chart of an encoder output signal when the power is turned on in the absolute encoder device according to the present invention.

FIG. 7 is a circuit block diagram on the receiving device side in the embodiment of the absolute encoder device according to the present invention.

FIG. 8 is a conversion table in the embodiment of the absolute encoder device according to the present invention.

FIG. 9 is an error detector in the embodiment of the absolute encoder device according to the present invention.

FIG. 10 is a timing chart of the receiving device side when the power is turned on in the absolute encoder device according to the present invention.

FIG. 11 is a timing chart of the receiving device side when the power is turned on in the absolute encoder device according to the present invention.

FIG. 12 is a timing chart on the receiving device side in the embodiment of the absolute encoder device according to the present invention.

FIG. 13 is a block diagram of a conventional absolute encoder device.

FIG. 14 is a configuration diagram of a detector in the conventional example and the present example.

[Explanation of symbols]

 10 Absolute Encoder Section 11 Code Board 13 Absolute Track 15 Incremental Track 21 Absolute Detection Means 23 Absolute Detector 25 Selector 27 Incremental Detection Means 29 Incremental Detector 31 Timing Generation Means 32 Differential Circuit 33 Inverter Gate 34 AND Gate 35 Oscillator 37 parallel-serial converter 41 initial operation means 42 power supply voltage detection circuit 43 delay circuit 44 delay circuit 45 EOR gate 46 AND gate 50 receiving circuit section 51 receiving section timing generating means 52 differentiating circuit 53 inverter 54 NAND gate 57 serial-parallel converter 61 Error detector 63 Conversion table 65 4-bit latch 67 Reversible counter 69 Direction discrimination pulse conversion circuit 71 Data Read Control Means 72 OR Gate 73 OR Gate 75 D-Flip Flop 74 AND Gate 81 Power Supply Control Means 82 Inverter Gate 83 3 Input OR Gate 84 AND Gate 87 Power Supply for Encoder

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toru Morita 3-2-3 Marunouchi, Chiyoda-ku, Tokyo Inside Nikon Corporation

Claims (6)

[Claims] 1. An absolute encoder section for outputting M-sequence absolute serial data, and a receiving circuit section for receiving the absolute serial data, wherein the receiving circuit section is the absolute serial signal from the absolute encoder section. A serial-parallel converter that receives data and converts it into parallel data, an error detection unit that detects an error in the previous M-series absolute serial data based on an M-series coding equation, and an output of the serial-parallel converter. An absolute encoder device, comprising: a conversion table for converting into binary data. 2. The absolute encoder section outputs an incremental signal together with the absolute serial data, and outputs the absolute serial data in synchronization with a signal change of the incremental signal, and to the receiving circuit section, The receiver timing generating means for detecting a change in the incremental signal from the absolute encoder section and operating the serial-parallel converter when the incremental signal changes is provided. Absolute encoder device. 3. The receiving circuit section has a reversible counter that loads the first data of the binary data after power-on as an initial value and counts an incremental signal input from the absolute encoder section. The absolute encoder device according to claim 2. 4. The absolute encoder unit is M
A code plate having a first track on which an absolute pattern is formed by applying a sequence and a second track on which an incremental pattern is formed; and an incremental detecting means for reading the incremental pattern,
An absolute detection unit that reads the absolute pattern and outputs it as parallel data in synchronization with the output change of the incremental detection unit, and a parallel output that outputs the parallel output of the absolute detection unit as serial data from the absolute encoder unit to the outside. A serial converter and timing generation means for detecting a change in the output of the incremental detector and activating the parallel-serial converter when the output of the incremental detector changes. The absolute encoder device according to claim 2 or 3. 5. The absolute encoder section has an initial actuating means for forcibly generating a change in the output of the incremental detecting means when the power is turned on. The described absolute encoder device. 6. The receiving circuit section has power control means for turning on the power of the absolute encoder section again when the absolute serial data first sent from the absolute encoder section when the power is turned on is not valid. Claim 1 thru | or 5 characterized by the above-mentioned.
An absolute encoder device described in any one of 1.