JPH08204991A - Detection circuit for frame synchronizing signal - Google Patents

Abstract

PURPOSE: To detect frame pulses even when the DC component of input MUSE signals and an amplitude value are not normal at the time of supplying power and at the time of switching input signals. CONSTITUTION: This circuit is constituted or a maximum value detection circuit 510 for detecting the maximum value in a fixed period of the input MUSE signals, a minimum value detection circuit 520 for detecting a minimum value, an adder 530 for adding the maximum value and the minimum value, a 1/2 circuit 540 for supplying the intermediate value, a delay circuit 500 for delaying the input MUSE signals and a comparator circuit 600 for performing comparison with the input MUSE signals with the intermediate value as a threshold value. Then, by binarizing the input MUSE signals with a value which is the 1/2 of the maximum value and the minimum value of a frame pulse part as the threshold value, even when the DC component of the input MUSE signals are not a normal value or when the level of amplitude is not normal, the frame pulses are surely detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame sync signal detection circuit, and more particularly to MUSE (Multiple Sub-N).
yquist Sampling Encoding)
The present invention relates to a frame synchronization signal detection circuit for detecting a frame timing of a television signal of a system.

[0002]

2. Description of the Related Art The MUSE system has been adopted as a system for band-compressing high-definition television signals for analog transmission. A signal band-compressed by this MUSE method (hereinafter, simply referred to as MUSE signal) is transmitted in a format as shown in FIG. As the sync signal of the MUSE signal, there are two positive sync formats of the HD signal and the frame pulse signal.

FIG. 9 is a waveform diagram of a frame pulse signal. This frame pulse signal is sample No. 1 of the first line and the second line of the MUSE signal. It is inserted between 317 and 480. Line No. 1 frame pulse is 1
The frame pulse of the second line is a signal in which the polarity of the first line is inverted. Here, the clock (ck) is a sampling clock when the MUSE signal is digitized, and the same applies hereinafter.

FIG. 10 shows the HD signal waveform. Sample No. of each line is shown. 1 to 11 are inserted as signals having a trapezoidal waveform and inverted every line. In addition, in FIG. Levels 1 and 11 are the following values. No. 1 is the immediately preceding signal level and HD waveform sample No. No. 2 is the arithmetic mean value with the level of 2. No. 11 is the signal level immediately after and HD waveform sample No. 11. It is an arithmetic mean value with 10 levels.

As a signal for reproducing the direct current component of the MUSE reception signal, sample Nos. A clamp level signal is inserted in 107 to 480. This clamp level signal is MU
When the SE signal is expressed by 8 bits (256 values), it is 12
It is defined as 8. This corresponds to the intermediate value of the video signal.

The MUSE decoder requires the above three types of signals in order to reproduce the synchronization. The basis of the synchronization detection is the detection of the frame pulse, and the processing such as the detection of the HD signal and the detection of the clamp level signal is performed with this signal as a reference.

A method of detecting a frame pulse in the conventional MUSE decoder will be described below with reference to FIG. In FIG. 5, the MUSE signal is input to the input terminal 1,
The / D converter 2 converts it into a 10-bit digital MUSE signal, and the LPF 4 reduces the noise component.

MSB of output of LPF4 (most significant bit)
Are supplied to the frame pulse detection circuit 700. The frame pulse detection circuit 700 detects the frame pulse pattern and outputs it to the output terminal 9 as a detected frame pulse.

As described above, conventionally, the frame pulse signal is detected from the MSB of the A / D converted digital MUSE signal.

When normal clamping is performed, A /
In the D-converted digital MUSE signal, the direct current component according to the format of the MUSE signal is reproduced, and when the maximum value and the minimum value of the frame pulse waveform change, it always crosses the midpoint of the digital signal, so the change in MSB The frame pulse can be detected. However, since the clamp level signal cannot be detected until after the frame pulse is detected, the DC component of the input MUSE signal shifts when the power is turned on or the input is switched, and the frame pulse crosses the MSB. If not, there is a problem that the frame pulse cannot be detected.

This state is shown in FIG. Input axis is MU
The digital value when the SE signal is A / D converted with 10 bits, the horizontal axis is time, the waveform is a part of the frame pulse, and each state represents a difference in DC component of the input MUSE signal.

The change point of the MSB is 200H (hexadecimal number), which corresponds to the state (1) of FIG. 6 when the clamp is performed normally, and it can be seen that the change of the frame pulse can be expressed by the MSB. However, state (2)-
When the normal clamping is not performed as in (5), the frame pulse does not cross the MSB change point (200H), so that the frame pulse cannot be detected depending on the MSB.

Therefore, there is a method of performing clamping with the average value of the video signal and gradually changing to a normal DC component. However, it takes time to reproduce the DC component, and as a result, it takes time to detect the frame pulse. Alternatively, if the video signal is entirely black or white, and the average value of the video signal is significantly different from the clamp level, the frame pulse may not be detected.

As a solution to this problem, there is a known example in which frame pulse detection is performed using three types of threshold values.
It is disclosed in Japanese Patent No. 23775. This known example will be described below with reference to FIGS. 6 and 7.

The MUSE signal is input to the input terminal 1,
The / D converter 2 converts the signal into a 10-bit digital MUSE signal, the LPF 4 reduces a noise component, and the noise is supplied to the comparators 600, 601, 602. The set values (1), (2) and (3) are given to each comparator, and the digital MU is supplied.
The SE signal and each set value are compared with each other, and when the value is equal to or more than the set value, the H level is output, and when the value is less than the set value, the L level is output to the frame pulse detection circuits 700, 701 and 702, respectively.

Frame pulse detection circuits 700, 701,
702 detects the frame pulse pattern, and outputs the detected frame pulse to the logical OR circuit 8.
The logical OR circuit 8 takes the logical sum of three types of detection frame pulses and outputs it to the output terminal 9 as a detection frame pulse.

Normally, the set value (1) is set to 200H, which corresponds to detection using MSB. Also, the set value (2) and the set value (3) are 300H and 100H corresponding to 3/4 and 1/4 of the level of the digital MUSE signal, respectively.
Are set respectively.

With this circuit, it is possible to detect the frame pulse even in the state (2) and the state (3) of FIG. 6, but depending on the set value, for example, the state (4) and the state (5) of FIG. There are cases where the frame pulse cannot be detected. Further, three frame pulse detection circuits having a large circuit scale are required, which causes a problem of increasing the overall circuit scale.

[0019]

As described above, in the conventional sync detecting circuit, the DC component of the input MUSE signal is deviated when the power source is turned on or when the input signal is switched by channel switching or station switching. If the frame pulse does not cross the MSB, there is a problem that it takes time to detect the synchronization or the frame pulse cannot be detected until the DC component approaches the normal value by the clamp.

Further, the above-mentioned Japanese Patent Laid-Open No. 3-23775 also has a problem that the frame pulse cannot be detected or the circuit scale becomes large depending on the set value.

Therefore, an object of the present invention is to provide a frame synchronization signal detection circuit which surely detects a frame pulse without a large increase in circuit scale even when the direct current component of the input MUSE signal is not accurately reproduced. .

[0022]

According to the present invention, the MUS
A frame synchronization signal detection circuit for detecting a frame pulse from an E signal to perform synchronization detection, which is a digitized M
Maximum value detecting means for detecting a maximum value of the USE signal in a predetermined period; minimum value detecting means for detecting a minimum value of the digitized MUSE signal in the predetermined period;
An intermediate value generating means for generating an intermediate value between the maximum value and the minimum value, and the digitized M using the intermediate value as a threshold value.
A frame synchronization signal detection circuit is obtained which includes a comparison unit for binarizing the USE signal, and the frame pulse is detected by the binarized signal.

[0023]

The maximum value and the minimum value of the input MUSE signal for a certain period or more are detected, the intermediate value between the maximum value and the minimum value is detected, and the intermediate value between the maximum value and the minimum value is held, and The frame pulse included in the MUSE signal is detected using the value as a threshold.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, the same parts as those of the conventional example shown in FIGS. 5 and 7 are designated by the same reference numerals.

The difference from the circuit of FIG. 5 is that the dotted line portion shown in FIG. 1 is added. M input to input terminal 1
The USE signal is 16.2 MHz by the A / D converter 2.
Exchanged with a digital signal of rate 10 bits. LP
After the noise component is removed in F4, the upper 4 bits are the delay circuit 500, the maximum value detection circuit 510, and the minimum value detection circuit 5.
It is input to 20.

Maximum value detection circuit 510 and minimum value detection circuit 5
The reset pulse input to 20 is a negative pulse having a 5-clock cycle of a 16.2 MHz clock and a 1-clock width. The outputs of the maximum value detection circuit 510 and the minimum value detection circuit 520 are added by the adder 530, and the 1/2 circuit 5
It is halved at 40.

The latch pulse input to the 1/2 circuit 540 is a positive polarity pulse having a 5-clock cycle of a 16.2 MHz clock and a 1-clock width. Delay circuit 500
And the output of the 1/2 circuit 540 are input to the comparator 600 as a comparison signal.

Comparator 600 outputs the H level when the output of delay circuit 500 is larger than the output of 1/2 circuit 540, and outputs the L level when it is smaller or equal. The output of the comparator 600 is input to the frame pulse detection circuit 700, the frame pulse detection circuit 700 detects the pattern of the frame pulse, and outputs it as a detected frame pulse to the output terminal 9.

The circuit of the portion surrounded by the dotted line in FIG. 1, which is a characteristic portion of the embodiment of the present invention, will be described in detail below with reference to FIG. 2 and the timing chart of FIG. 3 showing the operating principle.

The dotted line 510 is the maximum value detection circuit 510 of FIG.
Further, the dotted line 520 corresponds to the minimum value detection circuit 520 of FIG. 1, and the dotted line 540 corresponds to the 1/2 circuit 540 of FIG.

First, the maximum value detection circuit 510 will be described. The output 4 bits of the LPF 4 is the input A of the comparator 511.
Is input to the input a of the switch 512. Switch 51
The polarity of 2 is switched by the output A ≧ B of the comparator 511, and becomes the side a when A ≧ B. The output of the switch 512 is input to the D flip-flop 513,
It is held by the MHz clock.

The output of the D flip-flop 513 is logical A
It is output to the ND circuit 514 and the adder 513. Logical AN
Although not shown, the reset pulse having the timing shown in FIG. 3 is supplied to the other input of the D circuit 514 from the internal timing generation circuit. Logical AND circuit 514
Is supplied to the input b of the switch 512 and the input B of the comparator 511.

Next, the minimum value detection circuit 520 will be described. The upper 4 bits of the output of the LPF 4 are input to the input A of the comparator 521 and the input a of the switch 522. The polarity of the switch 522 is switched depending on the output of the comparator 521, that is, the output of A ≦ B. Switch 52
The output of 2 is input to the D flip-flop 523, and 1
It is held at a clock of 6.2 MHz.

The output of the D flip-flop 523 is a logical O.
It is output to the R circuit 524 and the adder 530. The reset pulse is inverted by the logic inversion circuit 525 and supplied to the other input of the logic OR circuit 524. The output of the logical OR circuit 524 is supplied to the input b of the switch 522 and the input B of the comparator 521.

The maximum value detection circuit 5 is added by the adder 530.
10 and the output of the minimum value detection circuit 520 are added.

Next, the 1/2 circuit 540 will be described.
The output of the adder 530 is halved by the halving circuit 541 and input to the D flip-flop 542. A half value of the maximum value and the minimum value, that is, an intermediate value is held by the latch clock at the timing shown in FIG. The latch clock is supplied from the timing generation circuit similarly to the reset pulse.

The output of the 1/2 circuit 540 is supplied to the input B of the comparator 600. The upper 4 bits of the output of the LPF 4 are input to the delay circuit 500, delayed by the clock of 16.2 MHz, and supplied to the input A of the comparator 600. The delay here depends on the cycle of the reset pulse and corresponds to one detection period for detecting the maximum value and the minimum value.

The comparator 600 uses the output of the 1/2 circuit 540 as a threshold value, and when the output of the delay circuit 500 is larger than this threshold value, outputs the H level to the frame pulse detection circuit 700 and the L level to the frame pulse detection circuit 700, respectively. .

The operation of each part will be described with reference to the timing chart of FIG. 3 showing the operating principle. In FIG. 2, the upper 4 bits of the MUSE signal are input to the input A of the comparator 511 and the input A of the comparator 521, and assume the values of 5H and BH in the frame pulse portion in the normal clamp state. . The state corresponds to the state (1) in FIG.

First, the maximum value detection circuit 510 will be described. In FIG. 3, the reset pulse is considered from the L level position. The input B of the comparator 511 is set to 0H by the logical AND circuit 514 because the reset pulse is at L level. In all cases, the comparator 511 is in the state of A ≧ B, so the output A ≧ B of the comparator 511 is at the H level, and the switch 512 is switched to the a side.

The D flip-flop 513 holds the output of the LPF 4 for one clock, and the value is supplied to the input B of the comparator 511 and the b side of the switch 512 via the logical AND circuit 514. The comparator 511 compares the output of the LPF 4 with the output of the LPF 4 one clock before. The output of the comparator 511 selects the one with a higher level by the switch 512, and the D flip-flop 513.
Held in. By repeating the above operation, the maximum value up to that point is held in the D flip-flop 513 until the reset pulse becomes the L level next time.

Similarly, the minimum value detection circuit 520 will be described. Since the reset pulse is inverted and the input B of the comparator 521 is at the H level, it is set to FH by the logical OR circuit 524. In all cases, the comparator 521 is in the state of A ≦ B, the output A ≦ B of the comparator 511 is at the H level, and the switch 522 is switched to the a side.

The D flip-flop 523 holds the output of the LPF 4 for one clock, and the value is held by the logical OR circuit 5.
24, the input B of the comparator 521 and the b of the switch 522.
Supplied to the side. The comparator 521 compares the output of the LPF4 with the output of the LPF4 one clock before.
According to the output of the comparator 521, the one with the smaller level is selected by the switch 522 and held by the D flip-flop 523. By repeating the above operation, the minimum value up to that point is held in the D flip-flop 523 until the reset pulse becomes the L level next time.

Since the outputs of the maximum value detection circuit 511 and the minimum value detection circuit 520 are the maximum value and the minimum value for the past 5 clocks, the frame pulse is 4 clocks and the L level and the H level alternate. So at least 1
The H level and the L level for the clock can be detected.

The maximum value and the minimum value detected through the above process are added by the adder 530, and 1 is added by the halving circuit 541.
It is set to / 2 and held as an intermediate value in the D flip-flop 542. In this case, this intermediate value is 8H. As can be seen from FIG. 6, this is 200H in 10 bit notation.
That is, it corresponds to the change point of the MSB. By using this signal as a threshold and comparing it with the output of the LPF 4 delayed by 5 clocks of the 16.2 MHz clock by the comparator 600, the waveform of the frame pulse is output as a binary signal to the frame pulse detection circuit 700. Then, the frame pulse detection circuit 700 detects the frame pulse by matching with the frame pulse pattern. When the regular clamp is performed in this manner, the detection is equivalent to the detection using the MSB shown in FIG.

Next, when the DC component of the input MUSE signal is extremely far from the normal level and the amplitude does not reach the normal level, for example, an example of the state (5) in FIG. 6 will be described. In this case, the input A of the comparator 511 and the comparator 52
The input A of 1 has values of 0H and 2H in the frame pulse portion. Even in this case, as shown in the timing chart of FIG. 4, from the output A> B of the comparator 600,
It can be seen that it is possible to detect the pattern of frame pulses.

Similarly, even in the states (2) to (5) of FIG. 6, it is possible to detect the pattern of the frame pulse. That is, if the amplitude of the frame pulse of the input MUSE signal is at a level equal to or higher than the resolution of 4 bits, the frame pulse can be detected.

As described in the embodiment, in the present invention, the MU
The feature is that the level of the frame pulse portion of the SE signal is detected, and the frame pulse is detected by binarizing the MUSE signal with an intermediate value thereof, so that the frame pulse can be detected reliably.

In this embodiment, the MUSE signal to be detected has 4 bits, but it does not have to be 4 bits and may be 2 to 10 bits depending on the desired detection accuracy. Further, although one detection period is set to 5 clocks in this embodiment, the L level and the H level of the frame pulse change every 4 clocks, so it may be 5 clocks or more.

[0051]

As described above, in the synchronization detection circuit according to the present invention, the DC component of the input MUSE signal is deviated when the power source is turned on or when the input signal is switched by channel switching, station switching, or the like. Thus, the frame pulse can be detected even if the frame pulse does not extend over the MSB or if the frame pulse does not have a normal amplitude, and the frame pulse can be reliably detected without a large increase in the circuit scale. .

Further, the time until the frame pulse is detected can be shortened when the power is turned on, or when the input signal is switched by channel switching or station switching.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a dotted line portion in FIG.

FIG. 3 is an example of a timing chart showing the principle of the embodiment of the present invention.

FIG. 4 is another example of a timing chart showing the principle of the embodiment of the present invention.

FIG. 5 is a block diagram of a conventional circuit.

FIG. 6 is a diagram showing a level state of a frame pulse.

FIG. 7 is a diagram showing an example of a conventional frame pulse detection circuit.

FIG. 8 is a diagram showing a transmission format of a MUSE signal.

FIG. 9 is a diagram showing a waveform of a frame pulse signal.

FIG. 10 is a diagram showing a waveform of an HD signal inserted in a MUSE signal.

[Explanation of symbols]

 1 Input Terminal 2 A / D Converter 3 Digital MUSE Signal 4 LPF 500 Delay Circuit 510 Maximum Value Detection Circuit 520 Minimum Value Detection Circuit 530 Adder 540 1/2 Circuit 600-602 Comparator 700-702 Frame Pulse Detection Circuit 8 Logic OR circuit 9 detection frame pulse

Claims (3)

[Claims] 1. A frame synchronization signal detection circuit for detecting synchronization by detecting a frame pulse from a MUSE signal, the maximum value detection means detecting a maximum value of a digitized MUSE signal in a predetermined period, and the digital signal. A minimum value detecting means for detecting a minimum value of the converted MUSE signal in the predetermined period, an intermediate value generating means for generating an intermediate value between the maximum value and the minimum value, and the digitized value using the intermediate value as a threshold value. A frame synchronization signal detection circuit, comprising: a comparator for binarizing the MUSE signal, and the frame pulse being detected by the binarized signal. 2. The frame synchronization signal according to claim 1, wherein the comparison means is configured to compare the signal obtained by delaying the digitized MUSE signal for the predetermined period with the threshold value. Detection circuit. 3. The frame synchronization signal detection circuit according to claim 1, wherein the predetermined period is a period having a width of 5 clocks or more of a sampling clock when the MUSE signal is digitized.