JPH08204565A - Semiconductor device and its driving method - Google Patents

Abstract

PURPOSE: To easily change the input terminal potential of a comparison and discrimination means, which detects a minute voltage to compare and discriminate it, from the middle point level of a discrimination threshold to an arbitrary potential level. CONSTITUTION: After a switch means M1 is turned on to set the input terminal and the output terminal of a comparison and discrimination means 30 to the same potential, the switch means M1 is turned off to set the input terminal of the comparison and discrimination means 30 to the floating state. After a voltage is applied from at least one or more input terminals 200 out of plural input terminals to shift the input terminal 10 of the comparison and discrimination means 30, which is set to the floating state, from the middle point level to a desired level, voltages are applied from the other input terminals 1 to (n) to make the comparison and discrimination means 30 perform the inverting operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a semiconductor circuit having a plurality of input terminals, each of which is commonly connected via a capacitance means and the input terminal of an inverter amplifier is connected to the common connection terminal. The present invention relates to a semiconductor device that detects a minute voltage and performs comparison determination, and a driving method thereof.

[0002]

2. Description of the Related Art Comparison of minute voltages using a semiconductor circuit having a plurality of input terminals, each of which is commonly connected through a capacitance means, and an input terminal of an inverter amplifier is connected to the common connection terminal. FIG. 2 shows a conventional example of a circuit for making a judgment.

2, C1, C2, C3, ... Cn are capacitors, 10 is an input terminal of an inverter amplifier, 100 is an output terminal of an inverter amplifier, and M1 is an inverter amplifier. A switch provided between the output terminal and the input terminal of the switch 20 is a control terminal of the switch. In this configuration, when the potential difference of VH is applied to the first signal input terminal with the switch M1 turned off and the input terminal of the inverter amplifier is in a floating state, the voltage amplitude Vfg generated at the input terminal of the inverter amplifier is , Vfg = VH * C1 / {C1 + C2 + C3 + ... + Cn} (1) Here, for example, if C1 = C2 = C3 ... = Cn, Vfg becomes VH / n, and C1 = (C2) / 2 =
If (C3) / 4 = ... (Cn) / 2 ^(n-1) , Vfg is V
H / 2 ^(n-1) , which becomes very small according to the value of n (when n = 8 and VH = 5V, 625 mV and 20 m, respectively)
V).

In order to detect such a minute voltage change,
In this conventional example, before applying an input signal to each signal input terminal, the switch M1 is turned on once, the input terminal potential of the inverter amplifier is clamped to the midpoint level of the transfer characteristic of the inverter, and the inverter amplifier has the most voltage gain. Set to a high operating point. After that, if the input signal is applied to a certain signal input terminal after the switch M1 is turned off, for example, even if the voltage amplitude Vfg generated at the input terminal of the inverter amplifier is as small as several tens mV, the inverter amplifier Since the voltage gain is high, the inversion operation of the inverter amplifier is caused by the minute voltage, and as a result, highly accurate detection of potential change and comparison determination can be realized.

[0005]

However, in the above-described conventional example, after the inverter amplifier is clamp-reset to the midpoint level, the inverter amplifier is immediately inverted with respect to the positive potential change applied to each signal input terminal. Since it is designed, if it is necessary to perform control such that the inverter amplifier is inverted only after a potential change of a certain potential level or more occurs after the clamp reset to the midpoint level, it is applied as it is. There is a problem that you cannot do it.

SUMMARY OF THE INVENTION Therefore, according to the present invention, when a minute voltage is detected and a comparison judgment is executed, a potential change above an arbitrary potential level occurs only after resetting once to the midpoint level as described above. An object of the present invention is to realize a semiconductor device capable of inverting an inverter amplifier and a driving method thereof.

[0007]

In order to achieve the above object, the present invention has a plurality of input terminals, each input terminal being commonly connected through respective capacitance means, and being connected to the common connection terminal. The input terminal of the comparison judgment means is connected,
In a method of driving a semiconductor device in which a switch means is provided between an output terminal and an input terminal of the comparison / determination means, after the switch means is turned on and the input terminal and the output terminal of the comparison / determination means are set to the same potential. An input terminal of the comparison and determination means in the floating state by applying a voltage from at least one or more input terminals of the plurality of input terminals by turning off the switch means and setting an input terminal of the comparison and determination means in a floating state. A method for driving a semiconductor device, comprising: shifting the terminal potential from a midpoint level to a desired level and then applying a voltage from the remaining other input terminals to invert the comparison / determination means. To do.

The present invention also provides a semiconductor device provided with each means for implementing the above driving method.

According to the present invention, the input terminal of the comparison / determination means is preliminarily shifted from the midpoint level by an arbitrary potential amount, and thereafter, the comparison / determination means causes an inverting operation, so that the input / output terminal of the comparison / determination means is shifted from another input terminal. It is possible to easily and arbitrarily change the amount of voltage to be applied with a small number of elements.

Further, in the present invention, it is conceivable that the comparing and judging means first causes the inversion operation due to the influence of the previously shifted potential amount, but the effect of the present invention is lost even if such a situation occurs. is not. That is, after that, if a certain voltage is applied from another input terminal and the comparison / determination means causes the inverting operation again, the effect of the present invention is obtained.

Further, since the shift amount to be shifted in advance can be arbitrarily set by the ratio of a plurality of capacitance means, it can be easily realized without requiring special control by an external signal.

[0012]

【Example】

[First Embodiment] FIG. 1 is a circuit diagram showing a first embodiment of the present invention. 1, n is a signal input terminal, 200 is a control terminal for shifting the potential Vfg of the input terminal of the inverter amplifier to a desired level, and C1, C2, C3, ... Cn, Cd are The capacitor 10 is an input terminal of the inverter amplifier, 100 is an output terminal of the inverter amplifier, M1 is a switch provided between the output terminal and the input terminal of the inverter amplifier, and 20 is a control terminal of the switch.

FIG. 3 is a timing diagram for explaining the operation of the present invention. Hereinafter, a detailed description will be given with reference to these drawings.

First, during the clamp reset period Tcp, the signal Vcp is at a high level and the switch M1 is turned on, so that the potential of the input terminal of the inverter amplifier is clamped at the midpoint level Vinv of the transfer characteristic of the inverter. At this time, all the signal input terminals 1, 2, 3, ... N are set to the low level and the control terminal 200 is set to the high level.

After that, the signal Vcp is set to the low level, the switch M1 is turned off to put the input terminal of the inverter amplifier in the floating state, and then the control terminal 200 is set to the low level. Then, the potential Vfg of the input terminal of the inverter amplifier in the floating state is shifted from the midpoint level Vinv by ΔV through the capacitance Cd.

Now, the difference potential between the low level and the high level is V
Assuming H, ΔV is ΔV = VH * Cd / {C1 + C2 + C3 + ... + Cn + Cd} (2) Therefore, if the ratio of the sizes of the capacitances C1, C2, C3, ... Cn and the capacitance Cd is arbitrarily set, the midpoint level Vin
The shift amount from v can be set to an arbitrary value. For example, C
If 1 = (C2) / 2 = (C3) / 4 = ... Cn / 2 ^(n-1) and Cd = C1 / 2, then when n = 8 and VH = 5V, ΔV becomes about 10 mV, It can be seen that the shift amount from the midpoint level Vinv can be controlled at a very small level.

As described above, the control terminal 200 shifts the potential Vfg of the input terminal of the inverter amplifier in a floating state to a desired level, and then the active period Tac.
At t, each signal voltage is applied from the signal input terminals 1, 2, 3, ... N. Each signal input terminal 1, 2, 3, ... N
Where V1, V2, V3, ... (3) Note that here, the formula (2) and C1 + C2 + C3
Considering that + ... + Cn >> Cd. As can be seen from the equation (3), the potential Vfg of the input terminal of the inverter amplifier rises due to the application of each signal voltage, but unless the amount of rise exceeds the initially set shift amount ΔV, the inverter amplifier performs the inverting operation. Do not wake up.

After that, the inverter amplifier is inverted only when each signal voltage rises and the amount of increase exceeds the shift amount ΔV. As described above, in the present embodiment, when the minute voltage is detected and the comparison determination is executed, the operation of inverting the inverter amplifier only after the potential change from the midpoint level to an arbitrary potential level or more occurs as described above. realizable.

In this embodiment, an inverter amplifier is used as the comparison / determination means, but the invention is not limited to this as long as it has a function equivalent to this. For example, a general operation input It may be a type amplifier or the like.

Needless to say, each signal input terminal requires a switch means for timely switching between setting to a low level and inputting a signal voltage.

In order to realize the above-mentioned series of driving, for example, a signal for switching the signal input terminal to the switch means, a control signal for the switch means provided in the inverter amplifier, and an input for the inverter amplifier. It goes without saying that a control circuit means in which logic is formed so as to generate a control signal for shifting the terminal potential in a timely manner is necessary. As such control circuit means, for example, one using a delay element or , A combination of logic elements, a clock control logic element, and the like can be implemented.

[Second Embodiment] FIG. 4 is a circuit diagram showing a second embodiment of the present invention. In FIG. 4, 1, 2,
3, ... N are signal input terminals, 200 is a control terminal for shifting the potential Vfg of the input terminal of the inverter amplifier to a desired level, C1, C2, C3, ... Cn, Cd are capacitors, and 10 is an inverter amplifier input terminal. , 100 is an output terminal of the inverter amplifier, M1 is a switch provided between the output terminal and the input terminal of the inverter amplifier, and 20 is a control terminal of the switch.

In this embodiment, an ON / OFF signal for controlling a switch provided between the output terminal and the input terminal of the inverter amplifier is used as a control signal for shifting the potential Vfg of the input terminal of the inverter amplifier to a desired level. Alternatively, it is characterized by using an inverted signal thereof. In the present embodiment, it is not necessary to provide a special control signal for shifting the potential Vfg of the input terminal of the inverter amplifier to a desired level as in the first embodiment, and therefore, the desired function can be achieved with a simpler configuration. Can be realized.

If it is desired to delay the timing of shifting the potential Vfg of the input terminal of the inverter amplifier to a desired level with respect to the timing of turning off the switch provided between the output terminal and the input terminal of the inverter amplifier. This can be handled by properly inserting a delay element or the like.

The operation of this embodiment is basically the first.
This is the same as that of the embodiment.

[Third Embodiment] FIG. 5 is a circuit diagram showing a third embodiment of the present invention. An eight-bit multi-step type A / D converter is constructed by using eight circuits of the above embodiment. The analog signal Vin is input to each of the eight circuits via an analog switch. 1 for each digit
Correspond to the above circuit, the most significant bit (MSB)
Then, 1/2 level determination is performed, and then determination is performed at each level as 1/4, 1/8, 1/16, ... The result determined by the upper bits is
It is sequentially fed back as an input signal to the lower digit, and for the lower bit, the level judgment is performed based on the analog signal Vin and the signal from the upper digit.

Before describing the overall operation of the A / D converter according to the present invention, first, the circuit provided for each digit will be described.

FIG. 6 shows that 0 to 7 digits of 8-bit A / D
It shows in detail the internal configuration of the fourth digit circuit.
The analog signal Vin is input to one of the plurality of input terminals, and the higher-order output signal Dn + 1 is input to the remaining input terminals.
The inverted signal of is input. Further, a switch M1 is provided between the output terminal and the input terminal of the first stage inverter amplifier.

Further, the control signal Vc for shifting the potential Vfg of the input terminal of the first stage inverter amplifier to a desired level is inputted with the signal Vcp for controlling the switch. In addition, a switch and an inverter for timely transmitting signals to lower bits are provided.
Each capacitance (Cin, C1, C2, connected to each input terminal
... Cd) has N as the number of A / D bits and n as the digit number.
(N is 0 to N-1, 0 is LSB, N-1 is MSB),
Letting the number of the capacity be j (j is 1 to N−n−1), the following relationships are established.

Cj = Cin / 2 ^(Nnj) Cd = Cin / 2 ^(Nn) (4) FIG. 7 shows the operation timing of the circuit shown in FIG. 6 and the potential change of each part. The operation of this circuit will be described with reference to this figure.

First, during the clamp reset period Tcp, the signal Vcp is at a high level and the switch M1 is turned on, so that the potential of the input terminal of the first-stage inverter amplifier is clamped at the midpoint level Vin of the transfer characteristic of the inverter. At this time, the analog signal input terminal is set to the low level, and all the signal input terminals are set to the high level via the transmission inverter and the control terminal Vc is also set to the high level.

After that, when the signal Vcp is set to low level and the switch M1 is turned off to put the input terminal of the inverter amplifier in a floating state, the potential V of the input terminal of the first stage inverter amplifier is set.
fg is the middle point level Vin by ΔV through the capacitance Cd.
shifted from v.

Now, the difference potential between the low level and the high level is V
When H is set, ΔVn at the n-th digit is ΔVn = VH * Cd / {ΣCj + Cin + Cd} (5) From equations (4) and (5), for example, LSB (n =
ΔV at 0) is VH / 511, and if VH is 5V, it is about 10 mV. Also, ΔV at n = 1 is VH
/ 255, ΔV at n = 2 becomes VH / 127, and the other values can be calculated in the same manner.

As described above, after the potential Vfg of the input terminal of the first stage inverter amplifier in the floating state is shifted to a desired level via the control terminal Vc and the capacitor Cd, it is applied to the analog signal input terminal in the active period Tact. The analog signal Vin is input like a ramp, and the inverted signal of the output signal Dn + 1 from the upper bit is input to the signal input terminal of the circuit of each digit through the transmission inverter. By the way, the output signals of each digit at the first stage are all low level.

Next, in the initial stage when an analog signal is input, for example, the potential Vfg generated at the input terminal of the first-stage inverter amplifier at LSB is: Vfg = Vinv-ΔV + {VinCin} / {ΣCj + Cin + Cd} (6) Become. As can be seen from the equation (6), in the LSB, the potential Vfg of the input terminal of the first-stage inverter amplifier gradually increases after the analog ramp signal voltage is input, and the increase amount is first shifted as described above. Potential amount ΔV (1
Only when the voltage exceeds 0 mV) does the first-stage inverter amplifier invert. As a result, the output signal of the LSB changes to high level. When the analog signal Vin further rises, the same thing as that just described occurs at the bit of n = 1. However, in the bit of n = 1, the amount of potential increase until the inversion operation of the first-stage inverter amplifier is 20 mV (5 V / 255), which is twice the amount in LSB.

Next, based on the above description, the operation of the entire multi-step type A / D converter according to the present invention will be further described. As described above, the clamp reset period Tcp
And the potential Vfgn of the input terminal of the initial inverter amplifier of each digit is set to a predetermined level, and then the analog signal Vin is applied so that the potential rises at a constant slope as shown in FIG. The potential Vfgn of the input terminal of the first-stage inverter amplifier of the digit also rises like a ramp through the capacitor Cin. At this time, the ratio of the amount of change in the potential Vfgn to the amount of change in the analog signal Vin is set to the voltage gain G.
Gn is given by the following equation.

Gn = Cin / {Cin + ΣCj + Cd} (7) From equation (7), when the total capacitance of the input terminals of the first-stage inverter amplifier of each digit is set to the same value, the gain Gn of each digit is equal. Become. Therefore, as shown in the drawing, the potential Vfgn of the input terminal of the first-stage inverter amplifier of each digit rises with the same inclination with respect to the change of the analog signal Vin.

With respect to the rise of the analog signal Vin, first, the potential Vf of the first-stage inverter amplifier of the least significant digit (LSB).
When g0 rises by 10 mV and reaches the midpoint level Vinv, the LSB first-stage inverter amplifier is inverted. As a result, the output terminal D0 of the LSB becomes high as shown in the figure.

After that, when the analog signal Vin continues to rise further, the potential Vfg1 of the input terminal of the first-stage inverter amplifier of the next higher digit further rises by 10 mV, and when the potential reaches the midpoint level Vinv, it is inverted. .
As a result, the output terminal D1 of the first digit becomes high as shown in the figure.

When the output terminal D1 of the first digit becomes high, its inverted signal is fed back to the lower digit (LSB). At this time, the voltage amount at which the potential Vfg0 of the input terminal of the initial inverter amplifier of LSB is swung by the feedback voltage from the nth digit through the capacitor Cn is expressed by the following equation.

Dvn = VH * Cn / {Cin + ΣCj + Cd} (8) From equations (4) and (8), for example, the voltage amount dv1 swung by the feedback voltage from the first digit is VH / 25.
5 and becomes about -20 mV when VH is 5V. In this manner, the feedback voltage from the first digit causes the potential Vfg of the input terminal of the LSB first stage inverter amplifier.
When 0 is swung to the minus side and returned to the above-mentioned initially set level (Vinv-10 mV), the potential Vfg0 of the input terminal of the first-stage inverter amplifier becomes smaller than the midpoint level Vinv again as shown in the figure. , The first-stage inverter amplifier of LSB is inverted again, and as a result, the output terminal D0 of LSB becomes low. After that, further analog signal V
When in continues to rise, as shown in the figure, the inverter amplifier of the higher digit inverts and the inverted signal is fed back to the lower digit in exactly the same mechanism as described above. As a result, the output terminals of each digit are sequentially set to desired values, and finally the 8-bit A /
D conversion is completed.

As described above, in the A / D converter according to the present invention, each digit has a plurality of input terminals, and the input terminals are commonly connected via the capacitance means, and the common connection terminals are connected to the inverter amplifier. By using a functional circuit such that the input terminal is connected and the potential of the input terminal of the inverter amplifier can be accurately set to an arbitrary potential level, the D step required for the multi-step A / D conversion can be achieved. /
The three basic processes of A conversion, analog subtraction, and compare are realized extremely efficiently (with a small number of elements and low power consumption) with only a single circuit.

[0043]

As described in the above embodiments, according to the present invention, a plurality of input terminals are provided, and each of the input terminals is commonly connected via a capacitance means, and the inverter amplifier is connected to the common connection terminal. In the semiconductor device in which the input terminal of is connected and the switch is provided between the output terminal and the input terminal of the inverter amplifier, after turning on the switch and setting the input terminal and the output terminal of the inverter amplifier to the same potential After turning off the switch to put the input terminal of the inverter amplifier in a floating state, a voltage is applied from at least one input terminal of the plurality of input terminals, After the potential is shifted to the desired level, the signal voltage is applied from the remaining input terminals to detect the minute voltage. When performing the comparison judgment, it is possible to economically realize the function of inverting the inverter amplifier only when a potential change of an arbitrary potential level or more occurs at the input terminal of the inverter amplifier with an extremely small number of elements. To be

That is, it is possible to obtain an effect that the input voltage amount required to cause the inversion operation in the comparison and determination means can be easily set to an arbitrary value.

Further, even when a multi-step type A / D converter is manufactured by using this function, an effect that can be economically realized with an extremely small number of elements can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional example.

3 is an operation timing chart for explaining a driving method of the embodiment of FIG.

FIG. 4 is a circuit diagram showing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing an A / D converter according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing the internal configuration of each circuit of the third embodiment of the present invention.

7 is an operation timing chart of the embodiment of FIG.

FIG. 8 is an operation timing chart of the embodiment shown in FIGS. 5 and 6;

[Explanation of symbols]

1, 2, 3, ... n signal input terminal, 10 input terminal of inverter amplifier, 20 control terminal of the switch, 30 inverter amplifier (comparative judgment means) 100 output terminal of inverter amplifier, 200 potential Vfg of input terminal of inverter amplifier , A switch provided between the output terminal and the input terminal of the M1 inverter amplifier, C1, C2, C3, ... Cn, Cd capacitors,

Claims (8)

[Claims] 1. A plurality of input terminals, said input terminals are commonly connected via respective capacitance means, said common connection terminal is connected to an input terminal of comparison determination means, and an output terminal of said comparison determination means. In the method for driving a semiconductor device, wherein switch means is provided between the input terminal and the input terminal, the switch means is turned on and the input terminal and the output terminal of the comparison determination means are set to the same potential, and then the switch means is turned off. The input terminal of the comparison / determination means is in a floating state, and a voltage is applied from at least one or more input terminals of the plurality of input terminals to set the potential of the input terminal of the comparison / determination means in the floating state to a midpoint. After shifting from a level to a desired level, a voltage is applied from the remaining other input terminals to invert the comparison / determination means to drive the semiconductor device. 2. When setting the input terminal and the output terminal of the comparison and determination means to the same potential, the high level of at least one or more input terminals of the plurality of input terminals is applied and the comparison and determination is performed. 2. The method for driving a semiconductor device according to claim 1, wherein a low level is applied to the input terminal after the input terminal of the means is brought into a floating state. 3. At least one of the plurality of input terminals
2. The method of driving a semiconductor device according to claim 1, wherein a signal for turning on / off the switch means or an inverted signal thereof is applied to one or more input terminals. 4. The method for driving a semiconductor device according to claim 1, wherein the shift amount is controlled arbitrarily by arbitrarily setting the ratio of the sizes of the respective capacitance means. 5. A plurality of input terminals, said input terminals are commonly connected via respective capacitance means, said common connection terminal is connected to an input terminal of comparison determination means, and an output terminal of said comparison determination means. In a semiconductor device in which a switch means is provided between an input terminal and an input terminal, the switch means is turned on to set the input terminal and the output terminal of the comparison determination means to the same potential, and then the switch means is turned off to perform the comparison determination. A means for bringing the input terminal of the means into a floating state; and applying a voltage from at least one or more input terminals of the plurality of input terminals to set the potential of the input terminal of the comparison and determination means in the floating state to the midpoint level. To a desired level, and a means for applying a voltage from the remaining other input terminal to invert the comparison / determination means. apparatus. 6. When setting the input terminal and the output terminal of the comparison / determination means to the same potential, the high level of at least one or more input terminals among the plurality of input terminals is applied, and the comparison / determination is performed. 6. The semiconductor device according to claim 5, further comprising means for applying a low level to the input terminal after the input terminal of the means is brought into a floating state. 7. At least one of the plurality of input terminals
6. The semiconductor device according to claim 5, further comprising means for applying a signal for turning on / off the switch means or an inverted signal thereof to one or more input terminals. 8. The semiconductor device according to claim 5, wherein the shift amount is arbitrarily controlled by arbitrarily setting the ratio of the sizes of the respective capacitance means.