JPH08203296A - Semiconductor storage device - Google Patents

Abstract

PURPOSE: To obtain a semiconductor storage device enabling external electrical discrimination of the existence or nonexistence of a redundant memory being used and the address of a failure bit. CONSTITUTION: When an address signal coincides with a failure address in a fail address memory 120, and a selection signal is outputted from an address comparing circuit 118 to a spare decoder 116 in the process of a redundant circuit test mode wherein a test mode signal te is outputted from a timing generation circuit 122, an output of an NAND circuit 132 turns to be at an 'L' level and a stepping-down operation of a voltage step-down circuit 126 stops. Only in the case where the failure address is accessed, accordingly, an operation is executed with an external voltage and the access time and others are changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of relieving defects generated during manufacturing.

[0002]

2. Description of the Related Art In a semiconductor memory device such as a dynamic random access memory (hereinafter referred to as DRAM), as the capacity of a memory cell array increases,
The chip area also increases, and there is a problem that the manufacturing yield is reduced due to a defective bit or a word line defect such as disconnection or short circuit of the word line.

Therefore, in addition to the regular memory cells, spare memory cells (hereinafter referred to as redundant bits) are formed in advance in the chip, and columns or rows having defective bits or word line defects in the memory cell array are formed. Is generally replaced with a spare memory column or memory row to provide a redundant circuit for relieving a defective bit or word line defect to improve the yield.

By the way, in memory failure analysis and the like, it is possible to know whether or not a redundant bit is used and the address of the repaired defective bit without resorting to inefficient means such as disassembly inspection even at the product stage. It would be convenient if possible.

In order to meet such a demand, a nonvolatile memory element indicating whether or not a redundant memory cell has been used for replacing a defective memory cell is provided in the memory, and the state of this nonvolatile memory element is read out. Has proposed a technique for knowing whether or not this memory uses redundant bits.

As a first conventional example, the above technique is disclosed, for example, in US Pat. No. 4,480,199.

FIG. 9 is a circuit for detecting the use of the redundant bit.
Shows DT. The circuit DT has a power supply voltage V_CCAnd internal circuit CB
As a fixed memory element between the external terminal EXT connected to
MOS transistor which is diode-connected to the fuse F of
Q _T1, Q_T2It is configured to include and in series.

The fuse F is blown if the redundant memory cell is used for the functional replacement of the defective memory cell of the normal memory cell array, and otherwise the fuse F.
Is not cut. The fuse is blown after the memory is tested.

In normal operation, the voltage at the external terminal EXT is
It is within the range of the potential V _CC and the ground potential, the transistors Q _T1 and Q _T2 are turned off, and the fuse F is connected to the external terminal EXT.
Electrically separated from. Therefore, the fuse F does not affect the normal operation at all.

When checking whether or not the memory uses redundant memory cells, the power supply potential V is applied to the external terminal EXT.
By applying a voltage that is higher than _CC by the sum of the threshold values of the transistors Q _T1 and Q _T2 ,
_{With T1} and Q _T2 turned on, the blown / non-broken state of the fuse F can be determined by the presence / absence of a current from the terminal EXT to the terminal V _CC .

However, in this method, it is necessary to apply a high voltage higher than the normal power supply voltage at the time of testing, the operation is complicated, and it is not possible to know the address replaced with the redundant bit.

[0012] Therefore, the second problem to solve the above problems
A conventional example of the above is disclosed in JP-A-60-151899.

FIG. 10 is a schematic block diagram showing the configuration of the second conventional example. The configuration and the data read operation will be briefly described below.

In FIG. 10, row address buffer 1
a, the column address buffer 1b receives the address signals A _xi , A _yi supplied from the outside by the multiplex method, and receives the internal complementary address signals a _xi , / a _xi and a _yi , /
a _yi are formed respectively.

The row address decoder 2a and the column address decoder 2b receive the internal complementary address signal and form a word line selection signal and a data line selection signal, respectively.

The word line selection signal is supplied to the word line driver 5 to select and drive the word line driver corresponding to the address A _xi . Further, the data line selection signal is supplied to the column switch 7 provided for each data line in the memory array 6.

The data of one data line corresponding to the address A _yi is amplified by the sense amplifier 8 through the column switch 7 which is turned on by the selection signal output from the column address decoder 2b, and is output to the output buffer 10.
Is output to the input / output terminal 11.

On the other hand, a spare memory row 6s is provided on one side of the memory array 6.

The address comparison circuit 3 is provided with a defective address storage means (not shown) capable of storing an address of a defective word line having a defect such as a defective bit or a disconnection therein by a program element such as a fuse, and externally. The input address signal is compared with the defective address stored inside to detect whether the input address matches the defective address.

When the input address matches the defective address, a signal φ _xij for operating the redundant decoder 4 is formed and supplied to the redundant decoder 4, and the redundant decoder 4 outputs a decoder inhibit signal. / Φ
_e is formed and supplied to the row address decoder 2a. On the other hand, by the redundant decoder 4, the redundancy selection signal phi _r of "H" level, such as to select a spare memory row is formed, it is supplied to the redundant word driver 5s. As a result, the redundant word driver 5s is driven and the word line of the spare memory row 6s is set to the selection level.

Further, in accordance with the decoder inhibit signal / φ _e output from the redundant decoder 4, the row address decoder 2
All the operations of a are prohibited, the word line driver 5 is deselected, and the regular word line in the memory array 6 is not set to the selected level.

On the other hand, if the input address does not match the defective address, the redundancy decoder 4 does not output the high level redundancy selection signal φ _r, but instead outputs the decoder enable signal φ _e . The enable signal φ _e is supplied to the row address decoder 2a, the decoder 2a is operated, the word line driver 5 corresponding to the input address A _xi is driven, and the regular word line in the memory array 6 is set to the selection level. It has become so.

Further, in the second conventional example, the internal circuit is controlled based on the control signals such as the chip select signal / CS, the row address strobe signal / RAS, and the column address strobe signal / CAS supplied from the outside. An internal signal generating circuit 13 is provided for forming the signals φ _x , φ _y , and φ _ma to be generated. Further, a control terminal 1 to which a control signal such as a chip select signal CS is input
When the level of the signal applied to 4 is higher than the "H" level (+ 5V) in the normal memory operation, for example, this is detected and a predetermined internal signal φ _c is detected.
A special condition determination circuit 15 that outputs is provided.

The internal signal φ _c is supplied to the redundant decoder 4
It is input to the AND gate circuit 16 together with the redundancy selection signal φ _r output from. A switch MOSFET 18 is connected between the control terminal 17 other than the control terminal 14 to which the special condition determination circuit 15 is connected and the ground point of the circuit.
18 is turned on / off by an output signal of the AND gate circuit 16.

Therefore, with a voltage higher than usual applied to the control terminal 14 such as a chip select terminal to which the / CS signal is applied, the address A
While changing _x one after another, all the word lines are scanned and the control terminal 17 connected to the MOSFET 18 is monitored.

At this time, when the defective address is accessed, the output level of the AND gate circuit 16 is set to the "H" level and the MOSFET 18 is turned on. as a result,
Since a leak current flows through the control terminal 17, the relief address (defective address) can be known by detecting this with an external device.

[0027]

Since the conventional semiconductor memory device capable of judging the usage state of the redundant memory has the above-mentioned structure, it has the following problems.

That is, in the first conventional example, the first
It is necessary to apply a voltage higher than the power supply voltage normally used in the test mode, and secondly, it is impossible to know the address where the defective bit exists.

Furthermore, in the second conventional example, although the above-mentioned second problem is taken as a countermeasure, in the tests at the product stage in both the first and second conventional examples, the external terminal 1 of the package is It is necessary to use one for determining whether the redundant bit is used or not.

In the DRAM and the like, the number of external terminals is limited to a fixed number according to the product standard. On the other hand, as the memory capacity increases, the number of external terminals to be used for address signal input and data input / output increases, and there is virtually no empty external terminal. For this reason, the external terminals used for other signals have to be diverted to determine whether the redundant bits are used. Therefore, at the time of judgment, a special voltage higher than the power supply voltage is required, and the special voltage damages the internal circuit element connected to this external terminal or causes an abnormal current, which reduces the reliability of the memory. It had a problem of causing it.

The present invention has been made to solve the above problems and has the following objects.

That is, it is possible to provide a semiconductor memory device in which it is not necessary to divert an external terminal used for another purpose at the time of determining a redundant bit, and thus it is not necessary to apply a special voltage higher than a power supply voltage during a test. That is.

Another object of the present invention is to provide a semiconductor memory device having a function of externally electrically determining an address where a defective bit exists.

[0034]

According to another aspect of the semiconductor memory device of the present invention, there is provided an address comparing means for comparing an input address with a defective address to which a defective memory cell belongs, and when the input address and the defective address match. A redundant memory selection signal generating means for generating a signal for selecting a spare memory cell column or a row, and an internal step-down circuit for stepping down an external power supply voltage to supply the internal power supply voltage are provided. In the redundant circuit test mode that includes the input terminal of the step-down circuit control signal that switches between the step-down operation stop state and the external signal, the step-down circuit is switched to the step-down operation state when the redundant memory is not selected in response to the redundant memory selection signal. , Step-down circuit control that inputs the step-down circuit control signal to the step-down circuit control signal input terminal to stop the step-down circuit when the redundant memory is selected Further comprising a No. generating means.

According to another aspect of the semiconductor memory device of the present invention, there is provided redundancy function memory means for storing the presence or absence of a defective address in a non-volatile manner, address comparing means for comparing an input address with a defective address to which a defective memory cell belongs, and an input address. And a defective address match, a redundant memory selecting means for selecting a spare memory cell column or row and an internal voltage down circuit for stepping down the external power supply voltage to supply the internal power supply voltage are provided. In the redundant circuit test mode including the input terminal of the step-down circuit control signal for switching between the step-down operation state and the step-down operation stop state, and the redundancy circuit test mode set by the external signal,
A step-down circuit control signal is input to the step-down circuit control signal input terminal to set the step-down circuit to the step-down operation state when the redundant memory is not used and to set the step-down circuit to the step-down operation stop state when the redundant memory is used, according to the storage of the redundant function storage means. It further comprises a step-down circuit control signal generating means.

According to a third aspect of the present invention, in addition to the configuration of the semiconductor memory device according to the second aspect, the semiconductor memory device further comprises means for generating a redundant circuit test mode designating signal in response to an external signal, and the redundant function memory means comprises: A first potential input end corresponding to the first logic level, a second potential input end corresponding to the second logic level, a first potential input end and a second potential input end A step-down circuit control signal generating means, the step-down circuit control signal generating means includes a first input terminal for inputting a redundant circuit test mode designating signal, and the resistor and non-volatile switching means. When the non-volatile switch means and the second input terminal connected to the connection point are disconnected, the signal for stopping the step-down operation in the redundant circuit test mode is changed to the step-down operation state except in the redundant circuit test mode. Do Outputs No., if the conductive state nonvolatile switching means, regardless of the redundancy circuit test mode signal, and an output terminal for outputting a signal to the step-down operation.

[0037]

According to the semiconductor memory device of the present invention, in the redundant circuit test mode, when the redundant memory is selected according to the input address, the internal step-down circuit stops the step-down operation according to the redundant memory selection signal. , Supply the external voltage as it is.

According to another aspect of the semiconductor memory device of the present invention, in the redundant circuit test mode, if a defective bit exists and the redundant memory is used, it is stored in advance in the nonvolatile redundant function storage means. The internal voltage down circuit stops the voltage down operation and supplies the external voltage as it is according to the information.

According to another aspect of the semiconductor memory device of the present invention, the non-volatile redundancy function storage means in the semiconductor memory device of the second aspect is connected in series between the first potential and the second potential. It consists of a resistor and a non-volatile switch means. The electric potential at the connection point between the resistor and the switch means holds the first electric potential or the second electric potential depending on the open / close state of the switch means.

[0040]

1 is a schematic block diagram showing the structure of a semiconductor memory device according to a first embodiment of the present invention.

Timing generation circuit 122 performs a redundancy circuit test with a specific combination of row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE, for example, WCBR (/ WE, / CAS before / RAS). Signal t _e to enter mode
Is output. Here, WCBR means that the / RAS signal cannot be in a normal operation state from "H" level to "L".
A combination of signals in which the / WE signal and the / CAS signal fall from the "H" level to the "L" level at the timing before falling to the level.

Row and column address buffer 112
The address signals A0, A1, ..., in accordance with the A _n, the address comparing circuit 118, and outputs an internal address signal to the row decoder 106 and column decoder 104.

The address comparison circuit 118 compares this internal address signal with a defective address stored in advance in the fail address memory 120 by a fuse element or the like. If they match, the address comparison circuit 118 outputs the selection prohibition signal to the row decoder 106 and the selection signal to the spare decoder 116. The bit data of the memory cell in the spare memory array 114 selected by the signal from the column decoder 104 is amplified by the sense amplifier 108, output to the output buffer 130, and finally output to the data input / output terminal.

The write operation is basically the reverse operation to the above. Here, the redundant circuit test mode signal and the spare decoder selection signal are input to the NAND circuit 132. Only when the redundant circuit test mode is entered and the redundant memory is selected, both signals become "H" level and NA
The output signal of the ND circuit 132 becomes "L" level. NA
The output signal of the ND circuit 132 is input to the voltage down converter 126. When this signal is at "L" level, the step-down circuit stops the step-down operation, and external voltage ext. Output V _CC as it is.

FIG. 2 is a block diagram of NAND circuit 132 and voltage down converter 126 in FIG.

The signal t _e is a control signal for the redundant circuit test mode for determining the redundant cell use. The signal B is an address decode signal of the redundant cell. Signal C is a control signal for the internal voltage down converter.

FIG. 3 is a timing chart showing the operation of the present invention. Next, the operation will be described. The redundant circuit test mode for determining the redundant cell use is, for example, the above-mentioned W.
It is entered by CBR and released by CBR or / RAS only refresh. When the redundant circuit test mode is entered, the control signal t _e changes from "L" level to "H" level. The signal t _e maintains the “H” level during the redundant circuit test mode, and changes from the “H” level to the “L” level when the special test mode is released. Also, during normal operation and standby, "L"
It remains at the level.

The address decode signal B of the redundant cell changes from the "L" level to the "H" level by setting / RAS when the redundant cell is used, and changes from the "H" level to the "L" level by resetting the / RAS signal. Become. When the redundant memory is not selected, this signal B remains at "L" level and does not change.

Next, the signal C is an internal step-down circuit control signal,
When this signal is at "H" level, the internal step-down circuit operates, and when it is at "L" level, the internal step-down circuit does not operate. As is apparent from FIG. 2, when both the signals t _e and B are at “H” level, the signal C goes to “L” level,
When either one or both of the signals t _e and B are at “L” level, the signal C goes to “H” level. That is, in the redundant circuit test mode, the step-down operation of the internal step-down circuit is stopped during the redundant circuit test mode only when the redundant memory is selected.

During operation of the internal step-down circuit, (external voltage ex
t. V _CC )> (internal voltage int.V _CC ), and when the internal step-down circuit is stopped, (external voltage ext.V _CC ) = (internal voltage int.V _CC ).

Therefore, while the redundant memory cell is selected during the redundant circuit test mode, the external power supply voltage is used instead of the stepped down power supply voltage, so that the power supply current can be measured or By measuring the access time, it is possible to determine whether the redundant memory is selected according to the input address at that time.

FIG. 4 is a schematic block diagram showing the configuration of the second embodiment of the present invention. The basic configuration is similar to that of the first embodiment.

The difference is that it is the logic circuit 136 that generates the control signal of the internal voltage down converter 126, and the input signal to the logic circuit 136 is the redundancy circuit test mode signal t.
_e and the output signal of the nonvolatile memory circuit 134.

The information stored in the nonvolatile memory circuit 134 is set at the same time when the defective address information is set in the fail address memory 120.

FIG. 5 shows the nonvolatile memory circuit 134 shown in FIG.
3 is a block diagram of a logic circuit 136. FIG. In FIG. 5, a high resistance resistance element 140 and a laser trimming fuse element 142 are connected in series. NAN
One input end of the D circuit 144 is connected to the connection point of the high resistance element 140 and the fuse element 142. N
The redundant circuit test mode signal t _e is input to the other input terminal of the AND circuit 144 as in the first embodiment.

FIG. 6 is a timing chart showing the operation of the second embodiment. Next, the operation will be described. First of all, when the redundant memory is used, the fuse element in the fail address memory 120 for switching to the redundant memory by laser trimming is cut, but the fuse element 142 of FIG. 5 is also cut at that time. The fuse element 142 is not cut when the redundant memory is not used.

As shown in FIG. 6, when the redundant memory is not used, the high resistance element 140 causes the signal B to be at "L" level and the signal C to remain at "H" level regardless of the signal t _e. The step-down circuit operates.

Next, when the redundant memory is used, the fuse element 142 is blown, so that the signal B becomes "H" level. Therefore, when the control signal t _e changes from the “L” level to the “H” level by the redundant circuit test mode entry, the signal C changes from the “H” level to the “L” level, and the internal step-down circuit Will stop. When the signal t _e changes from the “H” level to the “L” level in the redundancy circuit test mode release, the signal C changes from the “L” level to the “H” level and the internal step-down circuit operates again. Become.

Therefore, when the redundant memory is used, the internal step-down circuit stops operating during the redundant circuit test mode and operates at the external voltage, so that the access time and current consumption change and the redundant memory Whether or not it is used can be electrically determined.

FIG. 7 shows a third embodiment which is a modification of the second embodiment of the present invention. In FIG. 7, a fuse element 142 for laser trimming and a resistance element 140 having a high resistance value
Are connected in series. One input terminal of the NAND circuit 144 is connected to the fuse element 14 via the inverter 146.
2 and the connection point of the high resistance element 140. N
The redundancy circuit test mode signal t _e is input to the other input terminal of the AND circuit 144 as in the first embodiment.

FIG. 8 is a timing chart showing the operation of the third embodiment. Next, the operation will be described. Like the second embodiment, the fuse element 142 is cut only when the redundant memory is used. As shown in FIG. 8, when the redundant memory is not used, the high resistance element 140 causes the signal B to be at "L" level and the signal C to be at "H" level to operate the internal step-down circuit (in this case, the signal t _e). Does not depend on.).

Next, since the fuse element 142 is cut off when the redundant memory is used, the signal B becomes "H" level. Therefore, when the signal t _e becomes "H" level by the redundant circuit test mode entry, the signal C becomes "L" level. Further, when the redundant circuit test mode is released, the signal t _e becomes “L” level, so that the signal C returns to “H” level.

Therefore, similar to the second embodiment, when the redundant memory is used, the redundant circuit test mode is operated by the external voltage, and the redundancy is caused by the change of the access time and the consumption current. Whether or not the memory is used can be determined.

[0064]

According to the semiconductor memory device of the present invention, when the redundant memory is selected in the redundant circuit test mode, the internal step-down circuit stops operating and operates at the external voltage, so that the defective bit is dealt with. The access time and the current consumption change only at the address to be used. Therefore, not only the address of the defective bit can be electrically determined, but also it is not necessary to apply a voltage other than the specified value to the external terminal.

According to another aspect of the semiconductor memory device of the present invention, when the redundant memory is used, the internal step-down circuit stops operating during the redundant circuit test mode and operates at the external voltage. Current consumption changes.
Therefore, it is possible to electrically determine whether or not the redundant memory is used, and it is not necessary to apply a voltage other than the specified value to the external terminal.

According to another aspect of the semiconductor memory device of the present invention, when the redundant memory is used, the internal voltage reduction is performed during the redundant circuit test mode based on the information previously stored in the nonvolatile redundant function storage means. Since the circuit stops operating and operates with the external voltage, the same effect as that of the second aspect is achieved.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a main part of the first embodiment.

FIG. 3 is a timing chart showing the operation of the first embodiment.

FIG. 4 is a schematic block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram of essential parts of a second embodiment.

FIG. 6 is a timing chart showing the operation of the second embodiment.

FIG. 7 is a block diagram of an essential part of a third embodiment of the present invention.

FIG. 8 is a timing chart showing the operation of the third embodiment.

FIG. 9 is a block diagram of a main part of a first conventional example.

FIG. 10 is a schematic block diagram showing a second conventional example.

[Explanation of symbols]

1a row address buffer, 1b column address buffer, 2a row address decoder, 2b column address decoder, 3 address comparison circuit, 4 redundancy decoder, 5 word line driver, 5s redundancy word driver, 6 memory array, 6s spare memory row, 7 column Switch, 8 sense amplifier, 9 main amplifier, 1
0 output buffer, 11 input / output terminal, 12 input buffer, 13 internal signal forming circuit, 14 control terminal, 15 special condition determination circuit, 16 AND gate circuit, 17 specific pin (control terminal), 18 switch element, 100 semiconductor memory device , 102 memory cell array, 104 column decoder, 106 row decoder,
108 sense amplifier, 110 input / output circuit, 112 row and column address buffer, 114 spare memory array, 116 spare decoder, 118 address comparison circuit, 120 fail address memory, 122 timing generation circuit, 124 reference voltage generation circuit, 126 voltage step-down circuit , 128 input buffer, 130 output buffer, 132 NAND circuit, 134 non-volatile memory circuit,
136 logic circuits, 140 high resistance elements, 142 fuse elements, 144 NAND circuits, 146 inverters.

Claims (3)

[Claims] 1. A semiconductor memory device having a redundant circuit function for electrically replacing a defective memory cell column or row including a defective memory cell with a spare memory cell column or row, wherein an input address and a defective memory cell are provided. An address comparing unit that compares a defective address to which the defective memory belongs to, and a redundant memory selection signal generating unit that generates a signal that selects the spare memory cell column or row when the input address and the defective address match. An internal step-down circuit for stepping down an external power supply voltage to supply an internal power supply voltage, wherein the internal step-down circuit includes an input terminal of a step-down circuit control signal for switching between a step-down operation state and a step-down operation stop state, In the set redundant circuit test mode, the step-down circuit operates in the step-down mode according to the redundant memory selection signal when the redundant memory is not selected. The semiconductor memory device further comprising: a step-down circuit control signal generating means for inputting the step-down circuit control signal to the step-down circuit control signal input terminal for bringing down the step-down circuit when the redundant memory is selected. 2. A semiconductor memory device having a redundant circuit function for electrically replacing a defective memory cell column or row including a defective memory cell with a spare memory cell column or row, wherein presence / absence of a defective address is nonvolatile. Redundant function storage means for memorizing the input address, address comparison means for comparing an input address with a defective address to which a defective memory cell belongs, and when the input address and the defective address match, the spare memory cell column or A redundant memory selecting means for selecting a row and an internal voltage down circuit for stepping down an external power supply voltage and supplying an internal power supply voltage are provided. The internal voltage down circuit switches a voltage down operation state and a voltage down operation stop state. In the redundant circuit test mode including the signal input terminal and set by an external signal, the redundancy function storage means stores a redundancy in accordance with the storage. It further comprises a step-down circuit control signal generating means for inputting the step-down circuit control signal to the step-down circuit control signal input terminal, which sets the step-down circuit to the step-down operation state when the memory is not used and sets the step-down circuit to the step-down operation stop state when the redundant memory is used. , Semiconductor memory device. 3. A means for generating a redundancy circuit test mode designating signal in response to the external signal, wherein the redundancy function storage means includes a first potential input terminal corresponding to a first logic level, and a second potential input terminal. A second potential input terminal corresponding to the logic level of, and a resistor and non-volatile switch means connected in series between the first potential input terminal and the second potential input terminal. The step-down circuit control signal generating means includes a first input terminal to which the redundant circuit test mode designating signal is input, a second input terminal to be connected to a connection point of the resistor and the nonvolatile switch means, When the nonvolatile switch means is in the cutoff state, it outputs a signal for stopping the step-down operation in the redundant circuit test mode and a signal for setting the step-down operation except in the redundant circuit test mode. If pitch means is conductive, regardless of the redundancy circuit test mode signal, and an output terminal for outputting a signal to the step-down operation state, the semiconductor memory device according to claim 2.