JPH08203280A - Semiconductor device - Google Patents

Abstract

PURPOSE: To generate an optimum internal clock in accordance with the frequency of an external clock. CONSTITUTION: An output from a delay circuit is delayed by a delay time of the delay circuit in regard to an external clock CLK. In the case where the frequency of the external clock CLK is small, the delay circuit has already risen to an 'H' level at the time of a fall of the external clock CLK since the time of a pulse width of the external clock CLK is longer than the delay time, and an enable signal becomes to be at 'H' level and 'L' level at that time. Therefore a timing circuit 21 for a low speed operation becomes 'enable' and generates an internal clock CLK1. In the case where the frequency of the external clock CLK is large, the enable signal becomes to be at 'L' level and 'H' level and a timing circuit 22 for a high speed operation generates an internal clock CLK2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which generates an internal clock in synchronization with an external clock, and is particularly used in a synchronous memory circuit.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, some documents were described in the following documents. Literature; IEEE 1991 CUSTOM INTEG
RATED CIRCUIT CONFERENCE,
1991, (US), Shinagawa et al., "A Multi-Speed Digital Cross-Connect Switch"
VLSI UsingNew Circuit Technique in Dual Port RAMs
, "P. 3.4.1 to 3.4.4 Conventionally, a synchronous memory circuit is generally provided with a timing circuit that generates an internal clock such as a sense timing or a write pulse for high-speed operation or low power consumption. It has become. As the synchronous memory circuit, there are a case where R / W of the memory is performed in synchronization with an external clock, and a case where an address change is detected and R / W is performed in synchronization with this. FIG. 2 is a circuit diagram of a conventional synchronous memory circuit described in the above document. As shown in FIG. 2, the timing circuit 1 uses the external clock (system clock) CLK to generate the internal clock S1 in synchronization with the rising or falling of the external clock. The read / write circuit 2 and the decoder 3 operate based on the internal clock S1 to access the memory cell 4. AD _m
Is an address and D _n is data.

[0003]

However, the conventional synchronous memory circuit has the following problems. The internal clock is generated in synchronization with the rising or falling of the external clock, but it is generated regardless of the frequency of the external clock.
It is impossible to change the timing of the internal clock according to the frequency of the external clock. However, some memory circuits are designed for high speed and some are designed for low speed. In order to surely perform R / W on the memory circuit, the high-speed compatible memory circuit and the low-speed compatible memory circuit differ in optimum one in terms of the frequency or pulse width of the internal clock (for example, the power supply voltage V _DD Margin etc.). However, even if the memory circuit designed for high speed operation is operated at low speed, the internal clock timing is the same as during high speed operation. Considering the power supply voltage _VDD margin and the like, both low speed operation and high speed operation are almost the same. It becomes equal, for example, 5V ± 10% at high speed
When it is desired to operate at 1.5 V ± 10% at low speed, the optimum operation timing is required for each, so that it is difficult to realize.

[0004]

In order to solve the above problems, a first invention is directed to a clock frequency judging means for judging the frequency of an external clock, and an internal clock based on the judgment result by the clock frequency judging means. And a timing signal generating means for generating.

[0005]

According to the first aspect of the present invention, since the semiconductor device is configured as described above, the clock frequency determining means determines whether the external clock is high speed or low speed, and the enable signal for high speed and the enable signal for low speed are used. One of the enable signals enables the enable signal. The timing signal generating means generates an internal clock having a timing according to the enable signal based on the enabled enable signal. This internal clock is used, for example, at the timing of generating a read / write control signal in a memory circuit. Therefore, the above problem can be solved.

[0006]

First Embodiment FIG. 1 is a circuit diagram showing a semiconductor memory circuit according to a first embodiment of the present invention. The semiconductor memory circuit of the first embodiment is different from the conventional semiconductor memory circuit in that a clock frequency determination circuit 10 for determining the frequency of an external clock is provided and the low speed operation timing circuit 2 is provided according to the frequency.
First, one of the timing circuits 21 and 22 of the high-speed operation timing circuit 22 is made effective. This semiconductor memory circuit includes a clock frequency determination circuit 10, a low speed operation timing circuit 21, a high speed operation timing circuit 22, a read / write circuit 30, a decoder 40, and a memory cell 50. An external clock CLK is input to the clock frequency determination circuit 10, and an enable signal EN1 is applied to the low speed operation timing circuit 21 and an enable signal EN2 is applied to the high speed operation timing circuit 22. Timing circuit for low speed operation 2
1 or the high-speed timing circuit 22, the low-speed operation internal clock CLK1 or the high-speed operation internal clock CLK when the enable signal EN1 or EN2 is enabled.
2 is generated and given to the read / write circuit 30 and the decoder 40.

The read / write circuit 30 receives the internal clock CLK1 or CLK2 from the low-speed timing circuit 21 or the high-speed timing circuit 22 to read or write the control signal to the memory cell 15, and to write the control signal. Data D _n is given. The decoder 40 includes a low speed timing circuit 21 or a high speed timing circuit 22.
Further, the internal clock CLK1 or CLK2 is input, and the address signal AD _m is input from an address signal line (not shown) to apply the address signal to the word line and bit line of the memory cell 50. The memory cell 50 receives a control signal from the read / write circuit 30 and data at the time of writing, receives an address signal from the decoder 40, and inputs data D _n to the read / write circuit 30 at the time of reading. give.

FIG. 3 is a circuit diagram of the clock frequency determination circuit 10 in FIG. As shown in FIG. 3, the clock frequency determination circuit 10 includes a delay circuit 11, an inverter 12, and an inverter 12.
3 and 3. The delay circuit 11 is composed of an even number of inverters, and has a delay time T corresponding to a pulse width of a threshold value for discriminating between a high speed clock and a low speed clock.
Have 11. This delay circuit 11 uses the external clock CL
K is input and the external clock CLK delayed by the delay time T11 is output. The inverter 12 is the delay circuit 1
1 and inputs the inverted signal to the high-speed operation timing circuit 22 and the inverter 13. Inverter 13
Enables the enable signal E to the timing circuit 21 for low speed operation.
Give N1. 4 and 5 are time charts of the clock frequency determination circuit 10 of FIG. 3, particularly FIG. 4 shows the case where the pulse width of the external clock satisfies the operation specifications, and FIG. 5 shows the pulse width of the external clock. Is a case where the operation specifications are not satisfied. Whether the external clock frequency is low speed or high speed is determined by comparing it with a certain threshold value. Hereinafter, the operation of the clock frequency determination circuit 10 of FIG. 3 will be described with reference to these drawings.

First, referring to FIG. 4, the external clock CL
The operation when the frequency of K is lower than a certain standard will be described. Here, it is assumed that both the high-speed internal clock and the low-speed internal clock are generated in synchronization with the falling edge of the external clock. The output from the delay circuit 11 is delayed by the delay time T11 of the delay circuit 11 with respect to the external clock CLK. The output signal S11 of the delay circuit 11 is inverted by the inverter 12, and the inverted signal is given to the enable signal EN2 of the high speed operation timing circuit 22 and the inverter 13. When the frequency of the external clock CLK is low, the period of the pulse width of the “H” level of the external clock CLK is longer than the delay time T11. Therefore, when the external clock CLK falls, the output S11 of the delay circuit 11 is “H”. Level and enable signal EN1
Becomes "H" level, and the enable signal EN2 becomes
It becomes the "L" level. Thus, when the external clock is low speed, the enable signal EN1 is always at "H" level and the enable signal EN2 is at "L" level when the external clock CLK falls. Therefore, the low-speed operation timing circuit 21 is enabled, an internal clock for low-speed operation (for example, a clock having a relatively long pulse width and a rising delay time not required so much) is generated, and the read / write circuit 30 and the decoder are generated. Output to 40.

Next, referring to FIG. 5, the external clock CL
A case where the frequency of K is faster than a certain standard will be described. When the frequency of the external clock CLK is high, the external clock C
The time of the pulse width of the “H” level of LK is the delay time T11.
Therefore, when the external clock CLK falls, the output S11 of the delay circuit 11 remains at "L" level, the enable signal EN1 becomes "L" level, and the enable signal EN2 becomes "H" level. Therefore, the high-speed operation timing circuit 22 is enabled and generates an internal clock for high-speed operation (for example, a clock having a short pulse width and a short rise delay time) and outputs it to the read / write circuit 30 and the decoder 40. In the read / write circuit 30, the low-speed or high-speed internal clock C
Based on LK1 or CLK2, in the case of a control signal for reading or writing and writing, a data signal is output to the memory cell 50 at a predetermined timing. In the decoder 40, the low-speed or high-speed internal clock CLK1
Alternatively, the address signal AD _m is decoded based on CLK2, and the address signal is applied to the word line and the bit line.

In the memory cell 50, in the case of reading, the writing / reading circuit 3 reads the information of the memory connected to the raised word line from the bit line.
The data D _n is output to 0, and at the time of writing, the data output from the writing / reading circuit 30 is written from the bit line to the memory cell connected to the raised word line. As described above, according to the first embodiment, when the frequency of the external clock CLK is lower than a certain reference, the memory circuit operates with the internal clock for low speed operation. Further, when the frequency of the external clock CLK is higher than a certain reference, the memory circuit operates by the internal clock for high speed operation. Therefore, there is an advantage that an optimum internal clock can be generated according to high speed and low speed, and the range of operating conditions of the memory circuit can be easily widened.
For example, by switching the external clock between high-speed and low-speed, a high-speed compatible memory circuit can operate at 5V ± 10
%, And facilitates the design of a memory circuit whose operation is guaranteed to operate at 1.5 V ± 10% at low speed. Further, there is an advantage that it can be realized without increasing the number of signal lines.

Second Embodiment FIG. 6 is a circuit configuration diagram of a semiconductor memory circuit according to a second embodiment of the present invention. The semiconductor memory circuit of the second embodiment is different from the conventional semiconductor memory circuit in that the frequency of the external clock becomes faster than the specifications of the memory circuit or the duty of the external clock (“H” level and “L”).
The pulse width of the level) is extremely unbalanced and the pulse width of the external clock becomes shorter than the spec of the memory circuit. When the operation specifications are not satisfied, the enable signal EN is set to the “L” level at the falling edge of the external clock so that the internal clock CLK1 is not generated.
This semiconductor memory circuit includes a clock pulse width determination circuit 1
00, timing circuit 120, read / write circuit 130, decoder 140, and memory cell 150. The clock pulse width determination circuit 100 inputs the external clock CLK and gives an enable signal EN to the timing circuit 120. The timing circuit 120 is
External clock CLK and enable signal EN are input to read / write internal clock CLK1.
30 and the decoder 140. The read / write circuit 130 inputs the internal clock CLK1 from the timing circuit 120, and supplies a control signal for reading or writing to the memory cell 150 and data at the time of writing. The decoder 140 receives the internal clock CLK1 from the timing circuit 120 and the address signal AD _m from an address signal line (not shown ₎ to input the memory cell 1
Address signals are applied to 50 word lines and 50 bit lines.
The memory cell 150 receives the control signal from the read / write circuit 130 and the data D _n at the time of writing,
When the address signal is input from the decoder 140 and reading is performed, the data D _n is input to the read / write circuit 130.
give.

FIG. 7 is a circuit diagram of the clock pulse width determination circuit 100 shown in FIG. As shown in FIG. 7, the clock pulse width determination circuit 100 includes a delay circuit 101 and inverters 102 and 103. Delay circuit 101
Has a delay time T101 whose threshold is a period of a pulse width that the external clock CLK should satisfy. Delay circuit 1
01 receives the external clock CLK and inputs the inverter 1
A signal S101 is output to 02. The inverter 102 is
Output to the inverter 103. The inverter 103 outputs the enable signal EN to the timing circuit 120 in FIG. 8A and 8B are time charts of FIG. 7, and in particular, FIG. 8A shows the case where the pulse width of the external clock satisfies the operation specifications of the memory circuit, and FIG. In this case, the duty of the external clock becomes unbalanced, the pulse width of the “H” period of the external clock becomes short, and the specifications are not satisfied. As shown in FIG. 8A, when the pulse width of the external clock CLK satisfies the operation specifications, the pulse width is longer than the delay time T101. Therefore, at the falling edge of the external clock CLK, the output S101 of the delay circuit 101 is output. Becomes "H" level. As a result, the enable signal EN becomes "H" level, the internal clock CLK1 is generated from the timing circuit 120 in synchronization with the falling of the external clock CLK, and the read / write circuit 120 and the decoder 13 are generated.
Output to 0.

Further, as shown in FIG. 8B, when the pulse width of the external clock CLK is shorter than the operation specification,
Since the pulse width thereof is shorter than the delay time T111, the delay circuit 101 is provided at the falling edge of the external clock CLK.
Output S101 of "1" becomes "L" level. As a result, the enable signal EN becomes “L” level, the internal clock CLK1 is not generated at the fall of the external clock CLK from the timing circuit 120, and the memory circuit reads at the fall timing of the external clock CLK. And the writing operation is not performed. When the "H" level pulse width of the external clock CLK is short, the "H" level pulse width of the internal clock generated based on the external clock CLK also becomes short, and when the address signal is unstable, the R / W Cause movement, R / W
Will not be completed and the next address signal will be input, causing a malfunction. Therefore, the external clock C
When the pulse width of the “H” level of LK is short, the memory circuit does not operate and maintains the current state, so that erroneous writing to the memory cell 140 is prevented. As described above, according to the second embodiment, when the frequency of the external clock CLK is faster than the specifications of the memory circuit or the pulse width of the external clock CLK is shorter than the specifications of the memory circuit, erroneous writing, etc. This has the advantage of preventing data corruption in the memory of the.

Third Embodiment FIG. 9 is a circuit diagram of the clock pulse width determination circuit 100 in FIG. 6 showing a third embodiment of the present invention. The clock pulse width determination circuit 100 includes a delay circuit 111, an inverter 112, an S-RNOR type latch circuit (hereinafter, referred to as SR latch circuit) 113, and a D type flip-flop (hereinafter, referred to as DFF) 114. ing. The delay circuit 111 inputs the external clock CLK and outputs SR
The signal S111 is output to the R terminal of the latch circuit 113 and the clock terminal CN of the DFF 114. When the duty of the external clock CLK becomes unbalanced and the pulse width of the “L” level period of the external clock CLK becomes shorter than the specification, the delay time T111 of the delay circuit 111 is immediately after the “H” level of the external clock. In the period of
It is set to output the fall to the “L” level. If the duty of the external clock CLK is normal, the delay time T111 is set so that the fall to the “L” level is output during the “L” level period.
Has been set. The inverter 112 uses the external clock C
LK is input and output to the S terminal of the SR latch circuit 113. The S-R latch circuit 113 outputs DFF from the Q terminal.
The signal S113 is output to the D terminal of 114. DFF11
The enable signal EN is output from the Q terminal of No. 4.

FIG. 10 is a time chart of FIG.
The operation of FIG. 9 will be described below with reference to FIG. First, when the duty of the external clock CLK is normal,
When the delay circuit 111 falls, the external clock C
LK becomes “L” level, and the inverter 112 and SR
By taking the NOR logic of the latch circuit 112, its output S113 becomes "H" level. Thereby, DF
In F114, "H" is generated at the fall of the delay circuit 111.
The level is output, the enable signal EN becomes the “H” level, and the timing circuit 120 outputs the external clock CL.
At the fall of K, the internal clock CLK1 is generated.
On the other hand, when the duty of the external clock CLK becomes unbalanced and the pulse width of the low period of the external clock CLK becomes shorter than the specification, the external clock CLK becomes “H”.
The level period becomes longer, and the external clock CLK is at the “H” level at the time of the fall of the delay circuit 111. When the delay circuit 11 falls, the SR latch circuit 113 NORs the “H” level output of the inverter 112 and the “H” level output of the delay circuit 111, and sets the “L” level to the DFF 114. It is outputting.

The DFF 114 latches the data S113 at the fall of the delay circuit 111, outputs the "L" level, and sets the enable signal EN to the "L" level. As a result, at the next fall of the external clock CLK, the enable signal EN is at the “L” level indicating the unenable state, and therefore the internal clock CLK1 is not generated. Therefore, the memory does not operate in the next cycle, and the operation of the memory in the current cycle is completed. As described above, according to the third embodiment, if the pulse width of the external clock CLK in the low period is shorter than the specification, the next cycle comes while the data writing or the data reading is insufficient. Since the enable signal EN is set to the “L” level at the fall of the external clock CLK in the cycle of, the memory circuit does not operate in the next cycle, and the operation of the memory circuit in the current cycle is completed. There is an advantage that data destruction of the memory can be prevented.

Fourth Embodiment FIG. 11 is a circuit diagram of a semiconductor memory circuit showing a fourth embodiment of the present invention. This semiconductor memory circuit includes a clock determination circuit 200, a read / write circuit 210, a decoder 220, and a memory cell 230. The clock determination circuit 200 has an external clock CLK.
Is input, and the read / write circuit 210 and the decoder 220 are supplied with the falling signal WL of the word line.
The read / write circuit 210 gives a read or write control signal to the memory cell 230 and data at the time of writing. The decoder 220 receives the falling signal WL of the word line from the clock frequency determination circuit 200 and receives the address signal AD from the address signal line (not shown).
By inputting _m , an address signal or a word line falling signal is applied to the word line and the bit line of the memory cell 230. The memory cell 230 has a read / write circuit 21.
A control signal is input from 0, data D _n is input at the time of writing, an address signal is input from the decoder 220, and data D _n is given to the read / write circuit 210 at the time of reading. The clock determination circuit 200 is a means for sensing that the response of the external clock is interrupted, and the read / load circuit 210 and the decoder 220 are based on the word line falling signal WL which is the determination result of the clock determination circuit 200. , A means for controlling the operation of the memory cell 230.

FIG. 12 shows the clock decision circuit 2 in FIG.
It is a circuit diagram of 00. As shown in FIG. 12, the clock determination circuit 200 includes a delay circuit 201, an inverter 202,
It is configured by the DFF 203. Delay circuit 201
Receives the external clock CLK and delays the delay time T2.
The output S201 delayed by 01 is output to the clock terminal CN of the DFF 202. If the external clock CLK is a normal pulse, the delay time T201 is such that the falling edge of the pulse of the external clock CLK is output during the pulse output period immediately after the pulse (for example, the cycle of the external clock CLK. Of less than 3/2). The inverter 202 receives the external clock CLK and outputs it to the D terminal of the DFF 203. The DFF 203 outputs the word line falling signal WL from the Q terminal.

FIG. 13 is a time chart of FIG. The operation of FIG. 11 will be described below with reference to FIG. If the response is interrupted during the operation of the memory circuit (here, it corresponds to the low period of the external clock CLK) for some reason, the external clock CLK remains at the “L” level at the fall of the delay circuit 201. is there. The DFF 203 latches at the falling edge of the delay circuit 201. At this point, the external clock CL
Since K remains at "L" level, the inverter 202
Of the high level is latched by the DFF 203, and the fall signal WL of the word line is set to the “H” level. The falling signal WL of the word line is input to the read / write circuit 210 and the decoder 220 to close the word line of the memory cell 230 during data reading or data writing by these circuits. Therefore, when the response is interrupted during the operation of the memory circuit due to the external clock CLK, the word line is closed by the falling signal WL of the word line. Therefore, the address signal AD
_It is possible to prevent erroneous writing due to a shift in the synchronization between _m and the data signal D _n, and to cut the current consumption. Further, when the supply of the external clock CLK is restarted, the memory circuit can operate from the second cycle.
As described above, according to the fourth embodiment, when the external clock CLK is interrupted during the operation of the memory circuit, the word line of the memory cell is lowered to maintain the state where the write operation or the read operation is not performed. , Data protection is guaranteed and current consumption is reduced. The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications.

First Modification FIG. 14 is a circuit diagram of a semiconductor memory circuit showing a first modification of the first embodiment of the present invention. The difference between the first modification and the first embodiment is that four types of enable signals EN1 to EN are provided according to the frequency of the external clock CLK.
4 to generate enable signals EN1 to E
The timing circuits 321 to 324 generate the internal clock based on N4. This semiconductor memory circuit includes a clock frequency determination circuit 310, timing circuits 321 to 324, a read / write circuit 330, a decoder 340, and a memory cell 350. The clock frequency determination circuit 310 inputs the external clock CLK and inputs the timing circuits 321 to 32.
4 to the enable signals EN1 to EN4, respectively.
The timing circuits 321 to 324 use the enable signal EN.
1 to EN4 are input to the read / write circuit 330 and the decoder 340 to input the internal clock CLK1.
~ Give CLK4. Read / write circuit 330
Is an internal clock C from the timing circuits 321 to 324.
By inputting LK1 to CLK4, a control signal for reading or writing and a data D _n at the time of writing are given to the memory cell 350. The decoder 340 receives the internal clocks CLK1 to CLK4 from the timing circuits 321 to 324.
And an address signal AD _m is input from an address signal line (not shown) to apply the address signal to the word line and the bit line of the memory cell 350. The memory cell 350 is
The read / write circuit 330 inputs a control signal and data Dn _at the time of writing, an address signal from the decoder 340, and gives data to the read / write circuit 330 at the time of reading.

FIG. 15 is a circuit diagram of the clock frequency determination circuit 310 shown in FIG. As shown in FIG. 15, the clock frequency determination circuit 310 includes delay circuits 311-1 and 3-3.
11-3, inverters 312-1 to 312-3, 313
−1 to 313-3, 4-input AND gates 314-1 to 314-1
14-4 and. Delay circuit 311-1
An external clock CLK is input to 311-3.
The delay circuits 311-1 to 311-3 are set so that the respective delay times T311-1 to T311-3 are T311-1 <T311-2 <T311-3. The external clock CLK is
The clock frequency determination circuit 310 classifies the signal into four stages, and any one of the enable signals EN1 to EN4 becomes the “H” level, and the timing circuit 32 corresponding thereto is generated.
Any one of 1 to 324 is enabled. The inverter 312-i (i = 1 to 3) includes a delay circuit 311.
-I output S311-i is input to the inverter 31
Output to 3-i. The AND gate 314-1 receives the enable signals EN1 from the inverters 312-1 to 312-3. The AND gate 314-2 is input from the inverters 312-2, 313-2, 312-3 and outputs the enable signal EN2. AN
The D gate 314-3 has inverters 313-1 and 31.
3-2, 312-3 are input to enable signal E.
Output N3. The AND gate 314-4 is input from the inverters 313-1, 313-2 and 313-3 and outputs the enable signal EN4.

FIG. 16 is a time chart of the clock frequency determination circuit 310 shown in FIG. The operation of FIG. 15 will be described below with reference to FIG. The frequency of the external clock CLK in FIG. 16 corresponds to the frequency of the third highest classification. As in the first embodiment, the internal clock is generated in synchronization with the falling edge of the external clock CLK. At the frequency of the external clock CLK, the inverter 312-
The outputs of 1, 312-2 are "L" level, and the inverter 31
The output of 2-3 becomes "H" level. AND gate 3
14-3 to "H" level, AND gate 314-1,
The "L" level is output from 314-2 and 314-4. As a result, only the enable signal EN3 becomes "H" level, and the other EN1, EN2, EN4 become "L" level. Therefore, the internal clock CLK3 that enables the timing circuit 323 connected to the enable signal EN3 is generated. This internal clock CLK3
Is an optimum clock for the memory circuit at the frequency of the external clock CLK in this case, and the memory cell 350 is stably accessed by this internal clock. In any other case of the frequency of the external clock CLK, any one of the timing circuits 321 to 324 that generates the optimum internal clock is enabled according to the frequency of the external clock CLK. As described above, according to the first modification, the frequency of the external clock CLK is classified into high speed, medium speed, low speed, or higher,
There is an advantage that an optimum internal clock can be generated and the range of operating conditions of the memory circuit can be widened more easily.

Second Modification Example FIG. 17 is a circuit diagram of a semiconductor memory circuit showing a modification example (second modification example) of the fourth embodiment of the present invention. This semiconductor memory circuit includes clock determination circuits 410-A and 410-A.
-B, read / write circuits 420-A, 420-
B, a decoder 430-A, 430-B, and a 2-port memory cell 440. The clock determination circuit 410-A receives the A port external clock CLK and has the same configuration as the clock determination circuit 200 in FIG. The clock determination circuit 410-B receives the B-port external clock CLK and receives the clock determination circuit 20 of FIG.
It has the same configuration as 0. Read / write circuit 420
-A and the decoder 430-A include the clock determination circuit 4
10-A output word line falling signal WL-A
Work based on. Read / write circuit 420-
B and the decoder 430-B are the clock determination circuit 41.
It operates based on the word line falling signal WL-B output from 0-B. ADA _m is an A port address signal, DA _n is an A port data signal, ADB _m is a B port address signal, and DB _n is a B port data signal. The operation of FIG. 17 will be described below.

When both the A port external clock CLKA and the B port external clock CLKB are normal,
The word line falling signals WL-A and WL-B output from the clock determination circuits 410-A and 410-B remain at the "L" level, and the 2-port memory cell 440 has the A port system and the B port system. External clocks CLKA and C
Accessed according to LKB. In addition, A port external clock CLKA or B port external clock CLKB
When the supply of any of the clocks of
When the A port external clock CLKA is stopped, the clock determination circuit 410-A outputs the "H" level word line falling signal WL-A, so that the read / write circuit 420-A and the decoder 430-A are Do not work. On the other hand, since the B port external clock CLKB is normal, the read / write circuit 420-B, the decoder 4
According to 30-B, the 2-port memory cell 440 is accessed. As described above, according to the second modification, since the clock determination circuit of the fourth embodiment is applied to the A port clock CLKA and the B port clock CLKB, malfunction of the memory cell 440 can be suppressed and
There is an advantage that a normal port system can operate.

In addition to the above, there are the following modifications. (1) The internal clocks of the first to third embodiments can be generated in synchronization with the rising edge of the external clock. (2) In the second embodiment, the clock frequency determination circuit 100 determines whether or not the “H” level pulse width satisfies the operating specifications. However, an inverted signal of the external clock CLK should be input to the delay circuit 101. By "L"
It is possible to determine whether the pulse width of the level satisfies the operation specifications. (3) In the third embodiment, it is determined whether the pulse width of the “L” level satisfies the operating specifications. However, by inputting the inverted signal of the external clock CLK to the delay circuit 111, the “H” level is obtained. It is possible to determine whether or not the pulse width of s satisfies the operation specifications. (4) In the fourth embodiment, the word line falling signal WL is output when the response of the external clock CLK is interrupted for some reason, but the control signal for cutting the current path is output. May be. Besides the periphery of the memory cell, there are locations where a current path such as a sense amplifier and a write circuit is generated, so that the current path can be cut by the control signal and the current consumption can be reduced. (5) Enable signal and fourth signal of the second or third embodiment
It is also possible to combine the effects of both by taking the AND with the enable signal of the embodiment.

[0027]

As described in detail above, according to the first and second aspects of the present invention, the clock judging means for judging the frequency of the external clock is provided, and the internal clock is generated based on the judgment result. Since this is done, it is possible to generate an internal clock with optimum timing according to the frequency of the external clock. According to the third to fifth inventions, the clock pulse width determination circuit for determining the pulse width of the external clock is provided, and the internal clock is generated according to the determination result. Therefore, when the pulse width does not satisfy the specifications. Can be processed accordingly. 6th and 7th
According to the invention, since the clock determining means for sensing that the response of the external clock is interrupted is provided, the optimum operation can be selected when the response of the external clock is interrupted.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional synchronous memory circuit.

3 is a circuit diagram of a clock frequency determination circuit in FIG.

FIG. 4 is a time chart of FIG. 3 when the external clock frequency is lower than the reference.

FIG. 5 is a time chart of FIG. 3 when the external clock frequency is higher than the reference.

FIG. 6 is a circuit diagram of a semiconductor memory circuit according to a second embodiment of the present invention.

7 is a circuit diagram of a clock pulse width determination circuit in FIG.

FIG. 8 is a time chart of FIG.

FIG. 9 is a circuit diagram of a clock pulse width determination circuit according to a third embodiment of the present invention.

FIG. 10 is a time chart of FIG.

FIG. 11 is a circuit diagram of a semiconductor memory circuit according to a fourth embodiment of the present invention.

12 is a circuit diagram of a clock determination circuit in FIG.

FIG. 13 is a time chart of FIG.

FIG. 14 is a circuit diagram of a semiconductor memory circuit according to a first modified example of the present invention.

15 is a circuit diagram of a clock frequency determination circuit in FIG.

16 is a time chart of FIG.

FIG. 17 is a circuit diagram of a semiconductor memory circuit according to a second modified example of the present invention.

[Explanation of symbols]

10, 100, 310 Clock frequency determination circuit 100 Clock pulse width determination circuit 200, 410-A, 410-B Clock determination circuit 11, 101, 111, 201 Delay circuit 301-1 to 301-4 Delay circuit 12, 13, 102 , 103, 112, 202 Inverters 302-1 to 302-4, 303-1 to 303-4
Inverter 113 SR latch circuit 114,203 DFF 21,22,120,311-314 Timing circuit 30,130,210,330 Read / write circuit 410-A, 410-B Read / write circuit 40,140,220 Decoder 330, 420-A, 420-B decoders 50, 150, 230, 350, 440 memory cells

Claims (7)

[Claims] 1. A clock frequency determining means for determining a frequency of an external clock, and a timing signal generating means for generating an internal clock based on the determination result of the clock frequency determining means and the external clock. Characteristic semiconductor device. 2. The clock frequency determination means includes one or a plurality of delay circuits that delays the external clock by a predetermined time, and a logic circuit that outputs a plurality of enable signals based on the outputs of the delay circuits. The timing signal generating means includes means for generating a plurality of internal clocks at different timings, each activation / inactivation of which is controlled by each of the plurality of enable signals. The semiconductor device according to claim 1. 3. An "H" level or "L" of an external clock
A clock pulse width determining means for comparing a level pulse width with a threshold value and outputting an enable signal; and a timing signal generating means for generating an internal clock based on the enable signal and an external clock. Characteristic semiconductor device. 4. The semiconductor device according to claim 3, wherein the clock pulse width determination means includes a delay circuit that delays and outputs the external clock for a time corresponding to the pulse width of the threshold value. . 5. The clock pulse width determination means starts a pulse shorter than the threshold in the output period of the pulse immediately after the pulse of the external clock only when the pulse width of the external clock is shorter than the threshold. A delay circuit that delays and outputs the time point, and based on the output of the delay circuit and the external clock,
The semiconductor device according to claim 3, further comprising: a logic circuit that outputs a signal that sets the enable signal to an unenable state at a start time point of a pulse shorter than the threshold value. 6. A semiconductor device comprising: a clock determination unit that senses that the response of the external clock is interrupted; and a control unit that controls the operation based on the determination result of the external clock determination unit. . 7. The clock determination means, if the pulse of the external clock is normal, the external clock pulse is output so that the rising or falling time of the pulse of the external clock overlaps the output period of the pulse immediately after the pulse. 7. The semiconductor device according to claim 6, further comprising: a delay circuit that delays and outputs a clock, and a latch circuit that latches the external clock or an inverted signal thereof using the output of the delay circuit as a clock.