JPH08202370A - Musical sound synthesizer - Google Patents

Abstract

PURPOSE: To obtain a smooth synthesis sound when the interval of the synthesis sound is changed continuously and to increase the number of simultaneous pronounciation when time division multiplexing. CONSTITUTION: This synthesizer is constituted with a drive data generation circuit 101, an adder 107 adding the drive data to the synthesis data, a data storage circuit 102 delaying the addition data by a prescribed time and outputting as the delay data, a whole band-pass filter 103 delaying the delay data by a prescribed time and outputting as the synthesis data, a delay control circuit 104 deciding the delay times of the data storage circuit 102 and the whole band-pass filter 103 and an interpolation operation circuit 201 performing the interpolation operation of the data preserved in the data storage circuit 102 with the delay data before one sample when the pitch is fluctuated and transferring the operation result to the whole band-pass filter 103, and the delay control circuit 104 decides the interval of the synthesis data by setting the delay time of the data storage circuit 102 and the delay time of the whole band-pass filter 103.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical tone synthesizer for synthesizing musical tones by applying a time delay to waveform data using a digital electronic circuit.

[0002]

2. Description of the Related Art Conventionally, various sound source systems for electronic keyboards and synthesizers have been developed, and with the remarkable progress of digital technology in recent years, many high-quality tone synthesizers based on the sound source systems have been developed. Among them, a sound source method has been proposed (for example, Japanese Patent Application No. 5-5
No. 4544), the sound source system is introduced in a form similar to hardware, and therefore it is easy to realize it as a musical sound synthesizer using a digital electronic circuit. A musical tone synthesizer based on the above-described sound source system will be described below with reference to the drawings.

FIG. 3 is a block diagram showing the configuration of a conventional musical sound synthesizer. In FIG. 3, 101 is a drive data generation circuit that generates drive data from the time when tone generation start data is input, 107 is the drive data output from the drive data generation circuit 101, and the combined data output from the all-pass filter 103. Is a data storage circuit for writing the addition data, which is the addition result of the adder 107, to the address indicated by the write address, reading the data at the address indicated by the read address and outputting it as delay data, and 103 for the data An all-pass filter that delays the delay data output from the storage circuit 102 for a predetermined time and then outputs the resultant as synthetic data, and 104 is pitch instruction data that represents a ratio of how much the pitch of the synthetic data is changed with respect to the drive data. Based on K, the delay time of the data storage circuit 102 and the all-pass fill A delay control circuit for generating a sum M of an integer part (integer part int (M) = offset data) and a decimal part (fractional part frac (M)) for controlling the delay time of 103, and 105 is the sound generation start data. When input, the write address is reset to 0, and the difference between the write address and the read address is delayed by the delay control circuit 10.
An address generation circuit for setting a read address so as to obtain the offset data determined in step 4, and thereafter performing an increment operation of the write address and the read address at the generation timing of the system clock ψ, 106 is stored in the data storage circuit 102. A transfer data generation circuit that transfers data or a value 0 to the all-pass filter 103.

Note that the relationship between the pitch instruction data K, the frequency f0 of the drive data, and the synthesized data frequency f1 is expressed in (Equation 1), the relationship between the number of delay stages M and the sum D of the delay times is expressed in (Equation 2), and the integer part
The relationship between int (M) and the delay time DM of the data storage circuit 102 is shown in (Equation 3), and the relationship between the decimal part frac (M) and the delay time DA of the all-pass filter is shown in (Equation 4). .

[0005]

[Equation 1]

[0006]

[Equation 2]

[0007]

(Equation 3)

[0008]

[Equation 4]

FIG. 4 shows a circuit of the drive data generating circuit 101. In FIG. 4, 11 is a counter that resets the count value (address) at the time when the tone generation start data is instructed and then increments the address according to the system clock φ, and 12 is a read-only memory (hereinafter referred to as a read-only memory that stores drive data). ROM)). It should be noted that the ROM 12 has an address area for 128 addresses from 0 to 127, and the value 0 is always 0 at 127.
Is stored. Further, the counter 11 stops the address increment when the address reaches 127 and holds it at the address 127.

FIG. 5 is a circuit diagram of the all-pass filter 103. In FIG. 5, reference numeral 21 denotes a selector that selectively outputs the A input or the B input according to the transfer instruction data, and 22 delays the data output from the selector 21 by a time corresponding to one system clock ψ, that is, one sampling time Ts. The delay device 23 is a data storage circuit 10
24, a multiplier for multiplying the delay data output from 2 and the filter coefficient C output from the delay control circuit 104;
Is an adder that adds the data output from the delay unit 22 and the multiplication result output from the multiplier 23 and outputs the addition result as combined data, and 25 is the inverted value of the combined data and the filter coefficient C ( Multiplier for multiplying with -C), 2
An adder 6 adds the delay data and the multiplication result of the multiplier 25.

FIG. 6 is a circuit diagram of the delay control circuit 104. In FIG. 6, numeral 31 indicates the data storage circuit 1 by the conversion formula of (Equation 5) when the pitch instruction data K is input.
Offset data that is the number of delay stages of 02 (integer part int
(M)) and a filter coefficient C that is the delay time length of the all-pass filter 103, and is a conversion table for obtaining the variation amount ΔM of M that is the sum of the number of delay stages.

[0012]

(Equation 5)

Reference numeral 32 is a selector for selecting the half value of MAX_ADR which is the entire word length of the address of the data storage circuit 102 or the addition result of the adder 34, 33 is a register for holding the data output from the selector 32, 34
Is the data held in the register 33 and the conversion table 3
This is an adder that adds the fluctuation amount ΔM output from 1 to determine the delay stage number M. In the whole pass filter 35, the fractional part of M, which is the sum of the number of delay stages = frac (M)
It is a conversion table for converting into a filter coefficient C having a delay time length of 3.

[0014]

(Equation 6)

Further, M, which is the sum of the number of delay stages, is calculated by the selector 32 based on the operation of either (Equation 7) or (Equation 8).

[0016]

(Equation 7)

[0017]

(Equation 8)

FIG. 7 is a circuit diagram of the address generation circuit 105. Reference numeral 41 is a counter that resets the count value (write address) at the time when the tone generation start data is instructed, and then increments the write address of the data storage circuit 102 according to the generation timing of the system clock ψ, and 42 is offset data (integer Part int
(M)) and MAX_ADR, which is the entire word length of the address of the data storage circuit 102, and 43 is an adder that adds the write address counted by the counter 41 and the subtracted data of the subtractor 42. It is a vessel.

FIG. 8 is a circuit diagram of the transfer data generating circuit 106. In FIG. 8, 51 is the offset data output from the delay control circuit 104 (integer part int
(M)) is the time corresponding to one system clock ψ, that is, one
A delay device for delaying the sampling time Ts, 52 is a subtracter for subtracting the output of the delay device 51 from the offset data (integer part int (M)) output from the delay control circuit 104, 5
3 is a comparator for comparing the output data (A input) of the subtracter 52 with the B input (1.0) and the C input (-1.0), and 5
Reference numeral 4 is a selector that selects and outputs the A input or the B input according to the output of the comparator 53, and 55 is an OR gate that outputs the value input from the comparator 53 as transfer instruction data.

The operation of the conventional tone synthesizing apparatus configured as described above will be described below.

When the pitch designation data K is designated, the selector 32 of the delay control circuit 104 causes the data storage circuit 102 to operate.
A half value of the entire word length MAX_ADR is selected, and thereafter, the number of delay stages M (= delay time T) is selected. Register 33
Then, the data selected by the selector 32 is held and the adder 3
In step 4, the number of delay stages M is calculated by adding the variation amount ΔM output from the conversion table 31 to the data held in the register 33, the integer part of M is output as offset data, and the decimal part frac ( M) to conversion table 35
Is output as the filter coefficient C of the all-pass filter 103 according to (Equation 6).

The address generation circuit 105 resets the write address, which is the count value of the counter 41, to the value 0 when the tone generation start data is input, and writes the data in the data storage circuit 102 while incrementing the address every sampling cycle Ts. Output as an address. The subtracter 42 adds the result obtained by subtracting the integer part int (M) from MAX_ADR, which is the entire word length of the data storage circuit 102, and the write address, and outputs it as a read address. The integer part int (M) corresponds to the word length width in which the write address precedes the read address, and consequently becomes the number of delay stages of the data storage circuit 102. Also, the fractional part frac (M) is an all-pass filter 103.
It becomes the number of delay stages. In the data storage circuit 102, when the tone generation start data is instructed, first, the data storage circuit 10
All the values stored in 2 are reset to 0, the addition data is indicated by the address generation circuit 105, the addition data is written to the write address, the value indicated by the read address is read, and the delayed data is output. The all-pass filter 103 multiplies the delay data and the filter coefficient C, and outputs the addition result of this multiplication result and the value of the delay device 22 as combined data. On the other hand, the addition result is multiplied by the sign inversion value of the filter coefficient C, the multiplication result is added with the delay data output from the data storage circuit 102, and the result is written in the delay unit 22. All-pass filter 103
The data output from is output as combined data, and is also output to the adder 107 as an addition value with the drive data.

As described above, the driving data is added to the adder 1
07, the data storage circuit 102, and the all-pass filter 103
Since it loops through the loop formed by and, it is output as synthesized tone data.

Regarding the above operation, the data storage circuit 102
The operation of the data transfer circuit 12 will be described in detail with reference to actual drive waveform data (FIG. 9, (Table 1), (Table 2)). Here, a case will be described in which MAX_ADR, which is the entire word length of the data storage circuit 102, is changed to 2048, and the variation amount ΔM is changed from the value 0 to (−0.03). 1024
The fluctuation amount ΔM is 0 for the Ts sampling (1024 Ts).
After that, the operation when the pitch is raised by setting the variation amount ΔM to a value (−0.03) will be described with reference to FIG. 9 and (Table 1) (Table 2).

[0025]

[Table 1]

[0026]

[Table 2]

First, when the pitch designation data K is designated,
That is, when the sampling time is 0Ts, the data storage circuit 1
The stored values of 02 are all reset to (value 0), the value 0 of the drive waveform data is written to the address indicated by the write address, and the delay data (value 0) stored at the address indicated by the read address is passed through the all-pass filter 103. Is multiplied by the filter coefficient C (value 1) in the multiplier 54 and the multiplication result (value 0) is stored in the delay device 22 (value 0).
Is added by the adder 24 and output as combined data (see time 0Ts in (Table 1) and (Table 2) of FIG. 9A). Further, the result (value 0) obtained by multiplying the sign inversion value (value (−1)) of the filter coefficient C by the multiplier 25 is the adder 2
At 6, the delay data value 0 is added, the addition result (value 0) is assigned to the delay unit 22, and the write address value is incremented by 1 (FIG. 9 (a), (Table 1) (Table 2). )
Time 0Ts). By performing such an operation, the time 0T in (FIGS. 9 (a), (b), (Table 1) and (Table 2))
s to 1024 Ts) is obtained as a composite data value. Further, when the pitch is switched, that is, when the sampling time is switched from 1024Ts to 1025Ts (when the integer part int (M) is switched from the value 1024 to the value 1023) (Fig. 9 (d), (Table 2)). At time 1025
See Ts. ), The transfer data generation circuit 106 transfers the transfer data (value 1) to the delay unit 22 of the all-pass filter in FIG.
(30.89) is transferred to remove the noise generated when the integer part int (M) is switched, and the pitch is increased with respect to the input drive data as shown in (FIG. 11). I understand.

Incidentally, the time 1025 in (FIG. 9 (c), (Table 1))
Ts) represents the operation in the case where the transfer data generating circuit 106 is not provided, and when the pitch is switched, that is, the integer part int
At the time when (M) switches from the value 1024 to the value 1023, the output waveform deviates greatly from the expected value (value 134.82) to (value 3.98), and this deviation is output as noise. (See Figure 10). This expected value is the data (value 130.8
This is the value that should be output when 9) is read. Also,
The transfer data at this time is assumed to be the data stored in the foreground of the address designated by the read address, that is, the value skipped when the pitch is changed.

[0029]

However, in the above configuration, the data storage circuit 10 is used when the pitch is raised.
At the time of memory access of 2, the number of memory accesses required when processing one sample of musical tone data is read from the address indicated by the read address. When the integer part int (M) is switched, the value of the previous address pointed to is read out. Write the drive waveform to the address indicated by the write address. It was necessary three times to say. In this case, in a musical tone synthesizing device intended to realize continuous and smooth synthesis of musical tones without following the sampling time Ts in time-divisional processing of a plurality of sounds, the number of memory accesses becomes a bottleneck and the time-division processing is also limited. Was occurring.

[0030]

In order to solve the above-mentioned problems of the conventional example, the musical tone synthesizing apparatus of the present invention is a driving data generating means for generating driving data in response to a sounding start instruction, and driving data and synthetic data. Adding means for adding and
A data storage means for temporarily storing the addition result of the addition means and outputting it as delay data after delaying it by a predetermined time, an all-pass filter for delaying the delay data for a predetermined time and outputting it as synthesized data, and a data storage means based on the pitch instruction. And delay control means for determining the delay time of the all-pass filter, and temporarily storing the data stored in the data storage means,
And an interpolation calculation means for transferring to the all-pass filter.

[0031]

[Operation] With the above configuration, the integer part when the pitch is raised
When switching int (M), with a simple configuration, the value newly read from the data storage circuit and the value temporarily stored in the interpolation calculation circuit are interpolated and transferred to the delay unit of the all-pass filter as interpolation data. Therefore, a smooth waveform is synthesized.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the musical sound synthesizer of the present invention. In FIG. 1, 201 is an interpolation calculation circuit. The other blocks have the same structure as the conventional example.

FIG. 2 is a circuit diagram of the interpolation calculation circuit 201. In FIG. 2, 61 is a data storage circuit 102.
Delay device for temporarily delaying the delay data output from the device, 6
2 is an adder for adding the delay data output from the data storage circuit 102 and the delay data output from the delay device 61, and 63 is for extracting half the value of the addition data output from the adder 62. It is a multiplier that multiplies a half value.

The operation of the musical tone synthesizing apparatus configured as described above will be described. Since the basic operation is the same as that of the conventional tone synthesizer (FIG. 3), only the differences will be described. The difference is that in the interpolation calculation circuit 201, instead of the transfer data generation circuit 106 used to remove noise (data loss for one sample) when switching the integer part int (M) when the pitch is raised. , The integer part int (M) is switched, that is, the value of the offset data is switched,
The delay data output from the data storage circuit 102 and the delay data stored in the delay device 61 in the interpolation calculation circuit 201 (the data storage circuit 1 before the integer part int (M) is switched)
The value read from 02) is added, and the multiplier 63 calculates a half value (1/2) of the added data, and this multiplied data is used as interpolation data to obtain the all-pass filter 10
Data is temporarily stored in the interpolation calculation circuit 201 while compensating for data loss by transferring the data (integer part in
Since the value read from the data storage circuit 102 before t (M) is switched is used, only one read from the data storage circuit required to calculate one sample is required. This is less than the number of times of reading (3 times) when the generation circuit 106 is used.

As described above, according to this embodiment, at the time of switching the integer part int (M) when increasing the pitch, the interpolation operation circuit compensates for the data loss with a simple structure.
It is not necessary to newly read from the data storage circuit to calculate one sample, and the reading and writing time of the data storage circuit can be minimized, that is, the calculation speed can be increased.

[0037]

As described above, according to the present invention, the delay time of the data storage means and the all-pass filter is determined on the basis of the instruction of the pitch instruction data K, and the interpolation calculation means determines the delay time within the all-pass filter. By transferring the interpolation data to the delay device, it is possible to smoothly synthesize the timbre of the synthesized data without generating unnecessary noise. Furthermore, the computation time for one synthesized sample is shorter than in the past, so It is possible to increase the speed, and it is possible to increase the number of simultaneous sounds when more time division multiplexing is used.

[Brief description of drawings]

FIG. 1 is a block diagram of a musical sound synthesizer according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an interpolation calculation circuit of the musical sound synthesizer in the embodiment of the present invention.

FIG. 3 is a block diagram of a musical sound synthesizer in a conventional example.

FIG. 4 is a circuit diagram of a drive data generation circuit of a musical sound synthesizer in a conventional example.

FIG. 5 is a circuit diagram of an all-pass filter of a musical sound synthesizer in a conventional example.

FIG. 6 is a circuit diagram of a delay control circuit of a musical sound synthesizer in a conventional example.

FIG. 7 is a circuit diagram of an address generation circuit of a musical sound synthesizer in a conventional example.

FIG. 8 is a circuit diagram of a transfer data generation circuit of a musical sound synthesizer in a conventional example.

FIG. 9 shows a variation amount ΔM in the conventional example from a value 0 to (−0.
(A) is an operation explanatory diagram at time 0Ts, (b) is an operation explanatory diagram at time 1024Ts, and (c) is transfer data generation at time 1025Ts. Operation explanatory diagram when there is no circuit (d) is an operation explanatory diagram when there is a transfer data generation circuit at time 1025Ts

FIG. 10 is an output waveform diagram of synthesized data in the case where the transfer data generation circuit is not provided in the conventional musical tone synthesis apparatus.

FIG. 11 is an output waveform diagram of synthesized data when a transfer data generating circuit is used in a musical tone synthesizer of a conventional example.

[Explanation of symbols]

 101 Drive Data Generation Circuit 102 Data Storage Circuit 103 All-Pass Filter 104 Delay Control Circuit 105 Address Generation Circuit 107 Adder 201 Interpolation Operation Circuit

Claims (1)

[Claims] 1. A drive data generating means for generating drive data in response to a sounding start instruction, an adding means for adding the drive data and synthetic data described later, and data for delaying the output of the adding means for a predetermined time and outputting it as delay data. Storage means, an all-pass filter that delays the delay data for a predetermined time and outputs as combined data, a delay control means that determines a delay time of the data storage means and the all-pass filter based on pitch instruction data, and the data storage A musical tone synthesizing device comprising: an interpolating operation means for interpolating the data stored in the means and the data delayed by one sampling time and outputting the interpolated data to the all-pass filter.