JPH08195705A - Diversity receiver - Google Patents

Abstract

PURPOSE: To obtain a diversity receiver in which an arithmetic time to obtain diversity synthesis is considerably reduced, the circuit scale is remarkably reduced and the transmission efficiency from a transmitter side is improved. CONSTITUTION: A gain generating section 14 is provided with a gain table memory to store a relation between intensity of a reception signal from an intermediate frequency amplifier 3 or the like and a multiplication coefficient. When the intensity of the reception signal is sent from the intermediate frequency amplifier 3 or the like to the gain generating section 14, a corresponding multiplication coefficient is read from the gain table and given to a multiplier 5 or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diversity receiver used in digital radio communication by two-phase or multi-phase modulation, and more particularly to shortening a calculation time and a scale of a calculation circuit for obtaining diversity combination. Regarding suitable ones.

[0002]

2. Description of the Related Art Conventionally, diversity has been widely used as one of multi-path reception systems, and a receiver based on spatial diversity in this diversity is widely used as a receiver for a radio base in mobile communication. It is believed that it will happen.

FIG. 3 shows a circuit configuration of a conventional two-branch diversity receiver which is an example of the receiver based on the above-mentioned space diversity. In the figure, the receiving antenna 20 of the diversity branch A and the receiving antenna 25 of the diversity branch B are arranged so as to be uncorrelated with each other. Then, the signal input to the diversity branch A side is input to the quadrature detection unit 22 through the reception antenna 20 and the reception unit 21, and the quadrature detection unit 22 performs quadrature detection to output a baseband complex signal. The baseband complex signal is sent to the complex correlation detection unit 24 and the complex multiplier 23, and the complex correlation detection unit 24 is a known signal sequence previously stored in the complex correlation detection unit 24, which is a UW (Unique Wor).
d) and the like are used to obtain the complex correlation with the UW in the received signal (that is, the baseband complex signal). Therefore, when the UW has a sharp autocorrelation characteristic, the output of the complex correlation detector 24 can be regarded as an impulse response of the transmission line, but in fact, the UW has a sharp autocorrelation characteristic. The output of the complex correlation detector 24 can be regarded as the impulse response of the transmission line.

On the other hand, the signal input to the diversity branch B also receives the reception antenna 25, the reception unit 26, and the quadrature detection unit 2.
7 and the complex correlation detector 29 perform the same processing as above. Further, the coefficient calculation unit 32 inputs the outputs from the complex correlation detection unit 24 and the complex correlation detection unit 29, which can be regarded as the impulse response of each transmission line, and receives an independent complex multiplication coefficient for each diversity branch (that is, the impulse The complex conjugate of the response) is calculated and output to the complex multipliers 23 and 28 of each diversity branch, respectively. Then, the complex multipliers 23 and 28 multiply the baseband complex signals sent from the quadrature detectors 22 and 27, respectively, by the complex multiplication coefficients sent independently from the coefficient calculator 32. As a result, the level and the phase are corrected and transmitted. The adder 30 gives a signal obtained by adding the corrected baseband complex signals respectively sent from the complex multipliers 23 and 28 to the decision circuit 31, and the decision circuit 31 decodes the given signal. Turn into. With the above configuration, the maximum ratio combining diversity effect can be obtained.

The coefficient calculator 32 compares the impulse response powers of the transmission paths of the diversity branches A and B, and sends out the complex multiplication coefficient to the diversity branch having the lower power as 0, while When the complex multiplication coefficient for the higher diversity branch is to be transmitted as the complex conjugate of the impulse response of the diversity branch, the signal having the selective diversity effect is transmitted from the adder 30 to the decision circuit 31. .

[0006]

However, in the case of the conventional diversity receiver having the above-mentioned structure, it is necessary for the transmitting side to insert the above-mentioned known signal sequence into the transmission signal. The quadrature detection unit 22
And 27 and subsequent circuit units perform complex number arithmetic operations, but this causes the circuit configuration of the circuit units to be complicated and large-scaled. In particular, the complex correlation detection units 24 and 29 perform complex-sum product arithmetic operations. Because of the repetition of, the complexity and scale up of those circuit configurations becomes significant,
As a result, the calculation processing time in these circuit units also becomes longer.
The present invention has been made in view of the above circumstances, and it is not necessary to insert a known signal sequence into a transmission signal on the transmission side, and the circuit becomes complicated and large-scale due to the necessity of complex number operation. It is an object of the present invention to provide a diversity receiver capable of avoiding an increase in processing time and an increase in calculation processing time.

[0007]

In the present invention, in order to achieve the above object, the diversity receiver is configured as follows. That is, the diversity receiver is connected to a plurality of receiving antennas, and each of the plurality of receiving antennas is connected to a plurality of receiving antennas. A receiver and a frequency synthesizer that supplies a local oscillation frequency to the plurality of receivers, respectively,
It is connected to one of the plurality of receiving units, amplifies and outputs an intermediate frequency signal from the connected receiving unit, and at the same time receives signal strength, that is, RSSI (Received Signal).
A plurality of intermediate frequency amplifiers that output a strength indicator and each of the intermediate frequency amplifiers are connected to one of the plurality of intermediate frequency amplifiers, and the intermediate frequency signals from the connected intermediate frequency amplifiers are differentially detected to detect the position of the preceding symbol. A plurality of differential detection units that create and output a phase difference, and a gain table memory that stores each value of the received signal strength and a multiplication coefficient corresponding to each value in association with each other are provided. When a received signal strength from any of the amplifiers is given, a gain generation unit that reads out and outputs a multiplication coefficient corresponding to the multiplication coefficient from the gain table memory,
Each of them is connected to one of the plurality of differential detection units and corresponds to the phase difference output from the connected differential detection unit and the received signal strength from the intermediate frequency amplifier to which the differential detection unit is connected. A plurality of multipliers that multiply the multiplication coefficient output from the gain generating unit and output the multiplication result, and add the respective multiplication results from the plurality of multipliers,
It is configured to include an adder that outputs an addition result and a determination circuit that determines a signal from the addition result from the adder.

[0008]

First, in the above configuration, the known signal sequence is not used. Therefore, the transmitting side does not need to insert the known signal sequence into the transmission signal and transmit the signal, so that the transmission efficiency can be improved. There is. Further, the gain generation unit includes a gain table memory that stores the relationship between the received signal strength and the multiplication coefficient in advance as a table and stores the corresponding multiplication coefficient according to the received signal strength that is sent. Only the data is read out from the table memory and sent out, which contributes to the reduction in processing time and the circuit scale. Further, since the differential detection unit executes differential detection, phase adjustment between diversity branches is not necessary, and the weighting and combining in the multiplier and adder is executed by the scalar value (that is, the complex number operation is not performed). However, it is possible to reduce the circuit scale and processing time.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the embodiments shown in the drawings. FIG. 1 shows a circuit configuration of an embodiment of the present invention. That is, in this embodiment, the diversity branch including the receiving antenna 1, the receiving unit 2, the intermediate frequency amplifier 3, the differential detecting unit 4 and the multiplier 5 and the receiving antenna 6,
A diversity branch including a reception unit 7, an intermediate frequency amplifier 8, a delay detection unit 9 and a multiplier 10 is provided, and a two-branch diversity receiver is provided. The receiving antennas 1 and 6 are arranged so as to be uncorrelated with each other. The frequency synthesizer 13 is a circuit section that supplies a local oscillation frequency to the receiving sections 2 and 7 of both diversity branches. The receiving units 2 and 7 are circuit units that convert the high frequency received signals from the receiving antennas 1 and 6 into an intermediate frequency signal by the local oscillation frequency from the frequency synthesizer 13 and output.

The intermediate frequency amplifiers 3 and 8 amplify the intermediate frequency signals sent from the receivers 2 and 7, respectively, and send them to the delay detectors 4 and 9, respectively, and measure the power at the time of reception to obtain the respective powers. Value (ie the RSS
I) is a circuit unit for sending the I) to the gain generation unit 14. The differential detection units 4 and 9 perform differential detection on the intermediate frequency signals amplified by the intermediate frequency amplifiers 3 and 8, respectively, and perform 1
This is a circuit unit that extracts the phase difference (Δθ ₁ and Δθ ₂ ) from the signal before the symbol and outputs it to the multipliers 5 and 10, respectively. FIG. 2 is for explaining the differential detection. The phase difference Δθ ₁ (denoted as Δθ ₁ [n] in the figure) output from the differential detection unit 4 is one symbol before. indicates that a difference between the time obtained by subtracting the phase theta ₁ after row symbols of the signal i.e. the drawing of this symbol from the phase θ ₁ [n] of the preceding symbol of the signal or the figure of [n-1] ing.

The gain generator 14 receives the received signal strength (that is, RSSI) sent from the intermediate frequency amplifiers 3 and 8.
And a gain table memory that stores the corresponding multiplication coefficient in association with each other, and a circuit for reading out and transmitting the corresponding multiplication coefficient from the gain table memory based on the received signal strength transmitted. Assuming that the received signal strengths from the intermediate frequency amplifiers 3 and 8 are R1 and R2, respectively, and the multiplication coefficients sent from the gain generator 14 to the multipliers 5 and 10 are G1 and G2, these are respectively It is represented by the formulas (1) and (2) shown below. G1 = R1 / (R1 + R2) ……………… (1) G2 = R2 / (R1 + R2) ……………… (2)

The multipliers 5 and 10 are respectively provided with the phase difference (that is, Δθ shown in FIG. 1) from the differential detection sections 4 and 9.
₁ [n] and Δθ ₂ [n]) are input, and the multiplication coefficients G1 and G from the gain generator 14 are input, respectively.
This is a circuit unit that obtains 2, performs multiplication of the phase difference and the multiplication coefficient, and outputs the multiplication result to the adder 11. Further, the adder 11 is a circuit unit for adding and synthesizing the multiplication results sent from the multipliers 5 and 10 as described above and sending out the addition and synthesizing result (Δθ shown in FIG. 1) to the judging circuit 12. The determination circuit 12 is a circuit unit that inputs the above-mentioned addition and synthesis result Δθ sent from the adder 11 and executes decoding based on this. Next, the operation of this embodiment configured as described above will be described. Now, it is assumed that the transmission side employs two-phase or multi-phase modulation as a modulation method and performs differential encoding.

The signal sent from the transmitting side is received by the receiving antennas 1 and 6. Then, what is received by the receiving antenna 1 is frequency-converted by the receiving section 2, amplified by the intermediate frequency amplifier 3, detected by the delay detecting section 4, and output from the delay detecting section 4 as a phase difference Δθ ₁ .
On the other hand, what is received by the receiving antenna 6 is frequency-converted by the receiving unit 7, amplified by the intermediate frequency amplifier 8 and detected by the delay detecting unit 9, and the phase difference Δθ is detected from the delay detecting unit 9.
It is output as ₂ . Then, the phase difference Δθ ₁ is
The multiplication coefficient G1 is multiplied by the multiplier 5, and the multiplication result is sent to the adder 11. The phase difference Δθ ₂ is multiplied by the multiplication coefficient G2 in the multiplier 10, and the multiplication result is sent to the adder 11. Then, the adder 11 adds and synthesizes the two multiplication results sent thereto to obtain an addition synthesis result Δθ, and sends this to the determination circuit 12. Therefore, the following expression (3) is established. Δθ = G1 · Δθ ₁ + G2 · Δθ ₂ (3) Here, the differential detection vectors of the differential detection units 4 and 9 represented by complex numbers (vectors) are R1 · exp (j), respectively.
Δθ ₁ ) and R2 · exp (jΔθ ₂ ). Since these are already weighted with absolute values R1 and R2, respectively, the maximum ratio combined vector R · exp (jΔΦ) of the two-branch diversity differential detection output is obtained.
(Where R and ΔΦ represent the magnitude and difference phase of the combined vector, respectively) are the simple sum R · exp (jΔΦ) = R1 · exp (jΔθ ₁ ) + R2 · exp (jΔθ ₂ ) ... ( 4) is given in.

According to Taylor series expansion, X <<
When it is 1, exp (X) ≈1 + X …………………… (5). Therefore, assuming that Δθ ₁ and Δθ ₂ << 1 …………………… (6) and applying the above equation (5) to the above equation (4), the following equation (7) is obtained. Is obtained. R · exp (jΔΦ) ≈R1 (1 + jΔθ ₁ ) + R2 (1 + jΔθ ₂ ) = (R1 + R2) + j (R1 · Δθ ₁ + R2 · Δθ ₂ ) ... (7) From the formula (7), the maximum ratio of the delayed detection output is obtained. The differential phase ΔΦ obtained from the combined vector R · exp (jΔΦ) is approximately obtained by the following equation (8). ΔΦ ≈ (R1 · Δθ ₁ + R2 · Δθ ₂ ) / (R1 + R2) (8) Then, substituting the formulas (1) and (2) into this formula (8), ΔΦ ≈ G1 · Δθ ₁ + G2 Δθ ₂ ……… (9) is obtained. The right side of the equation (9) is nothing but the right side of the equation (3), that is, the output of the adder 11 (the weighted scalar combination of Δθ ₁ and Δθ ₂ by G1 and G2). Therefore, the output of the adder 11 is the maximum ratio combined vector R · exp (jΔ
It can be regarded as the differential phase obtained from Φ), and the maximum ratio combining diversity effect can be obtained.

By the way, although the above description is for the case where the above equation (6) is established, Δθ ₁ and Δ
When θ ₂ is close to π / 2 radians, for example, Δθ ₁ = Δθ ₁ ′ + π / 2 (10) Δθ ₂ = Δθ ₂ ′ + π / 2 ………… (11) Δθ ′ ₁ , Δθ ′ ₂ << 1 ……………… (12) can be set, and the following equations (13) and (14) are obtained. exp (jΔθ ₁ ) = jexp (jΔθ ₁ ′) (13) exp (jΔθ ₂ ) = jexp (jΔθ ₂ ′) (14) Formulas (13) and (14) are given by (4) ) Shows that each differential detection vector in the equation can be treated as a vector rotated leftward by π / 2, and even if the condition of the equation (6) is not satisfied,
The above explanation is correct under the conditions represented by the above equations (10), (11), and (12). That is, Δθ ₁ , Δθ
₂ indicates that the outputs of the adder 11 (that is, the output expressed by the equation (3)) are the same as the differential detection output expressed by the equation (8), although the degrees of approximation are different as long as they are in the same value region to some extent. Is the same as the differential phase ΔΦ obtained from the maximum ratio combined vector of

The received signal after diversity combining is decoded by the decision circuit 12. The multiplication coefficients G1 and G provided from the gain generator 14 to the multipliers 5 and 10
When the one corresponding to the smaller of the received signal strengths R1 and R2 of 2 is set to 0, the output of the adder 11 has the selective diversity effect. That is, the combined diversity or the selected diversity is instantly realized depending on the multiplication coefficient from the gain generator 14.

As described above, in the present embodiment, the relationship between the received signal strength (RSSI) and the multiplication coefficient is made into a table and set in the gain table memory of the preliminary gain generating section 14 to obtain the diversity effect. Therefore, the complex number correlation operation and the complex number weighting / combining operation, which increase the processing time and increase the circuit scale, are no longer required. Further, since the differential detection is used, it is not necessary to adjust the phase between the diversity branches, and since the weighted synthesis by the scalar value is used, the whole circuit scale is reduced. Further, the transmitter of the transmission / reception system using the present embodiment does not need to insert the known signal sequence into the transmission signal, which improves the transmission efficiency.

The present invention is not limited to the above embodiments, and various modifications and applications are possible without departing from the scope of the present invention. For example, in the above-mentioned embodiment, only two diversity branches are provided, but it goes without saying that this may be provided with three or more diversity branches.

[0019]

As described in detail above, according to the present invention,
Providing a diversity receiver that can significantly reduce the computation time for obtaining diversity combining, can significantly reduce the circuit scale, and can improve transmission efficiency because it does not require insertion of a known signal sequence in the signal on the transmitting side Is possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining differential detection.

FIG. 3 shows a configuration of a conventional diversity receiver.

[Explanation of symbols]

 2 reception unit 3 intermediate frequency amplifier 4 delay detection unit 5 multiplier 7 reception unit 8 intermediate frequency amplifier 9 delay detection unit 10 multiplier 11 adder 12 determination circuit 13 frequency synthesizer 14 gain generation unit 21 reception unit 22 quadrature detection unit 23 complex Multiplier 24 Complex correlation detector 26 Receiver 27 Quadrature detector 28 Complex multiplier 29 Complex correlation detector 30 Adder 31 Judgment circuit 32 Coefficient calculator A Diversity branch B Diversity branch

Claims (1)

[Claims] 1. A plurality of receiving antennas, and a plurality of receiving antennas, each of which is connected to one of the plurality of receiving antennas and frequency-converts an input signal from the connected receiving antennas from a high frequency signal to an intermediate frequency signal. Section, a frequency synthesizer for supplying a local oscillation frequency to the plurality of receiving sections, and each of which is connected to one of the plurality of receiving sections, and amplifies and outputs an intermediate frequency signal from the connected receiving section. A plurality of intermediate frequency amplifiers that output the received signal strength together with each of the plurality of intermediate frequency amplifiers, and
A plurality of differential detection units that differentially detect the intermediate frequency signal from the connected intermediate frequency amplifier, create a phase difference from the preceding symbol and output it, and the above-mentioned respective values of the received signal strength and the respective values A gain table memory is stored which is associated with a multiplication coefficient, and when a received signal strength from any of the plurality of intermediate frequency amplifiers is given, the corresponding multiplication coefficient is read from the gain table memory. And a phase difference output from the connected delay detection unit, which is connected to one of the plurality of delay detection units described above, and an intermediate frequency amplifier connected to the delay detection unit. Of a plurality of multipliers for multiplying the multiplication coefficient output from the gain generating unit as a signal corresponding to the received signal strength and outputting a multiplication result, and each multiplication from the plurality of multipliers. Adding fruit, an adder for outputting the addition result, the diversity receiver characterized by comprising a determination circuit for determining signal from the addition result from the adder.