JPH08195474A - Semiconductor device, electric components, and electric devices for multiple mounting - Google Patents

Semiconductor device, electric components, and electric devices for multiple mounting

Info

Publication number
JPH08195474A
JPH08195474A JP7004952A JP495295A JPH08195474A JP H08195474 A JPH08195474 A JP H08195474A JP 7004952 A JP7004952 A JP 7004952A JP 495295 A JP495295 A JP 495295A JP H08195474 A JPH08195474 A JP H08195474A
Authority
JP
Japan
Prior art keywords
lead
sealing body
semiconductor device
semiconductor
electronic components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7004952A
Other languages
Japanese (ja)
Inventor
Masakuni Shibamoto
正訓 柴本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7004952A priority Critical patent/JPH08195474A/en
Publication of JPH08195474A publication Critical patent/JPH08195474A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Abstract

PURPOSE: To dispense with various kinds of packages and lead frames by mounting a semiconductor device or electronic components having specified intermediate leads, on a mounting substrate, and mounting other semiconductor devices or electronic components on the semiconductor device or the electronic components mounted on the substrate. CONSTITUTION: This device is provided with an intermediate lead 7 where one end is electrically connected with a lead and the other end is exposed on the surface of a sealing body. Semiconductor devices 21 and 23 or electronic components 22 and 24 having these relays are mounted on a mounting substrate 1. And, other semiconductor devices 31 and 32 or electronic components 33 are mounted on the semiconductor devices 21 and 23 or the electronic components 22 and 24 mounted on the board 1. Furthermore, the semiconductor device 13 or the electronic components 33 is given heat conductive members 9 and 16, which absorbs and radiates the heat of the semiconductor device whose heat radiation is not performed enough, being surrounded by other semiconductor devices 11, 12, 21, 23, 31 and 32, the electronic components 22 and 24, or the substrate 1. The density of mounting of electronic components can be improved, by mounting such devices, etc., in multilayers.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多重実装用の電子部
品、半導体装置及びそれを用いた電子装置に関し、特
に、実装基板上への高密度の実装に適用して有効な技術
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component for multiple mounting, a semiconductor device and an electronic device using the same, and more particularly to a technique effective when applied to high-density mounting on a mounting substrate. is there.

【0002】[0002]

【従来の技術】半導体装置を用いた電子装置では、プリ
ント基板等の配線が形成された実装基板に各種の半導体
装置及び抵抗器コンデンサなどの各種電子部品を取付け
半田フローなどの方法で固定し且つ電気的な接続を行な
っている。
2. Description of the Related Art In an electronic device using a semiconductor device, various semiconductor devices and various electronic components such as a resistor capacitor are attached to a mounting substrate on which wiring such as a printed circuit board is formed and fixed by a method such as a soldering flow. Makes electrical connections.

【0003】[0003]

【発明が解決しようとする課題】電子装置では、近年よ
り一層の小型化及び高速化が要求され、これに対して半
導体装置或いは実装基板の性能を上げることで対処して
いるが、このような対処には限界があり、また結果的に
価格の上昇を招いてしまう。
In recent years, electronic devices have been required to be further miniaturized and speeded up, and this has been dealt with by improving the performance of the semiconductor device or the mounting substrate. There are limits to what can be done, and as a result, prices will rise.

【0004】また、多くの半導体装置を実装する場合に
は、強度等の問題から実装基板の大きさが制限され、そ
の結果すべての半導体装置を一枚の基板に実装すること
ができずに、複数の実装基板に半導体装置を実装し、各
基板にコネクタを設けケーブルによって各基板を接続す
る場合がある。
Further, when many semiconductor devices are mounted, the size of the mounting substrate is limited due to problems such as strength, and as a result, all semiconductor devices cannot be mounted on one substrate, In some cases, semiconductor devices are mounted on a plurality of mounting boards, connectors are provided on the boards, and the boards are connected by cables.

【0005】このような場合には、コネクタ及びケーブ
ルによって製品の価格が上昇し、コネクタ或いはケーブ
ルの接触不良等によって信頼性が低下し、加えて配線長
の増加によって動作速度の低下或いはケーブルからの混
入によるノイズの増加を招いてしまうことがある。
In such a case, the price of the product increases due to the connector and the cable, the reliability decreases due to the contact failure of the connector or the cable, etc., and the operating speed decreases due to the increase in the wiring length or the cable is removed from the cable. The noise may be increased due to the mixing.

【0006】このような問題を解決するために、特願平
2‐98301号或いは特願平5‐122726号のよ
うに実装基板上に半導体装置を多重実装することが考え
られている。しかしながらこれらの発明では特殊なパッ
ケージ或いはリードフレームが必要になり、通常の製品
とは互換性がなくなくなり、コストが上昇する。或い
は、技術適用の自由度が低い等の問題がある。
In order to solve such a problem, it is considered to mount multiple semiconductor devices on a mounting substrate as in Japanese Patent Application No. 2-98301 or Japanese Patent Application No. 5-122726. However, these inventions require special packages or lead frames, are not compatible with ordinary products, and increase costs. Alternatively, there is a problem that the degree of freedom in applying the technology is low.

【0007】本発明の目的は、電子装置の実装密度を高
め、かつ前述した問題を解決することが可能な技術を提
供することにある。
An object of the present invention is to provide a technique capable of increasing the mounting density of electronic devices and solving the above-mentioned problems.

【0008】本発明の他の目的は、電子装置を多重実装
した際に放熱性を向上させて、安定した作動をさせるこ
とが可能な技術を提供することにある。
It is another object of the present invention to provide a technique capable of improving heat dissipation and stably operating when multiple electronic devices are mounted.

【0009】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0010】[0010]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。
Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

【0011】中継機能を有する半導体装置或いは電子部
品を実装基板上に実装し、基板に実装した半導体装置或
いは電子部品の上に、他の半導体装置或いは電子部品を
実装する。更に、半導体装置或いは電子部品に、伝熱機
能を付与し他の半導体装置,電子部品或いは基板に囲ま
れて放熱が充分に行なわれない半導体装置の熱を吸収
し、放熱する。
A semiconductor device or electronic component having a relay function is mounted on a mounting substrate, and another semiconductor device or electronic component is mounted on the semiconductor device or electronic component mounted on the substrate. Further, the semiconductor device or the electronic component is provided with a heat transfer function to absorb and radiate the heat of the semiconductor device surrounded by other semiconductor devices, electronic components or the substrate, which does not sufficiently radiate heat.

【0012】[0012]

【作用】上述した手段によれば、半導体装置或いは電子
部品を多重に実装することによって、電子装置の実装密
度を向上させることができる。加えて、半導体装置或い
は電子部品に、伝熱機能を付与することによって、放熱
性が向上し性能が安定する。
According to the above-mentioned means, the mounting density of the electronic devices can be improved by mounting the semiconductor devices or the electronic parts in multiple layers. In addition, by imparting a heat transfer function to the semiconductor device or the electronic component, heat dissipation is improved and performance is stabilized.

【0013】以下、本発明の構成について、実施例とと
もに説明する。
The structure of the present invention will be described below together with embodiments.

【0014】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。
In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

【0015】[0015]

【実施例】【Example】

(実施例1)図1に示すのは、本発明の一実施例である
電子装置を示す縦断面図である。本実施例では、複数の
半導体装置及び電子部品を3層に積層して接続し、電子
装置を構成する。
(Embodiment 1) FIG. 1 is a vertical sectional view showing an electronic device according to an embodiment of the present invention. In this embodiment, a plurality of semiconductor devices and electronic components are laminated in three layers and connected to form an electronic device.

【0016】図中、1は実装基板であり、実装基板1
は、ガラスエポキシ系樹脂、セラミック等の絶縁体1a
に、銅、アルミニウム等の導体1bをパターン形成して
構成する。
In the figure, reference numeral 1 denotes a mounting board, and the mounting board 1
Is an insulator 1a such as glass epoxy resin or ceramic
Then, a conductor 1b such as copper or aluminum is formed by patterning.

【0017】実装基板1面上には1層目の半導体装置1
1,12,13を表面実装し、半導体装置11,12,
13に2層目の半導体装置21,23及び電子部品2
2,24を接続し、半導体装置21,23及び電子部品
22,24に3層目の半導体装置31,32及び電子部
品33を接続する。
The semiconductor device 1 of the first layer is provided on the surface of the mounting substrate 1.
1, 12, 13 are surface-mounted, and semiconductor devices 11, 12,
13, the second-layer semiconductor devices 21 and 23 and the electronic component 2
2, 24 are connected, and the semiconductor devices 31, 32 and the electronic component 33 of the third layer are connected to the semiconductor devices 21, 23 and the electronic components 22, 24.

【0018】半導体装置11,12,13,21,2
3,31,32は、SOP(Small Outline Package)
型の半導体装置であり、所定の回路を形成した半導体チ
ップ2をタブ3に載置し、従来の半導体装置に用いられ
るリード4(以下、単にリードという)のインナーリー
ド4aと半導体チップ2とをボンディングワイヤ5によ
って接続し、半導体チップ2,インナーリード4a,ボ
ンディングワイヤ5をエポキシ樹脂等の封止体6によっ
て封止してある。インナーリード4aは半導体装置の外
部端子であるアウターリード4bと一体になっており、
アウターリード4bにて実装基板1或いは他の半導体装
置11,12,13,21,23に接続する。
Semiconductor devices 11, 12, 13, 21, 2
3, 31, 32 are SOP (Small Outline Package)
Type semiconductor device, a semiconductor chip 2 having a predetermined circuit formed thereon is mounted on a tab 3, and an inner lead 4a of a lead 4 (hereinafter simply referred to as a lead) used in a conventional semiconductor device and a semiconductor chip 2 are connected to each other. The semiconductor chip 2, the inner leads 4a, and the bonding wires 5 are connected by the bonding wires 5, and are sealed by a sealing body 6 made of epoxy resin or the like. The inner lead 4a is integrated with the outer lead 4b which is an external terminal of the semiconductor device,
The outer leads 4b are connected to the mounting substrate 1 or other semiconductor devices 11, 12, 13, 21, 23.

【0019】電子部品22,24,33は、半導体装置
と略同様の形状であるが半導体チップを搭載せず、封止
体6とリード4とを有し、前記リード4のインナーリー
ド4aが封止体6内部に収容され、アウターリード4b
が封止体6外部に延出する。
The electronic components 22, 24 and 33 have substantially the same shape as the semiconductor device, but do not have a semiconductor chip mounted thereon, have a sealing body 6 and leads 4, and the inner leads 4a of the leads 4 are sealed. The outer lead 4b is housed inside the stopper 6.
Extend to the outside of the sealing body 6.

【0020】この電子部品22,24,33の製造に
は、通常の半導体装置の製造技術を流用することが可能
である。半導体装置製造用のリードフレームに所定の配
線を行ない、半導体装置と同様に封止体に封止し、リー
ドの成形を行なって製造する。
For manufacturing the electronic components 22, 24 and 33, it is possible to use a normal manufacturing technique of a semiconductor device. Predetermined wiring is provided on a lead frame for manufacturing a semiconductor device, and the lead frame is sealed in the same manner as the semiconductor device, and the leads are molded to manufacture the semiconductor device.

【0021】この電子部品22,24,33では半導体
チップを収容していないので、封止体6内の配線の引き
回しの自由度が高く複雑な配線を構成することができ
る。
Since no semiconductor chip is housed in the electronic parts 22, 24, 33, the wiring within the sealing body 6 has a high degree of freedom in routing and a complicated wiring can be constructed.

【0022】本実施例の半導体装置11,12,13,
21,23,31,32及び電子部品22,24,33
には、前述した通常のリード4の他に、インナーリード
4aから垂直に延びる垂直配線7aと封止体6の上面に
延在する表面配線7bとからなる中継リード7を取り付
ける。
The semiconductor devices 11, 12, 13 of this embodiment are
21,23,31,32 and electronic parts 22,24,33
In addition to the normal lead 4 described above, a relay lead 7 including a vertical wiring 7a extending vertically from the inner lead 4a and a surface wiring 7b extending on the upper surface of the sealing body 6 is attached.

【0023】この電子装置の電気的接続について、以下
説明する。
The electrical connection of this electronic device will be described below.

【0024】実装基板1に接続されたリード4と中継リ
ード7とによって線路が形成され、この線路に各半導体
チップ2を接続する。電源等の各半導体装置に共通な配
線では並列に接続され、例えば半導体装置12右側、半
導体装置23左側及び半導体装置32右側のように半導
体チップ2とインナーリード4aとがボンディングワイ
ヤ5によって同一の線路に接続される。
A line is formed by the lead 4 and the relay lead 7 connected to the mounting substrate 1, and each semiconductor chip 2 is connected to this line. Wirings common to each semiconductor device such as a power source are connected in parallel, and the semiconductor chip 2 and the inner lead 4a are the same line by the bonding wire 5 like the semiconductor device 12 right side, the semiconductor device 23 left side, and the semiconductor device 32 right side. Connected to.

【0025】個別のデータ入出力等の各半導体装置に固
有の配線では並列に接続されずに、例えば半導体装置3
1右側のように所定の半導体チップ2のみがインナーリ
ード4aとボンディングワイヤ5によって線路に接続さ
れ、他の半導体チップは接続されない。
For example, the semiconductor device 3 is not connected in parallel by the wiring unique to each semiconductor device, such as individual data input / output.
As shown on the right side of FIG. 1, only the predetermined semiconductor chip 2 is connected to the line by the inner lead 4a and the bonding wire 5, and the other semiconductor chips are not connected.

【0026】また半導体装置相互の接続のみで実装基板
には接続されない場合には、例えば半導体装置21右側
と半導体装置31左側との接続のように半導体装置2
1,31相互の接続のみとし、半導体装置11にて該当
する垂直配線をなくし、実装基板1との接続を阻止して
いる。
When the semiconductor devices are connected to each other but not to the mounting board, the semiconductor device 2 is connected, for example, the right side of the semiconductor device 21 and the left side of the semiconductor device 31.
1, 31 are only connected to each other, the corresponding vertical wiring is eliminated in the semiconductor device 11, and the connection with the mounting substrate 1 is blocked.

【0027】このようにして、各半導体装置と実装基板
との或いは半導体装置と他の半導体装置との電気的な接
続を行なう。
In this way, the respective semiconductor devices are electrically connected to the mounting board or the semiconductor devices are electrically connected to other semiconductor devices.

【0028】尚、最上層である3層目の半導体装置に
は、中継リード7を設けない通常の半導体装置32を用
いることも可能であるが、半導体装置31のように中継
リード7を設けこれに抵抗、コンデンサ等の電子部品8
を接続し、例えば時定数の設定等を行なう構成とするこ
とも可能である。
It is possible to use the ordinary semiconductor device 32 without the relay lead 7 as the uppermost third layer semiconductor device, but the relay lead 7 is provided like the semiconductor device 31. Electronic components such as resistors and capacitors 8
It is also possible to connect with and to set the time constant, for example.

【0029】また、前述した中継機能の他に、半導体装
置13及び電子部品33には放熱機能を設けてある。即
ち、半導体装置13には 封止体6外部に露出する伝熱
部材9を設け、前記半導体チップ2がこの伝熱部材9と
熱的に接続されている。
In addition to the relay function described above, the semiconductor device 13 and the electronic component 33 have a heat dissipation function. That is, the semiconductor device 13 is provided with the heat transfer member 9 exposed to the outside of the sealing body 6, and the semiconductor chip 2 is thermally connected to the heat transfer member 9.

【0030】電子部品33には、前記封止体6表面に夫
々露出する受熱部材15と伝熱部材16とを設け、この
受熱部材15と伝熱部材16とを熱的に接続している。
The electronic component 33 is provided with a heat receiving member 15 and a heat transfer member 16 which are exposed on the surface of the sealing body 6, and the heat receiving member 15 and the heat transfer member 16 are thermally connected.

【0031】半導体チップ2を流れる電流によって発生
した熱は、封止体6外部に露出する伝熱部9から受熱部
15に伝えられ、受熱部15と熱的に接続し封止体6上
面に露出した伝熱部材16から空気中に放出される。伝
熱部材9,16、受熱部材15には例えば熱伝達率の高
いアルミニウム、銅等の金属を用いるが、他にヒートパ
イプ等他の伝熱素子を用いてもよい。
The heat generated by the electric current flowing through the semiconductor chip 2 is transferred from the heat transfer portion 9 exposed to the outside of the sealing body 6 to the heat receiving portion 15, and is thermally connected to the heat receiving portion 15 and is provided on the upper surface of the sealing body 6. The heat is transferred from the exposed heat transfer member 16 to the air. The heat transfer members 9 and 16 and the heat receiving member 15 are made of a metal such as aluminum and copper having a high heat transfer coefficient, but other heat transfer elements such as a heat pipe may be used.

【0032】(実施例2)図2に示すのは、本発明の他
の実施例である電子装置を示す縦断面図である。本実施
例では、複数のDRAM(Dynamic Random Access Memo
ry)を積層して接続する場合について記述する。
(Embodiment 2) FIG. 2 is a vertical sectional view showing an electronic device according to another embodiment of the present invention. In this embodiment, a plurality of DRAMs (Dynamic Random Access Memo) are used.
ry) is connected and laminated.

【0033】図中、1は実装基板であり、実装基板1上
に半導体装置41,42,43を積み重ねて多重実装す
る。
In the figure, reference numeral 1 denotes a mounting board, and semiconductor devices 41, 42, 43 are stacked on the mounting board 1 and mounted in multiple layers.

【0034】実装基板1は、ガラスエポキシ系樹脂、セ
ラミック等の絶縁体1aに、銅、アルミニウム等の導体
1bをパターン形成して構成する。
The mounting board 1 is formed by patterning a conductor 1b of copper, aluminum or the like on an insulator 1a of glass epoxy resin, ceramic or the like.

【0035】半導体装置41,42,43は、SOJ
(Small Outline J type lead)型のDRAMであり、
半導体チップ2をタブ3に載置し、半導体チップ2とイ
ンナーリード4aとをボンディングワイヤ5によって接
続し、半導体チップ2,インナーリード4a,ボンディ
ングワイヤ5をエポキシ樹脂等の封止体6によって封止
してある。インナーリード4aは半導体装置の外部端子
であるアウターリード4bと一体になっており、アウタ
ーリード4bにて実装基板1或いは他の半導体装置4
1,42,43に接続する。
The semiconductor devices 41, 42 and 43 are SOJ
(Small Outline J type lead) type DRAM,
The semiconductor chip 2 is placed on the tab 3, the semiconductor chip 2 and the inner lead 4a are connected by a bonding wire 5, and the semiconductor chip 2, the inner lead 4a and the bonding wire 5 are sealed by a sealing body 6 such as an epoxy resin. I am doing it. The inner lead 4a is integrated with the outer lead 4b which is an external terminal of the semiconductor device, and the outer lead 4b is used to mount the mounting substrate 1 or another semiconductor device 4
1, 42, 43.

【0036】本実施例の半導体装置の内、最上層の半導
体装置43を除く他の半導体装置41,42には、通常
設けられているリード4の他に中継リード7を取り付け
る。中継リード7は、テープ状の導体7cを接着層7b
を介して半導体装置41,42,43の外周表面にに接
着し、中継リード7の導体7c一端がアウターリード4
bと電気的に接続し、他端が封止体6の上面に延在す
る。上層の半導体装置43,42のアウターリード4b
は直下の半導体装置42,41の上面に形成した中継リ
ード7に接続し、最下層の半導体装置41のアウターリ
ード4bを実装基板1に接続する。
In the semiconductor devices of this embodiment, other than the uppermost semiconductor device 43, other semiconductor devices 41 and 42 are provided with relay leads 7 in addition to the leads 4 which are normally provided. The relay lead 7 includes a tape-shaped conductor 7c and an adhesive layer 7b.
Is bonded to the outer peripheral surface of the semiconductor device 41, 42, 43 via the outer lead 4 and one end of the conductor 7c of the relay lead 7
It is electrically connected to b and the other end extends to the upper surface of the sealing body 6. Outer leads 4b of the upper semiconductor devices 43, 42
Is connected to the relay lead 7 formed on the upper surfaces of the semiconductor devices 42 and 41 immediately below, and the outer lead 4b of the semiconductor device 41 in the lowermost layer is connected to the mounting substrate 1.

【0037】この電子装置の電気的接続については、電
源等の各半導体装置に共通なリードでは、図2中右側の
ように並列に接続し、各半導体装置の半導体チップ2と
インナーリード4aとがボンディング接続される。
Regarding the electrical connection of this electronic device, the leads common to each semiconductor device, such as a power source, are connected in parallel as shown on the right side in FIG. 2, and the semiconductor chip 2 and the inner lead 4a of each semiconductor device are connected. Bonded and connected.

【0038】半導体装置2の個別のデータ入出力等の各
半導体装置に固有の配線では、並列に接続せずに、本実
施例ではリードの内で通常半導体チップと接続されない
空きピンと呼ばれているリードを利用してこれら固有の
配線の接続を行ない実装基板と接続する。例えば半導体
装置22のみを接続する場合には、図2中左側に示すよ
うに、半導体装置42では、空きピンとなっており通常
はワイヤボンディングを行なわないインナーリード4a
にボンディング接続し、他の半導体装置41,43にて
はリード4を空きピンとしてボンディング接続を行なわ
ない。これによって他の半導体装置41の中継リード7
及びリード4を利用して半導体装置42と実装基板1と
を接続する。
The wiring unique to each semiconductor device, such as individual data input / output of the semiconductor device 2, is not connected in parallel, and in this embodiment, is called an empty pin which is not normally connected to the semiconductor chip in the lead. These leads are used to connect these unique wirings to the mounting board. For example, when only the semiconductor device 22 is connected, as shown on the left side in FIG. 2, in the semiconductor device 42, the inner lead 4a which is an empty pin and is not normally wire-bonded.
In the other semiconductor devices 41 and 43, the lead 4 is used as an empty pin and bonding is not performed. As a result, the relay lead 7 of another semiconductor device 41
Also, the semiconductor device 42 and the mounting substrate 1 are connected using the leads 4.

【0039】本実施例では、中継リードを接着し、空き
ピンを利用して従来製品との互換性を維持する方向で構
成した。
In this embodiment, the relay lead is adhered and the empty pin is used to maintain the compatibility with the conventional product.

【0040】また、本実施例では3重に積層したが、よ
り多重の積層を行ない空きピンの数が不足する場合に
は、リードの数を増加させた他のリードフレームを用い
ることによって、より多重の積層が可能となる。
Further, in the present embodiment, three layers are stacked, but if more layers are stacked and the number of vacant pins is insufficient, another lead frame with an increased number of leads is used to improve the stacking. Multiple layers can be stacked.

【0041】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。
As described above, the inventions made by the present inventor are
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

【0042】[0042]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。
The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【0043】(1)本発明によれば、半導体装置に中継
機能をもたせたので、半導体装置の多重実装が可能にな
るという効果がある。
(1) According to the present invention, since the semiconductor device is provided with the relay function, there is an effect that multiple mounting of the semiconductor device becomes possible.

【0044】(2)本発明によれば、半導体装置を多重
実装することにより、実装基板への高密度の実装が可能
になるという効果がある。
(2) According to the present invention, by mounting the semiconductor devices in multiple layers, it is possible to achieve high-density mounting on the mounting substrate.

【0045】(3)本発明によれば、前記効果(2)に
より、装置を小型にすることができるという効果があ
る。
(3) According to the present invention, due to the effect (2), the device can be downsized.

【0046】(4)本発明によれば、前記効果(2)に
より、コネクタ,ケーブルが不用になるという効果があ
る。
(4) According to the present invention, due to the effect (2), there is an effect that the connector and the cable become unnecessary.

【0047】(5)本発明によれば、前記効果(4)に
より、価格が安くなり且つ信頼性が向上するという効果
がある。
(5) According to the present invention, due to the effect (4), the price is reduced and the reliability is improved.

【0048】(6)本発明によれば、前記効果(4)に
より、配線長が減少するので、回路が高速化しかつノイ
ズに強いという効果がある。
(6) According to the present invention, since the wiring length is reduced by the effect (4), there is an effect that the circuit is speeded up and resistant to noise.

【0049】(7)本発明によれば、半導体装置及び電
子部品に放熱機能をもたせたので、多重実装を行なって
も放熱が良好に行なわれるという効果がある。
(7) According to the present invention, since the semiconductor device and the electronic component are provided with the heat radiation function, there is an effect that the heat radiation is performed well even when the multiple mounting is performed.

【0050】(8)本発明によれば、前記効果(7)に
より、電子装置の性能が安定するという効果がある。
(8) According to the present invention, due to the effect (7), the performance of the electronic device is stabilized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例である電子装置を示す縦断面
図である。
FIG. 1 is a vertical sectional view showing an electronic device according to an embodiment of the present invention.

【図2】本発明の他の実施例である電子装置を示す縦断
面図である。
FIG. 2 is a vertical sectional view showing an electronic device according to another embodiment of the present invention.

【符号の説明】 1…実装基板、1a…絶縁体、1b…導体、2…半導体
チップ、3…タブ、4…リード、4a…インナーリー
ド、4b…アウターリード、5…ボンディングワイヤ、
6…封止体、7…中継リード、7a…垂直配線、7b…
表面配線、7c…導体、7d…接着層、8…電子部品、
9,16…伝熱部材、11,12,13,21,23,
31,32,41,42,43…半導体装置、15…受
熱部材、22,24,33…電子部品。
[Explanation of reference numerals] 1 ... Mounting substrate, 1a ... Insulator, 1b ... Conductor, 2 ... Semiconductor chip, 3 ... Tab, 4 ... Lead, 4a ... Inner lead, 4b ... Outer lead, 5 ... Bonding wire,
6 ... Sealing body, 7 ... Relay lead, 7a ... Vertical wiring, 7b ...
Surface wiring, 7c ... conductor, 7d ... adhesive layer, 8 ... electronic component,
9, 16 ... Heat transfer member, 11, 12, 13, 21, 23,
31, 32, 41, 42, 43 ... Semiconductor device, 15 ... Heat receiving member, 22, 24, 33 ... Electronic parts.

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップを封止体に封止し、一端を
封止体内部に収容し他端を封止体外部に延出させたリー
ドを備える半導体装置であって、 一端が前記リードと電気的に接続され他端が封止体表面
に露出する中継リードを設けたことを特徴とする多重実
装用の半導体装置。
1. A semiconductor device comprising a lead in which a semiconductor chip is sealed in a sealing body, one end is housed inside the sealing body, and the other end is extended outside the sealing body, wherein one end is the lead. A semiconductor device for multiple mounting, which is provided with a relay lead electrically connected to the other end of which is exposed on the surface of the sealing body.
【請求項2】 前記中継リードと電気的に接続されるリ
ードが前記半導体チップとも電気的に接続されているこ
とを特徴とする請求項1に記載の多重実装用の半導体装
置。
2. The semiconductor device for multiple mounting according to claim 1, wherein a lead electrically connected to the relay lead is also electrically connected to the semiconductor chip.
【請求項3】 前記中継リードと電気的に接続されるリ
ードが前記半導体チップとは電気的に接続されていない
ことを特徴とする請求項1に記載の多重実装用の半導体
装置。
3. The semiconductor device for multiple mounting according to claim 1, wherein the lead electrically connected to the relay lead is not electrically connected to the semiconductor chip.
【請求項4】 前記封止体外部に露出する伝熱部材を有
し、前記半導体チップがこの伝熱部材と熱的に接続され
ていることを特徴とする請求項1乃至請求項3の何れか
一項に記載の多重実装用の半導体装置。
4. The heat transfer member that is exposed to the outside of the sealing body, and the semiconductor chip is thermally connected to the heat transfer member. A semiconductor device for multiple mounting according to claim 1.
【請求項5】 封止体とリードと中継リードとを有し、
前記リードの一端が封止体内部に収容され他端を前記封
止体外部に延出させ、前記中継リードの一端が前記リー
ドと電気的に接続され他端が封止体表面に露出すること
を特徴とする電子部品。
5. A sealing body, a lead, and a relay lead,
One end of the lead is housed inside the sealing body and the other end is extended to the outside of the sealing body, one end of the relay lead is electrically connected to the lead and the other end is exposed on the surface of the sealing body. An electronic component characterized by.
【請求項6】 前記封止体表面に夫々露出する伝熱部材
と受熱部材とを設け、この伝熱部材と受熱部材とを熱的
に接続したことを特徴とする請求項5に記載の電子部
品。
6. The electronic device according to claim 5, wherein a heat transfer member and a heat receiving member which are respectively exposed on the surface of the sealing body are provided, and the heat transfer member and the heat receiving member are thermally connected to each other. parts.
【請求項7】 半導体チップを封止体に封止し、一端を
封止体内部に収容し他端を封止体外部に延出させたリー
ドを備え、一端が前記リードと電気的に接続され他端が
封止体表面に露出する中継リードを設けた半導体装置を
多重実装したことを特徴とする電子装置。
7. A semiconductor chip is sealed in a sealing body, and one end is housed inside the sealing body and the other end is extended to the outside of the sealing body, and the lead is electrically connected to the lead. An electronic device comprising a plurality of semiconductor devices, each having a relay lead, the other end of which is exposed on the surface of the sealing body.
【請求項8】 半導体チップを封止体に封止し、一端を
封止体内部に収容し他端を封止体外部に延出させたリー
ドを備え、一端が前記リードと電気的に接続され他端が
封止体表面に露出する中継リードを設けた半導体装置
と、 封止体とリードと中継リードとを有し、前記リードの一
端が封止体内部に収容され他端を前記封止体外部に延出
させ、前記中継リードの一端が前記リードと電気的に接
続され他端が封止体表面に露出する電子部品とを多重実
装したことを特徴とする電子装置。
8. A semiconductor chip is sealed in a sealing body, and one end is housed inside the sealing body and the other end is extended to the outside of the sealing body, and a lead is provided, and one end is electrically connected to the lead. A semiconductor device having a relay lead whose other end is exposed on the surface of the sealing body; and a sealing body, a lead, and a relay lead, wherein one end of the lead is housed inside the sealing body and the other end is sealed. An electronic device, comprising: an electronic component, which is extended to the outside of a stopper, and has one end of the relay lead electrically connected to the lead and the other end exposed on the surface of the sealing body.
【請求項9】 前記半導体装置が封止体外部に露出する
伝熱部材を有し、前記半導体チップがこの伝熱部材と熱
的に接続されていることを特徴とする請求項7又は請求
項8に記載の多重実装用の電子装置。
9. The semiconductor device according to claim 7, further comprising a heat transfer member exposed to the outside of the sealing body, and the semiconductor chip being thermally connected to the heat transfer member. 8. An electronic device for multiple mounting according to item 8.
【請求項10】 前記電子部品が前記封止体表面に夫々
露出する伝熱部材と受熱部材とを有し、この伝熱部材と
受熱部材とを熱的に接続されていることを特徴とする請
求項8に記載の多重実装用の電子装置。
10. The electronic component has a heat transfer member and a heat receiving member which are respectively exposed on the surface of the sealing body, and the heat transfer member and the heat receiving member are thermally connected to each other. The electronic device for multiple mounting according to claim 8.
【請求項11】 半導体チップが封止された半導体封止
体の上主面にその半導体チップに電気的に接続する導体
層が設けられ、その導体層に他の半導体封止体のリード
が接続されることを特徴とする多重実装用の半導体装
置。
11. A conductor layer electrically connected to the semiconductor chip is provided on an upper main surface of the semiconductor encapsulant in which the semiconductor chip is encapsulated, and leads of another semiconductor encapsulant are connected to the conductor layer. A semiconductor device for multiple mounting, which is characterized in that
JP7004952A 1995-01-17 1995-01-17 Semiconductor device, electric components, and electric devices for multiple mounting Pending JPH08195474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7004952A JPH08195474A (en) 1995-01-17 1995-01-17 Semiconductor device, electric components, and electric devices for multiple mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7004952A JPH08195474A (en) 1995-01-17 1995-01-17 Semiconductor device, electric components, and electric devices for multiple mounting

Publications (1)

Publication Number Publication Date
JPH08195474A true JPH08195474A (en) 1996-07-30

Family

ID=11597919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7004952A Pending JPH08195474A (en) 1995-01-17 1995-01-17 Semiconductor device, electric components, and electric devices for multiple mounting

Country Status (1)

Country Link
JP (1) JPH08195474A (en)

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