JPH08195437A - Flattening structure for reducing line capacity - Google Patents

Abstract

PURPOSE: To obtain a multilayer metallization structure for reducing line-to-line capacitance. CONSTITUTION: A metal interconnection layer comprises a metal interconnection line, and an improved dielectric layer 16. The dielectric layer 16 comprises a silicon dioxide part 18 and a low permittivity part 20. The low permittivity part 20 has permittivity of 3.5 or less and can include an organic polymer, e.g. 'Teflon AF(R)'. A via hole may extend through the silicon dioxide part 18. The low permittivity part 20 functions to shorten the RC time lag.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to semiconductor processing, and more particularly to reducing line capacitance.

[0002]

2. Description of the Prior Art Many integrated circuits include multiple layers of metallization for interconnection. As device geometries shrink and functional densities increase, reducing RC time constants within multi-layer metallization systems is inevitable. A commonly used dielectric for isolating metal lines from one another is silicon dioxide. Conventional oxide etching is effective for high aspect ratios and via holes. Silicon dioxide also effectively dissipates heat. However, the dielectric constant of silicon dioxide is approximately 3.9. Recently, attempts have been made to replace silicon dioxide with organic polymers having lower dielectric constants. Inorganic compounds have also been used. By using a lower dielectric constant, RC
The delay time is reduced. However, the thermal stability and etchability of organic polymers are inferior to those of silicon dioxide. Sidewall passivation coupling in oxygen plasma is particularly critical for contact and via hole etching.

[0003]

SUMMARY OF THE INVENTION A semiconductor device having a first metal structure and an improved dielectric layer is disclosed. The dielectric layer comprises a silicon dielectric portion overlying and on a first side of the metal structure, and a low dielectric portion on a second side of the metal structure. The low dielectric part has a dielectric constant of less than 3.5. For example, the low dielectric part is made of, for example, Teflon (Tefl).
on: trade name), benzocyclobutene (BCB), polyimide, or parylene (trade name)
And the like. Furthermore, siloxane-spin-on-glass or fluoride glass (f
It can also be composed of an inorganic compound such as fluorinated glass). In one embodiment, the organic polymer portion of the dielectric layer is placed between two metal interconnect lines to sufficiently reduce RC delay time.
At this time, the via holes may extend through the silicon dioxide portion to the metal interconnect line.

An advantage of the present invention is that it provides a multi-layer metallization structure that reduces line-to-line capacitance.

A further advantage of the present invention is to provide a planarized multi-layer metallization structure that reduces RC delay time.

[0006] A further advantage of the present invention is to provide a dielectric layer in a multi-layer metal device that has the advantages of silicon dioxide and reduces RC delay time.

These and other advantages will be apparent to those of ordinary skill in the art by reference to the specification in conjunction with the drawings and claims.

[0008]

DETAILED DESCRIPTION OF THE INVENTION In a multi-layer metal interconnect device, the capacitance can be decomposed into four capacitance sources, as shown in FIG. The capacitance C ₁₂ is a line capacitance between the line 1 and the line 2. C ₁₃ is the interlayer capacitance between line 1 and the line below it, ie line 3. C ₁₄ is the interlayer capacitance between line 1 and the line diagonally below it, ie line 4. C ₁₅ is the line-ground capacitance between line 1 and ground. C ₁₁ is defined as the total capacity. The metal width of each line 1 to 4 is 0.36 μm. The spacing between the lines is also 0.36 μm. The height of the metal lines 1 to 4 is 0.6 μm. The oxide thickness between the metal lines is 0.7 μm. The capacitance simulation was completed for the structure of FIG. 1 using the 0.35 μm Metal 1 design rule. The results are shown in Table I.

[Table 1] As can be seen from Table 1, the line capacitance occupies 85% of the total capacitance of the above example. Of course, the ratio of the capacitance between the lines changes depending on the space between the lines. As the space becomes smaller, the ratio of the line capacity to the total capacity increases. Therefore, reducing line capacitance has a significant impact on the overall RC delay time for a given interconnect line.

The preferred embodiment of the present invention will be described in connection with a multi-layer metallization process. It will be apparent to those skilled in the art that the number of metallizations can be varied and that the present invention is equally applicable to single layer metal devices.

A preferred embodiment of the present invention is shown in FIG. The semiconductor device 10 includes, for example, a transistor, a diode,
And other semiconductor devices known in the art (not shown). Semiconductor device 10 may also include other metal interconnect layers. Insulator layer 12 is formed on the surface of semiconductor device 10 to insulate and separate the structure of semiconductor device 10 from metal interconnect layer 14. Insulator layer 12 may comprise, for example, an oxide such as silicon dioxide. A contact (not shown) can be formed through the insulating layer 12 to connect the metal interconnect layer 14 and the semiconductor device 10. The metal interconnect layer 14 may comprise, for example, an aluminum or titanium-tungsten / aluminum bilayer. Dielectric layer 16 insulates metal interconnect layer 14 from subsequently processed elements such as additional metal interconnect layers (not shown). The dielectric layer 16 includes a silicon dioxide layer 18 and a low dielectric constant layer 20. Low dielectric constant layer 20
May comprise an organic polymer such as Teflon (trademark), BCB, Parylene (trademark) or other material having a dielectric constant of less than 3. Teflon AF is used in the embodiment. Layer 20 is located in the area of device 10 that has the greatest effect on capacitance. Since the line capacitance greatly contributes to the total capacitance, a low dielectric constant material such as Teflon AF is provided between the metal lines 30 to 34 of the metal interconnect layer 14. Silicon dioxide 18 is used elsewhere. The oxide layer 22 covers the dielectric layer 16 to protect the surface of the organic polymer layer 20.
The via hole 24 is formed through the silicon dioxide layer 18,
It extends to the metal interconnect layer 14.

Having a mixed organic polymer / silicon dioxide dielectric layer has several advantages. First, high aspect ratio etching, such as that required to form contact via holes, is difficult to achieve with organic polymers. Conversely, such etching is well known for silicon dioxide. Second, high currents flowing through metal lines can cause rises in the metal lines at certain locations. This is known as hillock / void formation.
Silicon dioxide suppresses hillock / void formation much more than organic polymers. Third, the low dielectric constant material 20
Has a low dielectric constant compared to silicon dioxide, so the line capacitance is reduced. Fourth, the heat generated in the metal line can be dissipated through silicon dioxide more easily than through organic polymers. Fifth, the surface of silicon dioxide is planarized for lithographic patterning. Finally, the silicon dioxide layer provides a barrier to mechanical instability of organic polymers. Thus, the benefits of silicon dioxide are combined with the benefits of reduced line capacitance due to the low dielectric constant layer 20.

Forming the preferred embodiment of the present invention into the structure shown in FIG. 3 will now be discussed. FIG. 2 illustrates semiconductor device 10 after forming transistors and other device elements (not shown). One or more interconnect layers may also be formed. In the preferred embodiment, no such interconnect layer was formed. An insulator layer 12 is formed on the surface of the semiconductor device 10.

Referring to FIG. 4, a metal layer is deposited and etched to form metal interconnect layer 14. For simplicity, FIG. 5 shows metal lines 30, 32.
3 shows a metal interconnect layer 14 with. However, it will be apparent to those skilled in the art that many other interconnect lines, as well as other geometries, may form part of the metal interconnect layer 14. The metal interconnect layer 14 has a thickness of approximately 0.5-2.0 μm. Next, a layer of silicon dioxide 18 is deposited over the oxide layer 12 and the metal interconnect layer 14. The silicon dioxide layer 18 has a thickness of approximately 1.0-3.0 μm. Silicon dioxide layer 18 may be planarized according to techniques well known in the art. For example, chemical mechanical polishing or sacrificial etch back method.
-Bath process) can be used.

A portion of the silicon dioxide layer 18 is shown in FIG. 5 of the metal interconnect layer 14, eg, metal line 3.
Etched away between metal lines such as 0, 32 and 34. It should be noted that the portion of the silicon dioxide layer 18 that is removed is the site that has the greatest effect on mutual capacitance. Thus, the portion to be removed can change depending on the metal interconnect geometry. It should also be noted that the insulator layer 12 remains on the entire surface of the semiconductor device 10.

Referring to FIG. 6, the low dielectric constant layer 20.
Is applied to the entire surface of the structure to a thickness of approximately 1.0 to 5.0 μm. The layer 20 is, for example, Teflon, B
It may comprise an organic polymer such as CB, polyimide, perfluorinated polymer or parylene. This layer 20 can also be formed of an inorganic compound such as siloxane spin-on glass or fluoride glass. Teflon AF is used in the preferred embodiment. After deposition, layer 20 may reflow to planarize the structure. Layer 20 is then etched back so that no material of layer 20 remains over the surface of silicon dioxide layer 18, as shown in FIG. Layer 2
Methods of etching 0 are well known in the art. For example, oxygen plasma etching with a small amount of CF ₄ gas may be used. The combination of layers 18 and 20 results in dielectric layer 16
To form.

Referring to FIG. 8, a layer of oxide 22 is deposited over the surface of the structure. Oxide layer 22 functions to protect layer 20 during subsequent processing steps. Referring also to FIG. 8, contact via holes 24 are patterned and etched through silicon dioxide layer 18 to metal interconnect layer 14 in accordance with the prior art. One advantage of the present invention is that the shorter RC
It is possible to use conventional contact / via hole etching while achieving the delay time. This is due to the fact that the organic polymer 20 is used in a more critical and appropriate location for the RC time constant, while leaving the silicon dioxide layer 18 wherever the via hole is desired.
Finally, a metal layer 42 is deposited to fill the via hole 24.

After forming the structure of FIG. 8, the process can be repeated to form additional metal interconnect layers, as shown in FIG. Generally, three to four such metal interconnect layers can be formed. However, the invention is equally applicable to devices having more than four layers of interconnects, as well as devices having only single or double layer metal interconnects.

Although the present invention has been described with reference to exemplary embodiments, this description is not meant to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. Accordingly, the claims are intended to cover any such variation or embodiment.

With respect to the above description, the following items will be further disclosed. (1) (a) a first metal structure, and (b) a silicon dielectric part covering the metal structure on the first and second sides of the metal structure, and a low side of the second side of the metal structure. A semiconductor device comprising: a dielectric layer having a dielectric portion, wherein the low dielectric portion has a dielectric constant of less than 3.9. (2) The device according to the item 1, wherein the low dielectric portion is made of an organic polymer. (3) The device according to item 2, wherein the organic polymer is Teflon AF.

(4) In the device according to the second aspect, the organic polymer is a material selected from Teflon, benzocyclobutene, perylene, polyimide, perfluorinated polymers and derivatives thereof. apparatus. (5) The device according to the item (2), wherein the low-dielectric part comprises an inorganic compound having a dielectric constant of less than 3.9. (6) In the device according to the fifth aspect, the inorganic compound is a low dielectric constant siloxane spin-on glass (siloxan).
e spin on glass). (7) In the device according to the fifth aspect, the inorganic compound is a low dielectric constant fluorinated glass.
device). (8) The device according to item 1, further comprising a second metal structure, wherein the low dielectric part of the dielectric layer is the first
And laterally between the second metal structure and
The device of claim 1, wherein the silicon dioxide portion is also located over the second metal structure.

(9) In the device according to the eighth aspect, (a) a third structure which is located above the first metal structure and is separated from the first metal structure by the silicon dioxide portion. (B) a fourth metal structure located above the second metal structure and separated from the second metal structure by the silicon dioxide portion; ) A layer of an organic polymer located between the third and fourth metal structures, further comprising: (10) The device according to claim 1, further comprising a via hole extending to the first metal structure through the silicon dioxide portion. (11) The device of claim 1, wherein the first metal structure comprises metal interconnect lines.

(12) (a) a first interconnect layer, the first interconnect layer comprising: (i) first and second metal interconnect lines; and (ii) the first and second interconnect layers. A first organic polymer layer laterally positioned between the second metal interconnect lines and having a dielectric constant of less than 3.9; and (iii) covering the first and second metal interconnect lines. A first layer of silicon dioxide located thereon, and a multi-layer metallization interconnect. (13) The interconnect of claim 12, further comprising (a) a second interconnect layer, wherein the second interconnect layer comprises (i) the first and second metal interconnect lines. Third and fourth metal interconnect lines located respectively above, (ii) a second organic polymer layer laterally located between said third and fourth metal interconnect lines, and (iii)
A second layer of silicon dioxide overlying the third and fourth metal interconnect lines. (14) The interconnect of claim 13, wherein: (a) a first via hole extending from the third metal interconnect line to the first metal interconnect line through the first layer of silicon dioxide. And (b) a second via hole extending from the fourth metal interconnect line to the second metal interconnect line through the first layer of silicon dioxide. Interconnection.

(15) In the interconnection described in item 12,
The interconnect, wherein the organic polymer comprises Teflon AF. (16) In the interconnect according to item 12, the organic polymer is a material selected from Teflon, benzocyclobutene, parylene, polyimide, a perfluorinated polymer and derivatives thereof. .

(17) (a) A first metal layer is formed on the surface of the semiconductor device.
And (b) etching the first metal layer to form first and second metal structures, and (c) the first and second metal structures. A body and a first layer of silicon dioxide over the surface of the semiconductor device; and (d) the first silicon dioxide located between the first and second metal structures. Etching a first portion of the layer, (e) depositing a first layer of a low-k material having a dielectric constant of less than 3.9, and (f) the first silicon dioxide layer. Etching the first layer of organic polymer so that no organic polymer remains on the surface of the multilayer interconnect. (18) The method according to the item 17, wherein the low dielectric constant material comprises an organic polymer.

(19) In the method described in paragraph 18, (a)
Depositing an oxide layer over the first layer of organic polymer and the silicon dioxide layer, and (b) depositing a second layer of metal over the oxide layer, c) the second
Etching the metal layer to form third and fourth metal structures. (20) The method of claim 19, wherein (a) depositing a second layer of silicon dioxide, and (b) a silicon dioxide layer between the third and fourth metal structures. Etching the second portion of the second layer, and (c) the first portion.
Filling said portion with a second layer of organic polymer. (21) The method according to the item 18, wherein the organic polymer comprises a material selected from the group consisting of Teflon AF, BCB, and parylene.

(22) The method according to the seventeenth item, wherein the low dielectric constant material comprises an inorganic compound. (23) The method according to the item 22, wherein the inorganic compound is a siloxane spin-on glass having a low dielectric constant. (24) The method according to the item 22, wherein the inorganic compound is fluorinated glass having a low dielectric constant.

(25) The metal interconnect layer comprises the metal interconnect lines (30, 32 and 34) and the improved dielectric layer 16. The dielectric layer 16 includes a silicon dioxide portion 18 and a low dielectric constant portion 20. Low dielectric constant part 20
Has a dielectric constant of less than 3.5 and may comprise an organic polymer such as Teflon AF. The via hole 24 may extend through the silicon dioxide portion 18. Low dielectric constant part 20
Functions to reduce RC delay.

[Brief description of drawings]

FIG. 1 is a block diagram of a multi-layer interconnection system.

FIG. 2 is a cross-sectional view of a multilayer interconnect device according to a preferred embodiment of the present invention.

FIG. 3 is a cross-sectional view of a multilayer interconnect device according to a preferred embodiment of the present invention at various stages of manufacture.

FIG. 4 is a cross-sectional view of a multilayer interconnect device according to the preferred embodiment of the present invention at various stages of manufacture.

FIG. 5 is a cross-sectional view of a multi-layer interconnect device according to a preferred embodiment of the present invention at various stages of manufacture.

FIG. 6 is a cross-sectional view of a multilayer interconnect device according to a preferred embodiment of the present invention at various stages of manufacture.

FIG. 7 is a cross-sectional view of a multi-layer interconnect device according to a preferred embodiment of the present invention at various stages of manufacture.

FIG. 8 is a cross-sectional view of a multilayer interconnect device according to the preferred embodiment of the present invention at various stages of manufacture.

FIG. 9 is a cross-sectional view of a multilayer interconnect device according to the preferred embodiment of the present invention at various stages of manufacture.

[Explanation of symbols]

 16 Dielectric Layer 18 Silicon Dioxide Part 20 Low Dielectric Constant Part 24 Via Hole 30, 32, 34 Metal Interconnect Line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/04 D

Claims (2)

[Claims] 1. A first metal structure; (b) a silicon dielectric portion covering the first side of the metal structure on the first side of the metal structure; and a low side of the second side of the metal structure. A semiconductor device comprising: a dielectric layer having a dielectric portion, wherein the low dielectric portion has a dielectric constant of less than 3.9. 2. (a) depositing a first layer of metal on the surface of the semiconductor device; and (b) etching the first metal layer to form first and second metal layers.
(C) depositing a first layer of silicon dioxide over the entire surface of the first and second metal structures and the semiconductor device; and (d) Etching a first portion of the first silicon dioxide layer located between the first and second metal structures; and (e) a low dielectric constant material having a dielectric constant less than 3.9. First of
And (f) etching the first layer of organic polymer such that no organic polymer remains on the surface of the first silicon dioxide layer. Method for forming a featured multi-layer interconnect.