JPH08195038A - Recording medium, data recording device and data reproducing device - Google Patents

Abstract

PURPOSE: To obtain a recording medium capable of reducing the scale of hardware used for recording, reproducing, etc., of data while improving error resistance. CONSTITUTION: The sector of a sector structure consists of at least a first region and second region. The first region includes at least CRC codes relating to the data described above and the second region includes at least EDC codes relating to the data. The size of the first region is the size exactly dividable by the first generating polynomial P0(x) in the Galois field of GF(2<n> ) formed by the first generating polynomial P0(x) and the size of the second region is the size exactly dividable by the second generating polynomial P1(x) in the Galois field of GF(2<2n> ) formed by the second generating polynomial P1(x). The first generating polynomial P0(x) and the second generating polynomial P1(x) have a factor relation as shown below: P0(x)=x<16> +x<15> +x<2> +1: P1(x)=(x<16> +x<15> + x<2> +1)*(x<16> +x<2> +x+1).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording medium in which data is recorded by a sector structure suitable for recording data,
The present invention relates to a recording device that records data on the recording medium and a reproducing device that reproduces data from the recording medium.

[0002]

2. Description of the Related Art A method of dividing data into predetermined units and recording / transmitting it in a packet structure or a sector structure has been widely put into practical use. For example, in Compact Disc (trademark),
Digital audio data has a sector structure of a predetermined length, is subjected to error correction (ECC) processing, and is recorded on an optical disk. ISO13818-
2 (MPEG2 system) also employs this method, and PES (Packetized Elementary Stream)
Transmission and recording / reproduction of data in units called packets have been proposed. In the PES packet system, in order to improve error resistance between transmission and reception, it is proposed not only to perform ECC processing for each packet but also to write a code for detecting an error in the packet. This code is CRC
It is called a (Cyclic Redundancy Check) code and is written as 2-byte (16-bit) data in the header of the PES packet. CRC code is a kind of checksum,
On the sending side, a predetermined value (usually set to 0) and the data of the portion to be inspected are calculated by a predetermined generator polynomial, and the result (CRC code) and the data are transmitted. On the receiving side, the received CRC code and data are divided by the generator polynomial. If the transmission is error-free and complete, the solution divided by the generator polynomial will always have the same predetermined value as the sender. If the specified value on the sending side is 0, the solution is 0,
That is, it is divisible. Therefore, it is possible to detect an error by checking whether or not it is a predetermined value. The general formula of this generator polynomial is defined by the following formula.

P (x) = x ⁿ + f _n-1 x ^n-1 + ... + f ₂ x ² + f ₁ x ¹ + f ₀ ... (1)

That is, Equation 1 is a Galois field G which is a generator polynomial.
The highest order of x that is F (2 ^x ) and has nonzero coefficients is called the polynomial order. The generator polynomial is also called an irreducible polynomial. A circuit that realizes this generator polynomial is configured as a circuit having an exclusive OR in bits and a register.

FIG. 10 shows the ISO 13818-2 (M
It is a circuit example on the decoder side of the CRC code exemplified by PEG2). This circuit uses a 32nd-order generator polynomial
The bit CRC code is decoded, and is composed of 32 registers Z (0) to Z (31) and a plurality of adders (+). The generator polynomial of the CRC code corresponding to this circuit is expressed by the following equation.

P3 (x) = x ³² + x ²⁶ + x ²³ + x ²² + x ¹⁶ + x ¹² + x ¹¹ + x ¹⁰ + x ⁸ + x ⁷ + x ⁵ + x ⁴ + x ² + x + 1 ) (2)

As described above, the CR obtained by the generator polynomial
A method of inserting a C code together with data into a packet or a header of a sector to improve error resilience is well known and widely practiced. The generator polynomial can be defined relatively freely, and the number of terms and the like can be appropriately determined in consideration of the scale of hardware and the like.

[0008]

The CRC code described above is not always satisfactory in error resilience, because each bit of all data in a sector is processed by the same generator polynomial. . Especially for important headers, there is a demand to increase the accuracy of error detection. Therefore, it is considered effective from the viewpoint of error resilience to set the sector to at least two areas, generate a CRC code by a different generating polynomial for each data in each area, and detect an error in each area. For particularly important areas, by overlapping the areas and adding CRC codes with different generator polynomials,
Strong error resilience can be expected.

However, by simply defining two generator polynomials, the scale of hardware is simply doubled, and the circuit is complicated.

An object of the present invention is to provide a recording medium capable of reducing the hardware used for recording and reproducing data while improving the error resistance. It is another object of the present invention to provide a recording device that records data on such a recording medium and a reproducing device that can read the data from the recording medium on which the data is recorded.

[0011]

A recording medium of the present invention is a recording medium capable of recording time-divided data by using a sector structure or reading the recorded data. Of sectors comprises at least a first area and a second area, the first area including at least a CRC code for the data, the second area including at least an EDC code for the data, and the size of the first area. Is GF (2 ⁿ ) formed by the first generator polynomial P0 (x)
Is a size divisible by the first generator polynomial P0 (x) in the Galois field of, and the size of the second region is the Galois of GF (2 ²ⁿ ) formed by the second generator polynomial P1 (x). The size is divisible by the second generator polynomial P1 (x) in the field,
The first generator polynomial and the second generator polynomial have a factor relationship.

[0012] Preferably, the first generator polynomial P0 (x) is represented by the following ^{formula, P0 (x) = x 16} + x 15 + x 2 +1 second generator polynomial is represented by the following formula It P1 (x) = (x ¹⁶ + x ¹⁵ + x ² +1) * (x ¹⁶ + x ² + x + 1)

Preferably, the first area contains at least header information, and the second area contains header information and data. More preferably, the CRC code is recorded at the beginning of the first area and the EDC code is recorded at the end of the second area.

Further, according to the present invention, there is provided a recording medium capable of recording time-divided data in a sector structure and reading the data, wherein the sector having a sector structure is at least the first sector.
And a second region, the first region includes at least a CRC code for data, the second region includes at least an EDC code for data, and the size of the first region is the first generator polynomial. The size is divisible by P0 (x), the size of the second region is divisible by the second generator polynomial P1 (x), and the first generator polynomial and the second generator polynomial are factors. A related recording medium is provided.

Further, according to the present invention, the time-division data is recorded as a sector structure and the data can be read out, and the sector of the sector structure has at least a first area and a second area. The first region contains at least a CRC code for the data, the second region contains at least an EDC code for the data, and the size of the first region is divisible by the first generator polynomial P0 (x). The size of the second region is a size divisible by the first generator polynomial and the second generator polynomial P1 (x), and the first generator polynomial and the second generator polynomial are factors. A recording medium having the above relationship is provided.

Further, according to the present invention, there is provided a data recording device having the above recording medium and a write signal processing circuit for recording data on the recording medium.

Further according to the present invention, the above recording medium,
A data reproducing apparatus having a read signal processing circuit for reading data from the recording medium is provided.

[0018]

The recording medium of the present invention uses a sector structure for time-divided data. At least the first sector of the sector structure
Area and a second area, the first area includes at least a CRC code for the data, and the second area includes at least an EDC code for the data. The size of the first region is GF formed by the first generator polynomial P0 (x).
In the Galois field of (2 ⁿ ), the first generator polynomial P0 (x)
The size of the second region is divisible by the second generator polynomial P1 (x) in the Galois field of GF (2 ²ⁿ ) formed by the second generator polynomial P1 (x). That's it. Since the first generator polynomial and the second generator polynomial have a factor relationship, the hardware circuit in decoding becomes simple. In addition, CRC code and EDC code are used to maintain error resilience.

[0019]

Embodiments of the recording medium, recording apparatus and reproducing apparatus of the present invention will be described below. FIG. 1 is a block diagram of a data recording device, and FIG. 2 is a block diagram of a data reproducing device. First, the sector structure of the recording medium of the present invention will be described with reference to FIG. 3, and then the recording device of FIG. 1 and the reproducing device of FIG. 2 will be described.

Principle of Sector Structure In the present embodiment, the data recording medium is, for example, a medium such as a compact disc, a magneto-optical disc, a hard disc, which can record and store data. With the data recording device shown in FIG. 3, video data, audio data, character data or a plurality of data of them, data produced on a computer and additional information are variable data as user data having a sector structure as shown in FIG. Recorded at rate. FIG. 3 is a diagram illustrating a sector structure as an embodiment of the present invention. In FIG. 3, each sector is composed of a synchronization pattern (SYNC), header, user data, and EDC code. The synchronization pattern is attached at the beginning of each sector with 4 bytes, so that the beginning of the sector can be detected.

Subsequently, the sector header shown in FIG. 4 is attached with 16 bytes. In Fig. 4, in Sector Hezda,
It has a folded structure every 4 bytes. First, the C
2 bytes of RC code is calculated by generator polynomial,
Is added. Next, copyright information: Copyright
(1 byte), Layer information: Layer (1 byte), Reserved: Reserved (1 byte), Sector address: Address
(3 bytes), track number: Track Number (2 bytes), application code: Application Code (1
Byte) and application data: Application
Data (5 bytes) is described. These 14 bytes are collectively called a subcode. Copyright information: "Copyright" is a code for permitting or prohibiting duplication. Whether or not duplication is permitted at all, copying is possible only for one generation, duplication freedom, etc. are identified by the code. Layer information: Layer indicates a layer number when the disk allows a multilayer structure. Reservation: Reserved is available to meet future standards changes.
It is a free byte. Sector address: Address is the serial number of the sector on this disk. When the disk has a multi-layer structure, the serial number of the sector in each layer is shown. The track number: Track Number is the serial number of the track in this disk, and in the case of the multilayer structure as described above, it indicates the serial number of the track in each layer. Information about user data is described in application code: Application Code and application data: Application Data. Therefore, it is possible to freely define and write character information other than images and sounds for each sector as user data.

Referring again to FIG. 3, in the sector structure of the embodiment of the present invention, the subcode is followed by the user data. The size of user data in one sector is 20
Selected as 48 bytes. Further, in the embodiment of the present invention, the CRC code by different generator polynomials is calculated in 4 bytes for the header and the user data after the user data, and is added subsequently to the user data. For convenience of explanation, the CRC code obtained from only the header and the CRC code obtained from the user data are E
It is called a DC (Error Detection Code) code.
Therefore, for header, CRC code (2 bytes) and E
The DC code (4 bytes) enables duplicate error detection. The relationship between the CRC code and the EDC code will be described later in detail. For such sectors,
Parity by Reed-Solomon code,
That is, an ECC (Error Correction Code) is added in 308 bytes. Therefore, 23 for one sector as a whole
Recording data of 80 bytes is recorded, stored, and reproduced on the data recording medium.

Relationship between CRC Code and EDC Code Next, the relationship between the CRC code and the EDC code of the present invention will be described. The CRC code has a length of 16 bits (2 bytes) and is defined as follows. That is, a code string (LSB First for each byte) including a code obtained by inverting the recorded CRC code and a subcode is divisible by the following generator polynomial which is a Galois field generator polynomial of GF (2 ¹⁶ ).

P (x) = x ¹⁶ + x ¹⁵ + x ² +1 (3)

The CRC code can be generated by a CRC generating circuit as shown in FIG. In FIG.
Each of R1 to R16 is a 1-bit register, and the registers R3 to R15 form a FIFO. Code 30
Reference numerals 1-303 denote exclusive OR adders. First, when all the subcode data is ready, registers R16 to R16
All 1s are loaded with 0s. After that, the most significant bit of the last byte of the subcode is sequentially input to the input terminal 304. Every time 1-bit data is input, the data in the registers R16 to R1 are shifted rightward in synchronization with the bit clock signal. Input data and register R
The output of 1 is added by the exclusive OR adder 303, the result is directly input to the register R16, and the output of the register R3 and the output of the register R3 are output by the exclusive OR adder 302 and the exclusive OR adder 301. The output of the register R16 and addition are performed. The outputs of the exclusive OR adder 302 and the exclusive OR adder 301 are input to the register R2 and the register R15, respectively.

When all the bits up to the least significant bit of the first subcode data have been input, the registers R1 to R are registered.
The value remaining in 16 is set to 2 bytes (16 bits) of the CRC code from the corresponding expression shown below, and the bit-inverted value is recorded in the CRC field.

Byte 0: (Bit7, Bit6 ---- Bit0) = (R9, R10 ---- R16) Byte 1: (Bit7, Bit6 ---- Bit0) = (R1, R2 ---- R8 ) ・ ・ (4)

Byte 0 is from register R9 to register R16
It corresponds to the bit in each register. Byte 1 corresponds to the bits in each of the registers R1 to R8.

FIGS. 6A and 6B show examples of specific numerical values. The value of register R9 to register R16 is [11100100]
Therefore, the values of registers R16 to R9 are [0
0100111]), Byte 0 is [11100100], and the CRC field is [00011011]. Since the values of registers R1 to R8 are [00001010], Byte 1 is [00001
010], and the CRC field is [11110101].

2-byte CRC recorded as described above
The code can be inspected by the check circuit shown in the block diagram of FIG. 7 at the time of decoding. In the figure, R1 to R1
6 is a 1-bit register, and registers R3 to R15
The shift register is configured as a whole. Reference numerals 311 to 313
Is an exclusive OR adder. First, after extracting the CRC code from the sector of the recording medium and inverting the bit,
Register R16 to register R1 according to the following correspondence equation
Substitute each bit into.

(R9, R10 --- R16) = (Bit 7 ----- Bit 0): CRC Byte 0 (R1, R2 --- R8) = (Bit 7 ----- Bit 0): CRC Byte 1 (5)

After that, data is input from the input terminal 314 in order from the least significant bit of the first byte of the subcode.
Each time one bit is input, the data in the registers R16 to R1 are shifted leftward in synchronization with the bit clock signal. The overflow from the register R16 is caused by the exclusive OR adder 313, the exclusive OR adder 312, and the exclusive OR adder 311 to input data from the input terminal 314, output from the register R2, and register R15. Is added to the output of each. The outputs of the exclusive OR adder 313, the exclusive OR adder 312, and the exclusive OR adder 311 are input to the register R1, the register R3, and the register R16, respectively. When the input to the most significant bit of the last subcode data is completed and all the bits in all registers are 0, that is, when the bits are divided by the above generator polynomial, there is no error.

The EDC code has a length of 32 bits and is defined by the following equation.

P (x) = (x ¹⁶ + x ¹⁵ + x ² +1) × (x ¹⁶ + x ² + x + 1) (6)

That is, for the code, subcode, and user data obtained by inverting the recorded CRC code,
When the processing by the generator polynomial of Expression 6 is performed and the input of all the bits up to the lowest bit of all data is completed, the values remaining in the registers R1 to R32 are bit-inverted by eight, as in the case of the CRC code. The data thus obtained is 4-byte data of EDC code. This 4-byte EDC code is shown in FIG.
As shown in, the data is recorded following the user data in the sector.

On the decoding side, with respect to the code sequence obtained by inverting the CRC code, the subcode, the user data, and the code sequence inverting the EDC code recorded on the recording medium (LSB First for each byte), The check is performed by the EDC code on the decoding side corresponding to the generator polynomial of Expression 6 above. Normally, the initial value of 0 is used on the code side, so if there is no remainder in the division result, it can be determined that there was no error. Therefore, for subcode, error detection is performed by using both CRC code and EDC code, and for user data,
Error detection is performed only by the EDC code. As a result, even if the EDC code indicates an error, if the CRC code does not indicate an error, it can be determined that the subcode has no error. In this case, the application code and the application data defined by the sub-code allow the decoder device to respond differently depending on the importance of the application. Also, Equation 6
The first term on the right side of is the same as the above-mentioned CRC code generator polynomial, and has a factor relationship.

FIG. 8 shows the relationship between the CRC code, EDC code and sector configuration. In FIG. 8, the total code string of the CRC code and the sub-code forming the header part is set to a value divisible by the above-mentioned CRC code generating polynomial (Equation 1). Next, the total code string of the header, the user data, and the code obtained by inverting the bit of the EDC code is set to a value divisible by the generator polynomial (Equation 2) of the EDC code. As a result, the CRC code generator polynomial (Equation 1) has a factor relationship with the EDC code generator polynomial (Equation 2). Therefore, the total code string of the user data and the code obtained by bit-reversing the EDC code has a relationship divisible by the generator polynomial (Equation 2) of the EDC code. Due to this property, the decoder device can be selected from a decoder that uses both the 16-bit check register and the 32-bit check register for checking, and a decoder that uses only the 16-bit check register. In the former case, the speed of inspection can be increased, while in the latter case, the circuit scale can be reduced. Therefore, either configuration can be selected at any time according to the scale and cost of the decoder.

Data Recording Device In FIG. 1, reference numeral 1 indicates the entire data recording device. That is, there is shown a block diagram of an embodiment of a data recording apparatus for realizing the data recording format according to the present invention. The data recording apparatus 1 of this embodiment multiplexes pre-produced video data, audio data, character data, or a program composed of a plurality of data or data produced on a computer and adds additional information. The data is recorded on the data recording medium 19 having the above-mentioned configuration.

In this data recording device 1, the master data transmission device 2 receives a command from the control device 20, and outputs the pre-produced video data, audio data and character data respectively to the video encoder 5, audio encoder 6 and character encoder 7. Send to. The master data transmission device 2 is composed of, for example, a commercial video tape player. Further, the master data transmission device 2 transmits the time code information to the time code information switching circuit 10 together with the video data, the audio data and the character data, when the time code information exists.

The computer 3 receives the command from the control device 20, and sends the computer data to be recorded on the data recording medium 19 to the computer interface 4. The computer interface 4 converts the electrical characteristics, the signal format, the data format, etc. of the information sent from the computer 3 and sends the information having the same contents to the multiplexing circuit 8.

The video encoder 5 converts the video data sent from the master data sending device 2 to ISO1117.
2-2 (MPEG1 Video) or ISO13818-
2 (MPEG2 Video) and coded according to the coding procedure and sent to the multiplexing circuit 8. Also, the entry point information indicating the position of the I picture data, the picture header information indicating the position of the picture header, the picture type information indicating the type of the picture, and the temporal reference in which the temporal reference number is recorded are sent to the subcode encoder 11.

The audio encoder 6 uses the audio data sent from the master data sending device 2 as it is or according to ISO11172-3 (MPEG1 Audio).
), ISO13818-3 (MPEG2 Audio) or MD (Minidisc trademark) standard ATRAC
(Adaptive Transform Acousitc Coding, trademark), and the encoded procedure is transmitted to the multiplexing circuit 8. The character encoder 7 sends the character data sent from the master data sending device 2 to the multiplexing circuit 8 as it is or after performing run length compression. The characters are subtitle data and the like.

The multiplexing circuit 8 sends the data sent from the video encoder 5, the audio encoder 6, the character encoder 7 and the computer interface 4 to the IS.
O11172-1 (MPEG1 System) or ISO1
Multiplexing is performed according to the regulations of 3818-1 (MPEG2 System). At this time, the control device 20 sends the data recording medium 1
In response to an instruction of the processing unit of data that can be read from 9 or written in the data recording medium 19, that is, the size of user data for one sector, multiplexing is performed so that one packet does not span user data of a plurality of sectors. At the same time, the multiplexed data is sent to the subcode adding circuit 15. At the same time, a sector boundary signal for notifying a sector boundary is sent to the subcode adding circuit 15.

The time code information generator 9 is a control device 20.
The time code information is generated in response to the command from. The time code information switching circuit 10 selects the time code information sent from the master data sending device 2 and the time code information sent from the time code information generator 9, and sends it to the sub-code encoder 11. However, when the time code information is sent from the master data sending device 2, the time code information is sent, and when there is no time code information sent from the master data sending device 2, it is sent from the time code information generator 9. Select the time code information that will be sent to you.

The sub-code encoder 11 is a control device 20.
The sector number information and other additional information sent from the encoder are encoded into a predetermined format, and the CRC encoder 12
Send to. Here, the other additional information is the copyright information, the layer information, the track number, the application code, and the application data shown in FIG.

The CRC encoder 12 calculates a CRC code for the subcode information sent from the subcode encoder 11 by the above-described generator polynomial, adds the CRC code to the subcode information, and sends it to the synchronization pattern adding circuit 13. Send out. The sync pattern adding circuit 13 CRs a predetermined sync pattern, that is, a 4-byte sync pattern in this embodiment.
It is added before the C data. Sync pattern, CRC
The code and subcode data are sent to the subcode buffer 14. The sync pattern, the CRC code, and the subcode data from the subcode buffer 14 are added to the user data from the multiplexing circuit 8 by the subcode adding circuit 15. The EDC encoder 16 calculates the EDC code from the CRC code, the subcode data, and the user data from the subcode adding circuit 15 by the above-described generator polynomial, adds the EDC data to the user data, and E
It is sent to the CC encoder 17. ECC encoder 17
Calculates the parity calculated by the Reed-Solomon code, that is, ECC, on the multiplexed data sent from the EDC encoder 16, adds it to the multiplexed data, and sends it to the writing circuit 18. Further, the sector boundary signal is received from the EDC encoder 16, and the sector boundary signal is sent to the writing circuit 18 so as to correspond to the sector boundary of the data to which the ECC is added.

The writing device 18 uses a modulation circuit (not shown) to convert the data sent from the ECC encoder 17 into
Modulation is performed so that the signal format can be recorded on the data recording medium 19. The writing device 18 electrically, magnetically, optically, and physically records the modulated signal on the data recording medium 19. In particular, an optical disc is suitable.

Here, after subcode data is added to the multiplexed data, ECC is calculated for the whole and parity is added. However, ECC is calculated for the multiplexed data,
The same thing can be done by adding subcode data after adding parity.

The control device 20 is controlled by the master data transmission device 2 and the computer 3 in accordance with the editing command from the user.
To the multiplexing circuit 8 and to instruct the multiplexing circuit 8 on the read / write processing unit of the data recording medium 19, that is, the size of the sector, and the time code information generator 9
Send a time code generation command to. Furthermore, the control device 20 sends a switching command to the time code switching circuit 10 and also receives a command regarding copyright management, a layer information, a track number, and an application identification number from the user, and the sub code encoder 11 receives sector number information. The copyright management information, layer information, track number, and application identification number are transmitted.

Description of Operation of Embodiment of Data Recording Device In the above configuration, the control device 20 first issues a data transmission command to the master data transmission device 2 or the computer 3 according to an editing command from the user. Also, the size of the sector is instructed to the multiplexing circuit 8. Also, sector number information and copyright management information for recording in the subcode,
The layer information, the track number, and the application identification number are generated and supplied to the subcode encoder 11. When there is no time code information sent from the master data sending device 2, the control device 20 gives an instruction to the time code information generator 9 according to a command from the user to generate the time code information.

The subcode encoder 11 creates subcode data according to the subcode structure shown in FIG.
It is sent to the RC encoder 12. CRC encoder 12
Calculates the CRC code of the data received from the subcode encoder 11, adds the CRC data immediately before the subcode data, and sends it to the synchronization pattern adding circuit 13. The sync pattern adding circuit 13 adds a sync pattern immediately before the subcode information and the CRC code received from the CRC encoder.

The video encoder 5 encodes the input video signal according to ISO11172-2 (MPEG1 Video) or ISO13818-2 (MPEG2 Video). At this time, the encoded picture type (I picture / P picture / B picture) and the temporal reference number are sent to the multiplexing circuit 8. When sending a picture header, information indicating that a picture header exists, that is, picture header information, and when further sending an I picture, information indicating that an I picture header exists, that is, entry point information is sent to the subcode encoder 11. .

The audio encoder 6 and the character encoder 7 encode the input audio signal and character signal, respectively, and send them to the multiplexing circuit 8. Multiplexing circuit 8
ISO111 sets the data sent from the video encoder 5, the audio encoder 6, and the character encoder 7.
72-1 (MPEG1 System) or ISO13818
-1 (MPEG2 System).

The user data packetized for each sector by the multiplexing circuit 8 is sent to the subcode adding circuit 15. In the multiplexing circuit 8, a sector boundary signal which becomes "1" only when the head byte of user data, that is, the boundary of a sector is transmitted, and becomes "0" in other cases is sent to the subcode addition circuit 15. send. Further, the sub code adding circuit 15 holds the received sector boundary signal,
When sending data to the DC encoder 16, a sector boundary signal is sent to the EDC encoder 16 such that it becomes "1" only when sending the first byte of user data, and "0" otherwise.

On the other hand, the subcode encoder 11 forms a subcode from the transmitted data with the copyright information, layer information, sector number, track number, application identification number, and application information shown in FIG. , CRC encoder 12. The CRC encoder 12 calculates the CRC code of the subcode data sent from the subcode encoder 11 and adds it to the position immediately before the subcode data to add the sync pattern adding circuit 1
Send to 3.

The sync pattern adding circuit 13 adds the sync pattern (SYNC) to the sub code buffer 14 immediately before the sub code data added with the CRC code, and sends the sub code data to the sub code buffer 14. The subcode buffer 14 holds the sent synchronization pattern, subcode data, and data in which the CRC code is continuous, and sends the data to the subcode adding circuit 15 in response to a request from the subcode adding circuit 15.

In the sub-code adding circuit 15, immediately before the user data sent from the multiplexing circuit 8, the sync pattern corresponding to the sub-code buffer 14 and the sub-code data and the CRC code are obtained immediately before the user data sent from the multiplexing circuit 8. Request continuous data, insert those data and send to EDC encoder 16. The CRC code, subcode and user data sent from the subcode adding circuit 15 are ED.
It is sent to the C encoder 16 and the EDC code is added.
The EDC code is added immediately after the user data and sent to the ECC encoder 17. In the ECC encoder 17,
Calculate the ECC and add it to the sector. In the writing device 18, the modulation circuit (not shown) modulates the data sent from the ECC encoder 17 and records the data sent to the data recording medium 19.

According to the above configuration, when video data, audio data, character data or a plurality of data of them or data produced on a computer are recorded on a recording medium in sector units, a CRC code is applied to each sector. It is possible to add codes different from the EDC code and the EDC code.
Therefore, the code for error detection can be added to the important header in a duplicated manner, and the error resistance is improved.

Data Reproducing Device In FIG. 2, reference numeral 21 generally indicates a data recording medium 1 recorded in the above-mentioned sector format according to the present invention.
9 shows a data reproducing apparatus for reading out video data, audio data, character data, or a plurality of data or data produced on a computer together with additional information from 9 and reproducing using the information.

In the data reproducing device 21, the reading device 22 mechanically mounts (mounts) and unmounts (removes) the data recording medium 19, and also an optical head and a magnetic head for reading a signal from the data recording medium 19. Alternatively, a pickup, which is a magneto-optical head, is driven, a signal is read from the data recording medium 19 using the pickup, and a reproduction signal obtained as a result is demodulated by a demodulation circuit (not shown). The ECC decoder 23 uses the ECC for the demodulated data sent from the reading device 22.
Is calculated and detected, the correctable error is corrected, the ECC is removed, and the user data in which the error is detected and corrected is sent to the EDC checker.

The EDC checker 24 includes a reading device 22.
From the signal containing the EDC code read by the above, the generator polynomial described above is calculated to check if there is an error, and if there is no error, the header and the data are sent to the sub-code separator 26. If there is an error, an error flag (not shown) is sent to the control device 33. Here, the EDC checker is, as described above, for example, as shown in FIG.
It can be composed of a generator polynomial consisting of two registers and a predetermined number of adders. However, the generator polynomial of the CRC code of the present invention has a relationship that constitutes a factor of the generator polynomial of this EDC code.

Therefore, as shown in FIG. 9, the EDC code generation polynomial generation circuit 60 can be composed of a first generation polynomial generation circuit 61 and a second generation polynomial generation circuit 62. In the figure, reference numeral 63 indicates a multiplier. The polynomial generated by either the first generator polynomial generating circuit 61 or the second generator polynomial generating circuit 62 has the same configuration as the generator polynomial of the CRC code. In FIG. 9, the first generator polynomial generating circuit 6
1 has the same configuration as the CRC code generation polynomial generation circuit. For the generator polynomial of the EDC code, the expression is expanded to 32
The usual method is to construct a bit chietuka.

Referring again to FIG. 2, the sub-code separating device 26 separates the sub-code data and the CRC code from the data for one sector sent from the EDC checker 24, and sends the data to the CRC checker 35, and the rest. Data is sent to the ring buffer 27. However, the synchronization pattern is not sent anywhere.

The CRC checker 35 calculates a generator polynomial for the CRC code and the subcode data sent from the subcode separation device 26, checks whether there is an error, and if there is no error, the subcode data is extracted. Send to subcode buffer 25. As described above, the CRC of the present invention
Since the codes are related to the factors of the EDC code, the CRC checker 35 can also serve as a part of the EDC checker shown in FIG. If there is an error, the subcode data is not sent to the subcode buffer 25. The subcode buffer 25 temporarily holds the subcode data and sends the subcode data to the control device 33 in response to a request from the control device 33.

The ring buffer 27 has a FIFO memory inside, and temporarily buffers the user data, sector number data and error flag sent from the sub-code separation device 26, and decodes the user data in response to a request from the demultiplexer 28. Send to the multiplexer 28.

In the configuration of this embodiment, the subcode information is separated immediately before the error correction is performed. However, when the error correction method can be divided into a plurality of procedures, the subcode information is separated during the error correction. You can also

The demultiplexer 28 uses the data sent from the ring buffer 27 as ISO 11172-1.
(MPEG1 System) or ISO13818-1 (M
The video bit stream, audio bit stream, character bit stream, and other bit streams are decomposed according to the regulations of the PEG2 System). Of these, the video bit stream is sent to the video decoder 29, the audio bit stream is sent to the audio decoder 30, the character bit stream is sent to the character decoder 31, and the other bit streams are regarded as computer data and sent to the computer interface 34. .

The video decoder 29 is the demultiplexer 2
The video bit stream sent from the
11172-2 (MPEG1 Video) or ISO138
Decoding is performed according to 18-2 (MPEG2 Video), and the decoding is sent to the post processor 32. Audio decoder 30
Is an audio bit stream sent from the demultiplexer 28 to ISO11172-3 (MPEG1).
Audio) or ISO13818-3 (MPEG2 Au)
dio), and outputs the decoded digital audio signal to the digital audio output terminal and the D / A converter 37. Further, in response to a command from the control device 33, it is possible to prevent the digital audio output terminal from outputting.

The character decoder 31 is the demultiplexer 28.
The character bit stream sent from the device is decoded and sent to the host processor 32. The host processor 32 superimposes the character data sent from the character decoder 31 on the video data sent from the video decoder 29 and outputs the digital video signal subjected to the imposing process to the digital video output terminal and D /
A, output to the NTSC converter 36. Further, according to a command from the control device 33, it is possible to prevent the output to the digital video output terminal.

The control device 33 sends a command to the reading device 22 to start reading from the data recording medium 19,
In addition, a seek command is issued to the reading device 22 to perform a seek operation, and a command for returning from the seek operation to the normal reproduction operation is issued to resume the normal reproduction operation. Further, the subcode data is read from the subcode buffer 25 and the information is also stored. Then, a seek command and a command for returning from the seek to the normal reproduction are issued.

The computer interface 34 temporarily holds the bit stream sent from the demultiplexer 28, converts the electrical characteristics, the signal format and the data format so that the computer can receive it, and outputs the data to the computer data output. Output.

The D / A, NTSC converter 36 converts the digital video signal sent from the post processor 32 into an analog video signal, further encodes it into an NTSC signal, and outputs it to an analog video output terminal. Further, according to a command from the control device 33, it is also possible not to output to the analog video output terminal. The D / A converter 37 converts the digital audio signal sent from the audio decoder 30 into an analog audio signal and outputs it to the analog audio output terminal.
Further, according to a command from the control device 33, it is also possible not to output to the analog audio output terminal.

Description of Operation of Embodiment of Data Reproducing Device In the above-mentioned configuration, the control device 33 first receives a reproducing command from the user and issues a seek command to the reading device 22. The reading device 22 moves the pickup to a predetermined position, reads a signal from the data recording medium 19, and sends it to the ECC decoder 23. The ECC decoder 23 performs error detection and correction using the sent ECC, corrects a correctable error, and outputs user data and the like to the EDC.
It is sent to the checker 24. Here, even if the error is not sufficiently corrected due to a wide error range due to a burst error or the like, the data is sent to the EDC checker 24.
The EDC checker 24 inspects the EDC code from the data error-corrected by the ECC decoder 23. If there is an error as a result of the inspection, although not shown, the control device 33
Send an error flag to. EDC Tietzka 24 has 1
When the inspection of the EDC code of the sector is completed, the data excluding the EDC code is sent to the subcode separation device 26. The sub-code separation device 26 detects a sync pattern from the data sent from the EDC checker 24, divides the data other than the sync pattern based on the position, and divides the sub-code and the CRC code by the CRC checker 35. The user data is sent to the ring buffer 27. The CRC checker 35 performs a check by the CRC code, and if there is no error, sends the subcode data to the subcode buffer 25. If there is an error, the subcode data is not sent to the subcode buffer 25. This is a fatal mistake. Although not shown, when an error is detected, an error flag is sent to the control device. The subcode buffer 25 temporarily holds the subcode data and sends the subcode data to the control device 33 in response to a request from the control device 33. The control device 33 is an EDC
The error flag sent from the checker 24 is compared with the error flag sent from the CRC checker 35. E
Even if the DC code indicates an error, if the CRC code has no error, it can be determined that the subcode has no error. In this case, the application code and the application data defined by the subcode cause the control device 33 to adaptively operate depending on the importance of the application. For example, it is assumed that there is no error in the copy information of the subcode, and when the decoder device is performing the copy operation, the application is a time code and the time code data is written as user data. In this case, even if the EDC code is erroneous, the copying operation can be continued as it is. As a result, in the duplicated sector, the time code data of the user data is
Wrong data is written. However, in normal usage, if the timecode data is not so important,
This is enough.

The user data sent to the ring buffer 27 is sent to the demultiplexer 28, where it is divided into a video bit stream, an audio bit stream, a character bit stream and other bit streams, and the video decoder 29 and the audio decoder 30 respectively. , Character decoder 31, and computer interface 34.

The video bit stream sent to the video decoder 29 is decoded and sent to the post processor 32. The audio bitstream sent to the audio decoder 30 is decoded and output to the digital audio output terminal and the D / A converter 37. The digital audio signal sent to the D / A converter 37 is
It is converted to an analog audio signal and output to the analog audio output terminal.

The character bit stream sent to the character decoder 31 is decoded and sent to the post processor 32. The post processor 32 has a video decoder 29.
Superimpose the character data sent from the character decoder 31 on the video data sent from
Output to the digital video output terminal, D / A, and NTSC converter 36.

The controller 33 controls the sub-code buffer 25.
When the subcode data is stored in the subcode data, the subcode data is read and the subcode buffer 25 is emptied. When the format of the subcode is as shown in FIG. 4, the control device 33 refers to the copyright management information included in the subcode data and outputs the permission and prohibition commands for the digital and analog output terminals of the video and audio signals, respectively. , If the corresponding byte of the copyright management information is other than 0, the post processor 32, D / A, NTSC converter 3
6. Audio decoder 30 and D / A converter 37
Command to prohibit output.

When the subcode data has a format as shown in FIG. 4, random access to each specific track number can be performed. Further, it is possible to access a sector having a specific application code.

In the above embodiment, regarding the sector structure,
A CRC code is added to the head of the header, and an EDC code is added following the user data. However, the position of the CRC code in the sector or the position of the EDC code in the sector can be freely set without departing from the scope of the present invention. Also, 2 bytes as CRC code, EDC
Although 4 bytes are illustrated as the code, the number of bytes can be freely defined as long as the CRC code maintains the factor relationship of the EDC code. For example, 2 bytes for CRC code, EDC
The code is 8 bytes. In this case, the number of bytes of user data in the sector may be changed appropriately.

Further, in the present invention, C is used as an error detecting method.
Although the RC code is used, it can be similarly applied to other detection methods without departing from the spirit of the present invention. Also, CRC
Codes, EDC codes, etc. are used in describing the embodiments of the present invention, and therefore other names are also used.
The gist of the present invention does not change at all.

[0081]

As described above, the sector structure applied to the recording medium of the present invention is particularly important for the header.
The CRC code and the EDC code enable redundant error detection, and the error resistance is strong. Furthermore, the circuit scale of the decoder can be selected by establishing a specific relationship between the generator polynomials of the CRC code and the EDC code.

[Brief description of drawings]

FIG. 1 is a block diagram of a data recording device for recording data on a recording medium using a sector structure according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a data reproducing apparatus for reproducing data recorded on a recording medium using a sector structure according to an embodiment of the present invention.

FIG. 3 is a conceptual diagram of a sector structure in a recording medium according to an embodiment of the present invention.

FIG. 4 is a conceptual diagram of a sector header according to an embodiment of the present invention.

FIG. 5 is a schematic configuration diagram of a CRC generation circuit on the encoding side of a CRC code generation polynomial as an embodiment of the present invention.

6A and 6B are graphs showing a specific operation example in the CRC generation circuit shown in FIG.

FIG. 7 is a schematic configuration diagram of a check circuit on the decoding side of a CRC code generation polynomial as an embodiment of the present invention.

FIG. 8 is a diagram showing a relationship between a CRC code generation polynomial and an EDC code generation polynomial according to an embodiment of the present invention.

FIG. 9 is a diagram showing a configuration example of an EDC code generation polynomial generation circuit according to an embodiment of the present invention.

FIG. 10 is a diagram showing a circuit configuration example on the decoding side of a generator polynomial exemplified in the MPEG system.

[Explanation of symbols]

 12 CRC encoder 16 EDC encoder 17 ECC encoder 23 ECC decoder 24 EDC checker

Claims (10)

[Claims] 1. A recording medium capable of recording time-divided data by using a sector structure or reading the recorded data, wherein the sector of the sector structure is at least a first area. Second
Area of the first area and the first area is at least a CRC for the data.
(Cyclic Redundancy Check) code, and the second area includes at least EDC (
Error Detection Code) code, and the size of the first region is the first generator polynomial P0 (x) in the Galois field of GF (2 ⁿ ) formed by the first generator polynomial P0 (x). And the size of the second region is the second generator polynomial P1 (x) in the Galois field of GF (2 ²ⁿ ) formed by the second generator polynomial P1 (x). A recording medium having a divisible size and having a factor relationship between the first generator polynomial and the second generator polynomial. 2. The recording medium according to claim 1, wherein the first generator polynomial P0 (x) is represented by the following equation, and P0 (x) = x ¹⁶ + x ¹⁵ + x ² +1 P1 generator polynomial is expressed by the following equation ^{(x) = (x 16 +} x 15 + x 2 +1) * (x 16 + x 2 + x + 1) recording medium comprising a. 3. The recording medium according to claim 1, wherein the first area includes at least header information, and the second area includes header information and data. 4. The recording medium according to claim 1, wherein the CRC code is recorded at the beginning of the first area and the EDC code is recorded at the end of the second area. Characteristic recording medium. 5. A recording medium capable of recording time-divided data as a sector structure and reading the data, wherein the sector of the sector structure is at least a first area and a second area.
The first area includes at least a CRC code for the data, the second area includes at least an EDC code for the data, and the size of the first area is the first generation. The size is divisible by the polynomial P0 (x), the size of the second region is divisible by the second generator polynomial P1 (x), and the first generator polynomial and the second generator A recording medium characterized by having a polynomial relationship with a factor. 6. A recording medium capable of recording time-divided data as a sector structure and reading the data, wherein the sector of the sector structure is at least a first area and a second area.
The first area includes at least a CRC code for the data, the second area includes at least an EDC code for the data, and the size of the first area is the first generation. The size of the second region is divisible by the polynomial P0 (x), and the size of the second region is divisible by the first generator polynomial and the second generator polynomial P1 (x). A recording medium, wherein the polynomial and the second generator polynomial have a factor relationship. 7. A data recording device comprising the recording medium according to claim 1 and a write signal processing circuit for recording data on the recording medium. 8. The data recording device according to claim 7, wherein the write signal processing circuit includes: a CRC code generation circuit that calculates a CRC code based on a generation polynomial for subcode information about the recording data; A circuit, an EDC code generation circuit that calculates an EDC code by a generator polynomial from the CRC code, subcode data, and user data, and a circuit that calculates an ECC for a CRC code, an EDC code, subcode data, and a synchronization pattern. The data recording device according to claim 7, which has. 9. A data reproducing apparatus having the recording medium according to claim 1 and a read signal processing circuit for reading data from the recording medium. 10. The data reproducing apparatus according to claim 9, wherein the read signal processing circuit includes a CRC checker that performs an error check using a CRC code and an EDC checker that performs an error check using an EDC code. Playback device.