JPH08191567A - Power supply device - Google Patents

Abstract

PURPOSE: To perform following control with improved response even if the resonance waveform changes extremely owing to an L load by determining the ON timing of a switching element according to the output of a first digital comparator and determining an UP/DOWN counter to be selected according to the output of a second digital comparator. CONSTITUTION: When a transistor SW. F is on, an U/D control circuit 9 controls data to be set in a down counter 3 by allowing U/D counters 7 and 8 to perform count-up or count-down operation. Consequently, while the output H of the counter 3 exceeds a setting value X to be compared by a comparator 2 the ON period of a transistor Tr1 is controlled. Until the transistor SW. F is turned off and a fluorescent lamp FL is lighted, a selector 6 selects the output of the U/D counter 8 when the output value H of the down counter 3 decreases below a setting value W (W<X) by the comparison using a comparator 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply unit, and more particularly to a power supply unit adapted to an image forming apparatus such as a copying machine or a printer.

[0002]

2. Description of the Related Art Conventionally, in a voltage resonance type switching power supply device generally used as this type of power supply device, it is a design point to stabilize the resonance waveform on the primary side of the power supply device and surely perform a zero cross switch. Has become.

[0003]

However, in the conventional power supply device as described above, the presence of the L (impedance) load may cause an extreme change in the resonance frequency. There was a problem that the control was not stable or the responsiveness was poor.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to make it possible to control the resonance waveform with good response even if the resonance waveform extremely changes due to the L load. To provide a power supply device.

[0005]

In order to achieve the above object, the present invention provides an analog comparator for comparing a predetermined value with a detection value obtained by detecting a rectified output of a predetermined winding of a converter transformer, and an output of the analog comparator. Of the first and second up / down counters whose count up / down can be switched by the selector, selectors for selecting the outputs of the first and second up / down counters, and another predetermined winding of the converter transformer. A synchronization circuit for generating a synchronization pulse at a predetermined timing according to the output, a down counter for loading the output of the up / down counter selected by the selector at the generation timing of the synchronization pulse, and an output of the down counter Control circuit including first and second digital comparators for comparing different predetermined digital values And determining the conduction timing of the switching element of the primary side drive winding of the converter transformer according to the output of the first digital comparator, and selecting the selector according to the output of the second digital comparator. The up / down counter to be determined is determined.

Further, as one mode of the present invention, the first and second up / down counters always have a difference of a predetermined value.

As another aspect of the present invention, a control circuit having the same function as the control circuit is provided as a CPU / RO.
It is characterized in that both a digital circuit such as an M / RAM and an analog circuit such as a D / A converter are formed on the same chip.

[0008]

In the present invention, the conduction timing of the switching element of the primary side drive winding of the converter transformer is determined according to the output of the first digital comparator, and the selector is selected according to the output of the second digital comparator. By determining the up / down counter to be used, the period of the voltage resonance waveform is pseudo-measured and two types of drive waveforms having an appropriate ON period are selected. This gives L
Even if the resonance waveform changes extremely due to the load, it is possible to control with good response by following the change.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the configuration of a power supply device according to an embodiment of the present invention. In FIG. 1, the + output obtained by rectifying and smoothing (not shown) the AC (alternating current) line input is applied as VB to one end of the N1 winding which is the primary winding of the converter transformer T1. The minus side of the rectified / smoothed output is indicated by a "circle arrow" in the figure. The other end of the N1 winding is connected to the drain of a switching transistor (FET (field effect transistor) in this embodiment) Tr1. Further, a resonance capacitor C1 is inserted between the terminal of the switching transistor Tr1 and the "circle arrow". The resonance capacitor C1 resonates with the inherent inductance existing equivalently in the N1 winding to make the voltage waveform generated in the N1 winding sinusoidal, thereby reducing switching loss and efficiently. It is for transmitting electric power to the secondary side of the transformer T1. A pulse signal for driving the switching transistor Tr1 is generated by a control circuit described later, and M
It is supplied as a PWM signal via the driver 1. Here, when the control circuit is arranged on the secondary side, it is insulated in the driver 1. By switching the transistor Tr1, each secondary winding N2, N3, N of the transformer T1 is
Similar to the N1 winding waveform, a desired voltage waveform corresponding to each winding ratio is generated at 4, N5 and the like. A plurality of sets of windings are wound according to the required number of outputs as illustrated in FIG. 1, but in the present invention, particular attention is paid to N2, N4 and N5.

N2 is an output winding, and the power supply output V0 rectified and smoothed by the diode D1 and the capacitor C2 is generated from the winding N2. Power output V0 is resistance R1, R2
The voltage is divided by and input to the analog comparator 11 of the control circuit as the voltage detection signal Vsns, and the control circuit operates so as to make the power supply output V0 constant. The control circuit is reset when the power is turned on.

N5 is a detection winding, and the output of the winding N5 is input to the preload terminal of the down counter 3 as a timing synchronization signal SYNC by the synchronization detection circuit 4 as described later. When a signal is input to the preload terminal, the down counter 3 is forcibly reset to zero and is configured to generate a zero flag signal Z. The Z signal loads the down counter 3 via the load control circuit 10. Connected to the terminal. The output of the load control circuit 10 is also input to the up / down control (U / D control) circuit 9.

N4 is a winding for supplying electric power to the fluorescent lamp FL. Since the fluorescent lamp has a high impedance when turned off, a relatively high-voltage AC waveform specific to the fluorescent tube is required to start lighting, and the impedance becomes low when lighting starts, so the voltage waveform during lighting is a low voltage Is. In order to satisfy this condition, in this embodiment, the output of the winding N4 is connected to both ends of the fluorescent lamp LF via the coil LFL.
Further, in order to control the turning on / off of the fluorescent lamp, the diode bridge circuit DB1 and the transistor SW. AC by F
A shunt switch is provided. The capacitor Cy
1 and Cy2 are for adjusting the amount of current for preheating the filament of the fluorescent lamp when the lamp is turned off.

The down counter 3 has a clock CLK having a frequency sufficiently higher than the frequency for driving the transformer T1.
, And a presettable counter having a function of generating the above-described zero flag signal Z having a bit width capable of obtaining the required resolution and period. Outputs of up / down counters (U / D counters) A and B indicated by reference numerals 7 and 8 in the drawing are selected by the selector 6 and input to the digital set input terminal of the down counter 3. Is counted down by.

Further, the U / D control circuit 9 is supplied with a result obtained by comparing the voltage detection signal Vsns with a predetermined value E0 given in advance by the analog comparator 11. U /
The D control circuit 9 generates count-up / down signals and clocks for the U / D counters 7 and 8 from the clock CLK, the comparison result and the output of the load control circuit 10.

Digital output H of the down counter 3
Is compared with a preset digital value X by a digital comparator A indicated by reference numeral 2, and the output of the digital comparator 2 as the comparison result is high / low (high).
The transformer T1 is driven via the driver 1 as an MPWM signal of (h / low) level. Further, the output of the counter 3 is also input to the digital comparator B indicated by reference numeral 5 and compared with a preset digital value W, and the output of the digital comparator 5 as the comparison result causes the selector 6 to generate the U / D counter 7 Any one of 8 is selected and it is determined whether to be the set value of the down counter 3.

The operation of the above control circuits 1 to 11 is shown in the timing chart of FIG. In FIG.
The horizontal axis in the figure represents time. (A) schematically shows the output value H of the down counter 3. (B) is a comparator (A)
2 shows the output, that is, the MPWM signal, (C) shows the output signal SYNC of the synchronization detection circuit 4, and (D) shows the output signal of the analog comparator 11. Further, the rising peak value of the sawtooth wave in (A) corresponds to the output of the U / D counter 7 or 8. Further, X and W in (A) correspond to the set value X of the digital comparator 2 and the set value W of the digital comparator 5. Further, (E) is a drain voltage waveform of the switching transistor Tr1.

The period (I) in FIG. 2 is when the power supply output reaches the target set value and the control is in a stable state.
The high (high) pulse width of the signal is increased or decreased at substantially equal intervals to hold the power supply output V0 of the output winding N2 at a constant value. Further, the period (II) in the diagram of FIG. 2 represents the operation of the waveform during the transient response.

The overall operation of the embodiment of the present invention will be described with reference to FIGS.

First, the transistor SW. If the SYNC signal is generated when F is ON and the SYNC signal is generated, the down counter 3 is reset to zero and the Z flag signal is output as described above. Then, the down counter 3 loads the output of the U / D counter 7 via the selector 6 via the load control circuit 10,
Further, the digital comparator 2 compares the output H of the down counter 3 with the set value X. When the output H is larger than the set value X, the comparator 2 outputs the MPWM signal at the high level. Then, the transistor Tr1 is turned on via the driver 1, and N1 of the transistor T1 is turned on.
The voltage VB is applied to the winding and the excitation energy is accumulated in the N1 winding (timing in FIG. 2).

Next, the down counter 3 outputs the clock CLK.
When the output H of the down counter 3 becomes smaller than the set value X, the comparator 2
Inverts and outputs a low-level MPWM signal (timing in FIG. 2). As a result, the transistor Tr1 is turned off via the driver 1, and the N of the transformer T1 is turned off.
The excitation energy accumulated in one winding voltage-resonates at a frequency determined by the equivalently existing inductance L and capacitor C1 to generate a sinusoidal flyback waveform. This voltage waveform is the secondary winding N2 of the transformer T1.
~ N5 occurs, the diode D1 is turned on, the capacitor C2 is charged, and the DC voltage V0 is obtained.

Further, the down counter 3 has a clock CL.
Although it is counted down by K, the synchronization detection circuit 4 operates at the zero-cross timing shown by the flyback waveform in FIG. 2, and when the SYNC signal is generated, the output of the U / D counter 7 is loaded again via the selector 6. .

With the above as one cycle, the transformer T1 is driven. The U / D control circuit 9 outputs the output V0 to the resistors R1 and R
When the value Vsns divided by 2 is lower than the target set value E0, the U / D counters 7 and 8 are counted up. If the value Vsns exceeds the target set value E0, the U / D counters 7 and 8 are turned on. By counting down, the data set in the down counter 3 is controlled. As a result, the ON period of the transistor Tr1 is controlled while the output H of the down counter 3 exceeds the set value X compared by the comparator 2. The U / D control circuit 9 drives the U / D counters 7 and 8 by adjusting the timing in consideration of the response characteristics of the entire power source and the consistency with the operation in the subsequent stage. In this way, the output V0 is controlled to a constant value by increasing or decreasing the digital set value loaded in the down counter 3.

Transistor SW. When F is ON,
The inductance existing equivalently on the primary side of the transformer T1 is equivalent to the inductance L1 of the N1 winding and the coil LFL being connected in parallel, and in this state, the resonance frequency of the flyback waveform is L1 /. / LFL and C1
Is determined.

However, the transistor SW. F is OFF
Since the fluorescent lamp FL has a high impedance until the fluorescent lamp FL starts lighting, the coil LFL cannot be seen from the primary side, and the resonance frequencies in that case are L1 and C1.
Is determined. Therefore, the transistor SW. F is OFF
Then, as shown in FIG. 2, the frequency of the flyback waveform is lowered and the peak value is reduced. In this case, the peak value generated in each winding decreases, and the output V0 decreases. Of course, the ON period of the switching transistor Tr1 is gradually extended by the U / D control described above, and the peak value is recovered, but the period is relatively long.

Therefore, when the output value H of the down counter 3 becomes lower than the set value W (W <X) by the comparison of the comparator 5, the selector 6 selects the output of the U / D counter 8. The U / D counter 8 is preset with a predetermined value (this is α), and is up / down based on that value, and is always U / D.
The count value is larger than the D counter 7 by the value of α. As a result, the transformer T1 is driven by the data loaded at the timing shown in FIG. 2, so that the peak value shown in FIG. 2 recovers to the original value at once. In addition, the fluorescent lamp F
L turns on and becomes low impedance, or the transistor SW. When F is turned on, the reverse operation is performed.

(Other Embodiments) As a control circuit having the same function as the control circuit including the analog comparator 11, the first and second up / down counters 7 and 8 described above, a C
By forming both digital circuits such as PU / ROM / RAM and analog circuits such as D / A converters on the same chip, each set value can be set by the CPU.
With this configuration, it becomes possible to set the optimum value by software under various conditions.

[0028]

As described above, according to the present invention,
Even if the resonance waveform changes extremely due to the L load, it is possible to realize a power supply device that can respond and control the change with good response.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a power supply device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the control device according to the embodiment of the present invention.

[Explanation of symbols]

 1 Driver 2 Digital Comparator A 3 Down Counter 4 Synchronization Detection Circuit 5 Digital Comparator B 6 Selector 7 Up / Down Counter A 8 Up / Down Counter B 9 Up / Down Control Circuit 10 Load Control Circuit 11 Analog Comparator T1 Converter Transformer Tr1 Switching Transistors N1 to N5 Winding C1 Resonant capacitor

Claims (3)

[Claims] 1. An analog comparator for comparing a detection value obtained by detecting a rectified output of a predetermined winding of a converter transformer with a predetermined value, and counting up / up by the output of the analog comparator.
According to the first and second up / down counters that can be switched down, the selector that selects the output of the first and second up / down counters, and the output of another predetermined winding of the converter transformer. A synchronization circuit that generates a synchronization pulse at a predetermined timing, a down counter that loads the output of the up / down counter selected by the selector at the generation timing of the synchronization pulse, and a predetermined predetermined output that is different from the output of the down counter. A control circuit including a first digital comparator and a second digital comparator for comparing a digital value, and a conduction timing of a switching element of a primary side drive winding of the converter transformer according to an output of the first digital comparator. The selector to be selected according to the output of the second digital comparator. Power supply and determines the-up / down counter. 2. The power supply device according to claim 1, wherein the first and second up / down counters always have a difference of a predetermined value. 3. A control circuit having the same function as that of the control circuit, wherein a digital circuit such as CPU / ROM / RAM and an analog circuit such as a D / A converter are both formed on the same chip. The power supply device according to claim 1.