JPH08190800A - Non-volatile storage device - Google Patents

Abstract

(57) [Summary] [Object] To provide a nonvolatile memory device capable of high-speed operation, in which the layout of a decoder element is adapted to the miniaturization of memory cells. [Structure] In a word decoder circuit hierarchized for speeding up, each decoder element (for example, SD0)
Switch and a n-th row word line (eg, W00, W01) selectively controllable switch (eg, SW0
0, SW01), and one decoder element is shared by the word lines of n rows. With this configuration, the layout pitch of the decoder elements can be n times the pitch of the word lines. Further, the number of decoder elements can be reduced with respect to the number of word lines, and wiring in the word line direction can be reduced. Therefore, it is possible to realize a non-volatile memory device that is suitable for miniaturization of memory cells while increasing the speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory device such as a flash memory, and more particularly, a layout pitch of a decoder element constituting a decoder circuit is made larger than a layout pitch of word lines to enable high integration and high speed operation. Non-volatile storage device.

[0002]

2. Description of the Related Art A flash memory, which is a kind of non-volatile memory device capable of electrically writing and erasing, uses the same fine processing technology because its memory cell has a simple structure consisting of a control gate and a floating gate. Ordinary dynamic random access memory (DRAM)
It can be configured with a smaller memory cell area, and as a result, higher densities are possible, and research presentations have been actively made recently. Fig. 11 shows the 1994 Symposium on Bryer S.I.S. Circuits, Digest of Technical Papers, pp. 61-62 (1994 Sym.
Posium on VLSI Circuits, D
igest of Technical Papers,
pp. 61-62) shows an example of the array configuration in the conventional flash memory. In the figure, C
00 to C1m are memory cells, and m memory cells are present on one data line (D0 or D1) in the sub-array in one block. W00 to W1m are word lines. The sources (S0 or S1) and drains (D0 or D1) of the memory cells in one block are commonly connected using a diffusion layer. This source is connected to a common source line (SL0) via a block selection MOS (ST0S or ST1S) controlled by S0S or S1S. The drain is a block selection MOS controlled by S0D or S1D.
It is connected to the global data line (DL0) via (ST0D or ST1D). By using the diffusion layer wiring in this way, one contact hole to the metal wiring can be shared by m memory cells, and the memory cell area can be miniaturized.

Further, the word decoder circuit is hierarchized into a block decoder for selecting a block and a gate decoder and a sub-decoder for selecting a specific word in the selected block in order to increase the speed. Each of the plurality of sub-decoder elements forming the sub-decoder is composed of a complementary MOS (CMOS) inverter, and each output thereof is connected to a word line. CMOS in Figure 12
An example of the configuration of a sub-decoder element composed of is shown. G00-G
0m is a gate line selection gate signal input to each sub-decoder element, B0P and B1P are power supplies to electrodes of P-channel MOS transistors (hereinafter referred to as PMOSs) of each sub-decoder element, and B0N and B1N are sub-channels. Decoder element N-channel MOS transistor (hereinafter referred to as NMO
S) is the power supply to the electrodes. The gate signal of this sub-decoder element, the power supply signal of PMOS and the NMOS
The power supply signal can be independently controlled by the hierarchical gate decoder circuit and block decoder circuit. The above-described conventional sub-decoder element is provided for each word line, and the PMOS and NMOS of the inverters forming each sub-decoder element are laid out side by side so as to be connected in series in the word line direction. Therefore, in addition to the word lines, B0P,
0N, B1P, B1N wiring, and PMOS and NMO
The wiring connecting the gates of S or the drains of S
It was wired in the word line direction.

[0004]

Since the area of the memory cell in the memory device can be miniaturized by using the diffusion layer wiring as described above, the layout can be performed at a pitch of about twice the minimum processing dimension, and the word line can be arranged. It has become possible to lay out at the same pitch. On the other hand, the word decoder circuit, as shown in FIG.
A plurality of sub-decoder elements, which are layered in order to increase the speed and which form a sub-decoder circuit that directly controls the word lines, are formed by a simple CMOS for reducing the layout area.
Inverter configuration was adopted by. However, even with such a configuration, since the layout of the sub-decoder element has a large number of wirings in the word line direction, the layout rule between the wirings and the diffusion layer cannot keep up with the miniaturization of the memory cell. Has occurred. An object of the present invention is to solve the above-mentioned problems and to provide a non-volatile memory device in which the layout of decoder elements is adapted to the miniaturization of memory cells.

[0005]

To achieve the above object, the present invention is a decoder comprising a plurality of memory cells, a word line connected to the memory cells, and a plurality of decoder elements for driving the word lines. A non-volatile memory device having a circuit, each of the plurality of decoder elements being connected to the plurality of word lines through the first switching means which is selectively controlled. , Complementary MOS transistor (CMO
It is characterized in that it is composed of an inverter composed of S). Further, the first switching means is configured by one NMOS transistor for each word line, a plurality of NMOS transistors connected to a common decoder element have a common diffusion layer on the side connected to the decoder element, and a gate has a word word. The feature is that it is laid out so as to be orthogonal to the line.

[0006]

According to the present invention, with the above configuration, a switch that can be selectively controlled is provided between the output of each decoder element and a plurality of (n rows) word lines, and one switch is provided for a plurality (n rows) of word lines. Since the decoder elements can be shared, the layout pitch of the decoder elements can be increased (n times). That is, the number of decoder elements can be reduced (1 / n) with respect to the number of word lines. Further, the wiring in the word line direction connecting the gates or drains of the COMS inverters forming the decoder element can be reduced by the number of the decoder elements. The switching means (NMO) between the output of the decoder element and the plurality of word lines is used.
In S), the layout is such that the diffusion layer on the decoder side is common and the gate is orthogonal to the word line. This allows
The gate signal of the switching means (NMOS) utilizes on the gate orthogonal to the word line, and wiring can be performed in the same direction as the gate, so that it does not become a factor to increase the word line pitch or the area in the word line direction. . Therefore, a word decoder circuit suitable for miniaturization of memory cells can be realized.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. In the figure, W00 to W in the sub-array
Reference numeral 03 is a word line, D0 is a data line, and memory cells (C00 to C03) are installed at respective intersections of the word line and the data line. Here, for the sake of simplicity, the case of four memory cells per data line is shown. The word lines are laid out at the same pitch as the memory cells. The structure in the memory array may be the same as the structure shown in the conventional example of FIG. Further, the sub-decoder element SD0 has a changeover switch S.
Two word lines W00 and W0 by W00 and SW01
1 and the sub-decoder element SD1 is connected to the two word lines W02 and W03 by the changeover switches SW10 and SW11. That is, each of the sub-decoder elements is shared by two word lines and laid out at a pitch of two word lines. For example, the sub-decoder element S
D0 is shared by the word lines W00 and W01, and the selected word line is switched to W00 or W01 by the switches SW00 and SW01. The switch S shown in FIG.
The connection state of W00 to SW11 is an example when the shaded memory cell C00 is selected. The selection signal from the sub-decoder element SD0 selects only the word line W00 by turning on the switch SW00 and turning off the switch SW01. On the other hand, switches SW10 and SW
When both 11 are turned on, the disturb blocking voltage is applied to the non-selected word lines. In the case of this example, the word line W01 is in a floating state.

FIG. 2 is a block diagram of the second embodiment of the present invention. In the present embodiment, in addition to the configuration of FIG. 1, switches SWR00 to SWR11 are further provided on each word line. As a result, the word line W01
The disturb blocking voltage can be applied to all non-selected word lines including. For example, the sub-decoder element S
D0 is shared by the word lines W00 and W01, and the selected word line is switched to W00 or W01 by the switches SW00 and SW01. FIG. 2 is an example in the case where the memory cell C00 indicated by hatching is selected. The selection signal from the sub-decoder element SD0 selects the word line W00 by turning on the switch SW00 and turning off the switch SWR00. On the other hand, by turning off all the switches SW01 to SW11 and turning on the switches SWR01 to SWR11, the disturb blocking voltage can be applied to all the non-selected word lines W01 to W03. The inventions shown in FIGS. 1 and 2 are characterized in that the sub-decoder elements can be laid out at a layout pitch of, for example, two word lines, and can be adapted to the miniaturization of the memory array. .

FIG. 3 is a diagram showing a third embodiment of the present invention, in which a plurality of blocks of the first embodiment shown in FIG.
Shows the case of two). An example of the write operation of this embodiment is shown in FIG. 4, an example of the erase operation is shown in FIG. 5, and an example of the read operation is shown in FIG. In this embodiment, each switch in FIG. 1 is composed of an NMOS. In FIG. 3, C00 to C13 are memory cells and W0
0 to W13 are word lines, S0 and S1 are memory cell sources, D0 and D1 are memory cell drains, SL
0 is a common source line, DL0 is a global data line, ST
0S and ST1S are source side block selection MOS, S
T0D and ST1D are drain side block selection MO
S, S0S and S1S are source side block selection MOSs
, A gate signal of the drain-side block selection MOS, B0P and B1P are PMOS power supply lines of sub-decoder elements, and B0N and B1N
Is an NMOS power supply line of the sub-decoder element, G00 to G0
1 is a gate signal of the sub-decoder element, SWG00 to SWG
G11 is a gate signal for the selected word line switching MOS. In this embodiment, the sub-decoder element portion of the hierarchical word decoder circuit can be shared by, for example, two word lines and can be laid out at a pitch of two word lines by switching the switch composed of NMOS. become. The write operation, erase operation, and read operation in this embodiment will be described in detail below. In this description, the selected memory cell is assumed to be C00.

First, the write operation will be described in detail with reference to FIG. Memory cells at the time of write operation (C00 to C
03 and C10 to C13) and a block selection MOS (S
The board of T0S, ST1S, ST0D, ST1D) is 0V.
To P of the sub-decoder element in the selected block
Set the MOS power supply B0P to 3V and the NMOS power supply B0N to-
Set to 9V. The gate signal G00 of the sub-decoder element connected to W00 which is the selected word line is 3V, and the gate signal G01 of the sub-decoder element connected to W02 and W03 which is the non-selected word line is -9V. At this time, switch M
Set OS gate signal SWG00 to 3V and SWG01 to -9
By setting V, SWG10 and SWG11 to 3V,
In the selected block, the write gate voltage -9V is applied only to the word line W00, and the unselected word lines W02 and W02
A disturb blocking voltage of 3 V is applied to 03. Word line W01 is in a floating state. Power supply B1 for the PMOS of the sub-decoder element in the non-selected block
The power supply B1N for P and NMOS is set to 0V. Since the gate signal G00 of the sub-decoder element is 3V and G01 is -9V, the unselected word lines W10, W12 and W13 are 0V,
W11 is in a floating state. At this time, the common source line SL0 and the source-side block selection MOS (ST
By setting the gate signals S0S and S1S (0S and ST1S) to 0V, the sources S0 and S1 of the memory cells are brought into a floating state. Global data line DL0 is 4
The gate signals S0D and S1D of the drain side block selection MOSs (ST0D and ST1D) are set to 5V and 0V, respectively. As a result, the drain D0 of the memory cell in the selected block becomes 4V and the drain D1 of the memory cell in the non-selected block becomes in a floating state. By the above operation, memory cell C00 is selected and writing is performed.

Next, the erase operation will be described in detail with reference to FIG. Memory cells (C00 to C03 and C10 to C13) and block selection MOS (ST0S, S0) at the time of erase operation
The substrates of (T1S, ST0D, ST1D) are set to -4V.
The PMOS power supply B0P and the NMOS power supply B0N of the sub-decoder element in the selected block are set to 12V and 0V, respectively. The gate signal G00 of the sub-decoder element connected to W00 which is the selected word line is 0V, and the gate signal G01 of the sub-decoder element connected to W02 and W03 which is the non-selected word line is 12V. At this time, the gate signal SWG00 of the switch MOS is 13V, SWG01 is 0V, SW
By setting G10 and SWG11 to 3V, the erase gate voltage 1 is applied to only the word line W00 in the selected block.
2V is applied and unselected word lines W02 and W03 are 0V
Becomes Word line W01 is in a floating state.
PMOS of sub-decoder element in non-selected block
The power source B1P and the power source B1N of the NMOS are set to 0V. The gate signal G00 of the sub-decoder element is 0V, and G01 is 1
Since it is 2V, the unselected word lines W12 and W13 are 0
V, W10 and W11 are in a floating state. At this time, the common source line SL0 is set to -4V, and the gate signal S0S of the source-side block selection MOS (ST0S and ST1S).
By setting S1S and S1S to 0V, the sources S0 and S1 of the memory cell become -4V. Global data line DL0
Is set to -4V, and the block selection MOS (ST
0D and ST1D) gate signals S0D and S1D are set to 0V. As a result, the drain D0 of the memory cell in the selected block and the drain D0 of the memory cell in the non-selected block
1 becomes -4V. By the above operation, the memory cell C0
0 is selected and erase is performed.

Next, the read operation will be described in detail with reference to FIG. Memory cells (C00 to C03 and C10 to C13) and block select MOS (ST0
The substrates S, ST1S, ST0D, ST1D) are set to 0V. PMO of sub-decoder element in selected block
The power supply B0P for S is set to 3V and the power supply B0N for NMOS is set to 0V. The gate signal G00 of the sub-decoder element connected to W00 which is the selected word line is 0V, and the gate signal G01 of the sub-decoder element connected to W02 and W03 which is the non-selected word line is 3V. At this time, the gate signal SWG00 of the switch MOS is 3V, SWG01 is 0V, and SWG
By setting 10 and SWG11 to 3V, the read gate voltage 3 is applied only to the word line W00 in the selected block.
V is applied and the unselected word lines W02 and W03 become 0V. Word line W01 is in a floating state. The power supply B1P for the PMOS and the power supply B1N for the NMOS of the sub-decoder element in the non-selected block are set to 0V. Gate signal G00 of the sub-decoder element is 0V, G01 is 3V
Therefore, the unselected word lines W12 and W13 are 0V, W
10 and W11 are in a floating state. At this time, the common source line SL0 is set to 0V and the block selection MO on the source side is set.
S (ST0S and ST1S) gate signals S0S and S1S
Are set to 3V and 0V, respectively, so that the sources S0 and S1 of the memory cell are set to 0V and a floating state.
The global data line DL0 is set to 2V, and the gate signals S0D and S1D of the drain side block selection MOSs (ST0D and ST1D) are set to 3V and 0V, respectively. As a result, the drain D0 of the memory cell in the selected block becomes 1V and the drain D1 of the memory cell in the non-selected block becomes in a floating state. By the above operation, the memory cell C00 is selected and read.

FIG. 7 is a diagram showing a fourth embodiment of the present invention, in which a plurality of blocks of the second embodiment shown in FIG.
Shows the case of two). FIG. 8 shows an example of the write operation of the present embodiment, FIG. 9 shows an example of the erase operation, and FIG. 10 shows an example of the read operation. In this embodiment, each switch in FIG. 2 is composed of NMOS. In FIG. 7, C00 to C13 are memory cells and W
00 to W13 are word lines, S0 and S1 are sources of memory cells, D0 and D1 are drains of memory cells, and S
L0 is a common source line, DL0 is a global data line, S
T0S and ST1S are source side block selection MOSs,
ST0D and ST1D are drain side block selection MO
S, S0S and S1S are source side block selection MOSs
, A gate signal of the drain-side block selection MOS, B0P and B1P are PMOS power supply lines of sub-decoder elements, and B0N and B1N
Is an NMOS power supply line of the sub-decoder element, G00 and G01 are gate signals of the sub-decoder element, and SWG00 to SWG00
SWG11 is a gate signal of the selected word line switching MOS,
SWRG00 to SWRG11 are gate signals of the disturb blocking voltage switching MOS, and VSW0 and VSW1 are disturb blocking voltages. In the present embodiment, the sub-decoder circuit portion of the word decoder element that is hierarchized can be shared by, for example, two word lines and can be laid out at a pitch of two word lines by switching the switch composed of NMOS. become. Further, by providing one switch constituted by an NMOS on the opposite side across the memory cell, the disturb blocking voltage can be applied to all non-selected word lines. The write operation, erase operation, and read operation in this embodiment will be described in detail below. In this description, the selected memory cell is assumed to be C00.

First, the write operation will be described in detail with reference to FIG. Memory cells at the time of write operation (C00 to C
03 and C10 to C13) and a block selection MOS (S
The board of T0S, ST1S, ST0D, ST1D) is 0V.
To P of the sub-decoder element in the selected block
Set the MOS power supply B0P to 3V and the NMOS power supply B0N to-
Set to 9V. The gate signal G00 of the sub-decoder element connected to W00 which is the selected word line is 3V, and the gate signal G01 of the sub-decoder element connected to W02 and W03 which is the non-selected word line is -9V. At this time, the disturb blocking voltage VSW0 is set to 3V, the gate signal SWG00 of the switch MOS is set to 3V, and SWG01, SWG10, and S.
WG11 is -9V, SWRG00 is -9V, SWRG0
By setting 1 and SWRG10 and SWRG11 to 3V, the write gate voltage -9V is applied only to the word line W00 in the selected block, and the non-selected word line W01.
A disturb blocking voltage of 3 V is applied to W02 and W03. The PMOS power source B1P, the NMOS power source B1N, and the disturb blocking voltage VSW1 of the sub-decoder element in the non-selected block are set to 0V. Since the gate signal G00 of the sub-decoder element is 3V and G01 is -9V, the unselected word lines W10, W11, W12 and W13 are 0V. At this time, by setting the gate signals S0S and S1S of the common source line SL0 and the block select MOSs (ST0S and ST1S) on the source side to 0V, the sources S0 and S1 of the memory cells are brought into a floating state.
The global data line DL0 is set to 4V, and the gate signals S0D and S1D of the drain side block selection MOSs (ST0D and ST1D) are set to 5V and 0V, respectively. as a result,
The drain D0 of the memory cell in the selected block is 4V, and the drain D1 of the memory cell in the non-selected block is in the floating state. By the above operation, memory cell C00 is selected and writing is performed.

Next, the erase operation will be described in detail with reference to FIG. Memory cells (C00 to C03 and C10 to C13) and block selection MOS (ST0S, S0) at the time of erase operation
The substrates of (T1S, ST0D, ST1D) are set to -4V.
The PMOS power supply B0P and the NMOS power supply B0N of the sub-decoder element in the selected block are set to 12V and 0V, respectively. The gate signal G00 of the sub-decoder element connected to W00 which is the selected word line is 0V, and the gate signal G01 of the sub-decoder element connected to W02 and W03 which is the non-selected word line is 12V. At this time, the disturb blocking voltage VSW0 is set to 0V and the gate signal S of the switch MOS is set.
13V for WG00, SWG01, SWG10, and SWG1
1 for 0V, SWRG00 for 0V, SWRG01 and SWR
By setting G10 and SWRG11 to 3V, the erase gate voltage 12V is applied only to the word line W00 in the selected block, and the non-selected word lines W01, W02, and W
03 becomes 0V. The power supply B1P for the PMOS and the power supply B1 for the NMOS of the sub-decoder element in the non-selected block
N, the disturb blocking voltage VSW1 is set to 0V. The gate signal G00 of the sub-decoder element is 0V and G01 is 12V.
Since it is V, the non-selected word line W10 is in a floating state, and W11, W12, and W13 are 0V. This time,
The common source line SL0 is set to -4V, and the gate signals S0S and S of the source side block selection MOSs (ST0S and ST1S).
By setting 1S to 0V, the source S0 of the memory cell is
And S1 becomes -4V. Global data line DL0 is-
4V, block select MOS on drain side (ST0D
And ST1D) gate signals S0D and S1D are set to 0V. As a result, the drain D of the memory cell of the selected block
0, and the drain D1 of the memory cell of the non-selected block
Is -4V. By the above operation, the memory cell C00
Is selected and erased.

Next, the read operation will be described in detail with reference to FIG. Memory cells during read operation (C00 to C03
And C10 to C13) and block selection MOS (ST0
The substrates S, ST1S, ST0D, ST1D) are set to 0V. PMO of sub-decoder element in selected block
The power supply B0P for S is set to 3V and the power supply B0N for NMOS is set to 0V. The gate signal G00 of the sub-decoder element connected to W00 which is the selected word line is 0V, and the gate signal G01 of the sub-decoder element connected to W02 and W03 which is the non-selected word line is 3V. At this time, the disturb blocking voltage VSW0 is set to 0V and the gate signal S of the switch MOS is set.
3V for WG00, SWG01, SWG10, and SWG11
To 0V, SWRG00 to 0V, SWRG01 and SWRG
By setting 10 and SWRG11 to 3V, the read gate voltage 3V is applied only to the word line W00 in the selected block, and the unselected word lines W01, W02, and W0.
3 becomes 0V. The power supply B1P for the PMOS and the power supply B1 for the NMOS of the sub-decoder element in the non-selected block
N, the disturb blocking voltage VSW1 is set to 0V. Further, the gate signal G00 of the sub-decoder element is 0V, G0
Since it is 13V, the non-selected word line W10 is in a floating state, and W11, W12, and W13 are 0V. At this time, the common source line SL0 is set to 0V, and the gate signals S0S and S1S of the block select MOSs (ST0S and ST1S) on the source side are set to 3V and 0V, respectively, so that the sources S0 and S1 of the memory cells are set to 0V and a floating state. Becomes The global data line DL0 is set to 2V, and the gate signals S0D and S1D of the drain side block selection MOSs (ST0D and ST1D) are set to 3V and 0V, respectively. As a result, the drain D0 of the memory cell in the selected block is 1V,
The drain D1 of the memory cell in the non-selected block is in a floating state. By the above operation, the memory cell C0
0 is selected and reading is performed. Although the flash memory has been described above as an example, the feature of the present invention is that it is possible to realize a word decoder circuit suitable for miniaturization of memory cells at the same time as increasing the speed.
d Programmable ROM), EEPROM (Electrical
It can also be applied to a word decoder circuit such as a ly erasable and programmable ROM) or a ferroelectric memory (the applied voltage for driving is different).

[0017]

According to the present invention, in a word decoder circuit hierarchized for speeding up, a switch which can be selectively controlled is provided between the output of the decoder element and a plurality of word lines, and n Since the sub-decoder elements are shared by the word lines of the rows, the layout pitch of the decoder elements can be increased by n times. Further, the number of decoder elements can be reduced with respect to the number of word lines, and wiring in the word line direction can be reduced. Therefore, it is possible to realize a non-volatile memory device that is suitable for miniaturization of memory cells while increasing the speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a diagram showing an example of a write operation according to a third embodiment of the present invention.

FIG. 5 is a diagram showing an example of an erase operation according to a third embodiment of the present invention.

FIG. 6 is a diagram showing an example of a read operation according to the third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 8 is a diagram showing an example of a write operation according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing an example of an erasing operation according to a fourth embodiment of the present invention.

FIG. 10 is a diagram showing an example of a read operation according to the fourth embodiment of the present invention.

FIG. 11 is a diagram showing a circuit example of a conventional nonvolatile memory device.

FIG. 12 is a configuration example of a sub-decoder element composed of CMOS.

[Explanation of symbols]

SD0 to SD1: Sub decoder element, SW00 to SW1
1: Selected word line changeover switch, SWR00 to SWR
11: Disturb blocking voltage selector switch, C00-
C1m: memory cell, W00 to W1m: word line, SL
0: common source line, DL0: global data line, ST
0S to ST1S: Source side block selection MOS, ST0
D to ST1D: Drain side block selection MOS, S0S
~ S1S: gate signal of source side block selection MOS,
S0D to S1D: gate signal of drain side block selection MOS, B0P to B1P: PMOS of sub-decoder element
Power line, B0N to B1N: NMO of sub-decoder element
S power line, D0 to D1: memory cell drain, S0
-S1: source of memory cell, G00-G0m: gate signal of sub-decoder element, SWG00-SWG11: gate signal of selected word line switching MOS, SWRG00-
SWRG11: gate signal of disturb blocking voltage switching MOS, VSW0 to VSW1: disturb blocking voltage

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoki Miyamoto, 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. In-house

Claims (10)

[Claims] 1. A non-volatile memory device having a plurality of memory cells, a word line connected to the memory cells, and a decoder circuit including a plurality of decoder elements for driving the word lines, wherein the plurality of decoder elements are provided. Each of which is connected to a plurality of word lines via a first switching means which is selectively controlled. 2. The non-volatile memory device according to claim 1, wherein the memory cell has a structure having a control gate and a floating gate. 3. The nonvolatile memory device according to claim 1, wherein the sources and drains of the plurality of memory cells are connected by a buried diffusion layer. 4. Each of the decoder elements is composed of an inverter composed of a complementary MOS, and a gate signal of the inverter, a high potential side power supply signal of the inverter, and a low potential side power supply signal of the inverter are independently provided. 4. The non-volatile memory device according to claim 1, further comprising a control unit. 5. The non-volatile according to claim 1, wherein the first switching means is composed of one N-channel type MOS transistor for each word line. Storage device. 6. The plurality of N-channel type MOS transistors connected to the common decoder element are laid out so that the gates are orthogonal to the word lines with a common diffusion layer on the side connected to the decoder elements. The non-volatile storage device according to claim 5. 7. A second switching means for applying a specific non-selected word voltage to all the non-selected word lines is provided on the opposite side of the memory cell from the first switching means. The non-volatile memory device according to claim 1, wherein 8. The non-volatile memory according to claim 1, wherein the second switching means is composed of one N-channel type MOS transistor for each word line. Storage device. 9. The N-channel MOS transistor constituting the second switching means is laid out such that the gate is orthogonal to the word line with a common diffusion layer on the side to which the non-selected word voltage is directly applied. The non-volatile memory device according to claim 1, wherein the non-volatile memory device is a non-volatile memory device. 10. The nonvolatile memory device according to claim 1, wherein the memory cell is a ferroelectric memory cell.