JPH0818617A - Multilevel encoding modulation system and decoding system therefor - Google Patents

Abstract

PURPOSE:To maintain the ability of codes without increasing a redundant bit number by applying a parity check code to a bit sequence for optional two levels and turning a parity bit to be added to the bit sequence for the two levels to one bit. CONSTITUTION:At the time of defining the bit sequences of a second level for constituting the optional two levels as b21-b23 (a block length L=3) and defining the bit sequences of a first level as a b11 and a b12, a two-level code part 2 generates the even number (or odd number) of a parity one bit P for the bit sequences b21-b23 and b11 and b12 for gathering the two levels and adds it to the bit position of the first level. Even when the parity one bit is added to the bit sequences b21-b23 and b11 and b12 for gathering the two levels in such a manner, the minimum free distance of codes is two and the error correction of one bit is made possible. Also, an encoding rate R becomes R=(2L-1)/2L and the degree of redundancy is lowered without lowering the ability of the codes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-level coded modulation system and a decoding system therefor, and more particularly to two-dimensional coding system.
Multilevel coded modulation in which a binary vector of length m is assigned to each signal point of a digital modulation method having ^m signal points in a one-to-one manner and two levels of the binary vector are collectively coded The present invention relates to a method and its decoding method.

This type of coding / decoding system is applied to digital radio communication and the like as a system for realizing highly reliable data transmission on a band-limited communication path.

[0003]

2. Description of the Related Art FIG. 11 is a diagram for explaining a conventional technique.
As shown in FIG. 11A, Imai, Hirakawa et al. Use a plurality of block encoders having different error correction capabilities, and each encoder has a level corresponding to each component (each bit position) of the binary vector. A multi-level coded modulation method has been proposed in which a bit sequence of L _{1 to} L ₇ is independently coded one level at a time (for example, “A new multi-level coding method using error collecting. Causes "IEE Transactions on Information Seoli, IT-23, Volume 3, May 1977).

However, in the method of independently encoding each level, when attention is paid to an arbitrary one level as shown in FIG. 11B, the signal is taken in four directions around the signal point having the label 0 at the center. Is an arrangement in which four signal points having the label 1 exist at positions separated by the minimum signal point distance (level distance) at that level. That is, there are four types of error patterns (number of error sequences) per bit. It is generally known that if the number of error sequences doubles, the coding gain near the error rate of 10 ⁻⁶ decreases by 0.2 dB.

Therefore, as shown in FIG. 11C, a method of collectively coding two levels has been proposed (Kalder Bank's "Multilevel Cause and
Multi-stage decoding "
E-Transactions on Communication, COM-37, Volume 3, March 1989). In this way, when attention is paid to arbitrary two levels, for example, assuming that the correct signal point is 00, each of the 10,01 (corresponding to the Hamming distance of 1) located at the minimum signal point distance is two points, It is reduced to 1/2. On the other hand, 11 (corresponding to the Hamming distance of 2) exists at four points, but the minimum inter-signal point distance is located at 1.4 times (double the squared distance). Therefore, the reduction in coding gain is approximately half the amount described above.

However, in the case of the method of collectively encoding the above two levels, the level distance is already large, and for example, even with respect to the level 4 which does not need to be encoded, the encoding is performed together with the level 3. This causes a problem that the scale of the decoder and the decoding delay increase. Therefore, conventionally, as shown in FIG. 11D, an error correction encoder 103 that simultaneously encodes two data sequences for consecutive lower two bits including the least significant bit of a binary vector.
And an error correction encoder 1 for separately performing error correction encoding for each level data series of 3rd bit or more
A coded modulation system including 02 and the like has been proposed (Japanese Patent Laid-Open Nos. 2-291743 and 2-291744).

FIG. 11E shows a case where a parity check code of coding rate R = (L-1) / L (where L is a block length) is applied to each level in the error correction encoder 103. When the two levels are put together without changing the coding rate, the parity-bit P _2L and the first level are added to the data bit series b _{21 to} b _{2 (L-1)} of the second level L _2. the L ₁ data bit sequence _{b 11 ~b 1 (L-1} ) parity - would bits P _1L are attached respectively.

[0008]

However, if the two levels are put together without changing the coding rate as described above, the number of parity bits becomes twice as large as in the case of one level, and the coding rate as a whole is lowered. (That is, increase the redundancy).
On the contrary, under the condition that the coding rate as a whole is determined, there is a drawback that the degree of freedom of code allocation is reduced.

An object of the present invention is to provide a multi-level coded modulation system and its decoding system which can maintain the coding capability without increasing the number of redundant bits.

[0010]

The above problems can be solved by the structure shown in FIG. That is, the multi-level coded modulation system of the present invention (1) has a length m of 2 at each signal point of the digital modulation system having 2 ^m signal points per two dimensions.
In a multi-level coding modulation system in which one-to-one allocation of original vectors is performed and two levels of the binary vectors are collectively coded, a parity check code is applied to an arbitrary two-level bit sequence. At the same time, one parity bit is added to the bit sequence for the two levels.

The above problem can be solved by the structure of FIG. That is, the multi-level decoding system of the present invention (6) is an error in accordance with a 2-state trellis in which a parity 1 bit is considered for a 2-level bit sequence in the multi-level decoding system for decoding the multi-level coded signal. The correction decoding is performed.

[0012]

The function of the present invention (1) is shown in (A) and (B) of FIG.
The two-level encoding unit 2 according to (1) sets the second-level bit sequences constituting arbitrary two levels as b _{21 to} b ₂₃ (however, in this example, the block length L = 3) and sets the first-level bit sequences. Is set to b _{11 to} b ₁₂ , an even (or odd) parity 1 bit P is generated for the bit sequences b _{21 to} b ₂₃ and b _{11 to} b ₁₂ that combine these two levels,
This is attached to the bit position of the first level.

By the way, when soft decision Viterbi decoding is adopted for the decoding, the bit sequence b ₁₁ , b _{12 of} the first level as in the prior art is used.
Even if the parity of 1 bit is added to the second level, and the parity of 1 bit is added to the bit sequence b ₂₁ , b ₂₂ of the second level, the minimum free distance of the code of each level is 2 and the capability of the code is 1 bit. Error correction is possible. On the other hand, even if one bit of parity is added to the bit sequences b _{21 to} b ₂₃ and b ₁₁ and b ₁₂ which are two levels as in the present invention, the minimum free distance of the code is 2 and error correction of 1 bit is possible. It will be possible. Moreover, the coding rate R is R = (2L-1) / 2L, and the redundancy can be reduced without lowering the code performance.

Preferably, the parity bit operation is 2
The calculation of the parity bit between the first and second levels forming the level is cumulatively performed for each symbol. That is, in FIG. 1B, first, a parity operation of P ₁ = b ₂₁ + b ₁₁ is performed, and then P ₂ = P ₁ + (b ₂₂ + b ₁₂ ) is performed,
Finally, P = P ₂ + b ₂₃ is performed. Therefore, the parity operation can be serially performed by a single circuit, which saves the circuit.

Further, preferably, the parity bit operation is performed in parallel at the first and second levels forming the two levels, and the parity between the first and second levels is calculated for each coding cycle (ie, block length). Calculate. That is, in FIG. 1B, P ₁ = b ₁₁ + b ₁₂ and P ₂ = b ₂₁ + b
₂₂ + b ₂₃ parity operations are performed in parallel, and finally P
= P ₁ + P ₂ is performed. Therefore, even if the input signal is fast, the parity operation can be performed at high speed.

Further preferably, the parity bits are attached at the same ratio to the bit positions in each of the first and second level coding periods constituting the two levels. That is, for example, in FIG.
As shown in, when given the parity bit P in the first block L ₁ to the first level, the next block L ₂
In, the parity bit P is added to the second level. Therefore, in this case, the time shift of the bit data forming one symbol is 1 bit at the maximum. It should be noted that they may be attached at the same ratio, and they are not necessarily attached alternately.

Also preferably, the first of the two levels comprises
Bit information of the first axis forming the two-dimensional signal space is assigned to the level, and bit information of the second axis is assigned to the second level. That is, assuming that the two-dimensional signal space is represented by orthogonal axes X and Y as shown in FIG. 1C, for example, the Y axis is assigned to the first-level bit sequences b ₁₁ and b ₁₂ , and the X axis is assigned to the X axis. It is assigned to the second-level bit sequences b ₂₁ and b ₂₂ . Therefore, as described with reference to FIG. 11C, this is a signal arrangement with a small number of error sequences, and efficient coding can be performed with redundant 1 bit.

Further, in FIG. 2A, the present invention (6) is used.
2-level decoder 7 by the error correction by soft decision according to the two-state trellis considering parity 1 bit for bit sequence b ₂₁ ~b ₂₃ and b _11, b ₁₂ of the two levels caused by the two-level coding of the Decrypt. That is, assuming even parity, for example, in FIG.
The path starting from the state A ₀ (= 0) goes to the state A ₆ (= 0) through 32 paths consisting of two levels of soft decision bit sequences b _{21 to} b ₂₃ , b ₁₁ , b ₁₂ and the parity bit P. It should come. That is, the remaining 32 paths that reach the state B ₆ (= 1) do not exist. Therefore, 1-bit error correction decoding can be performed by soft-decision decoding of a 2-state trellis considering 1 bit of parity.

Preferably, the decoding according to the two-state trellis is serially performed for each symbol for the first and second level bit sequences forming the two levels. That is, for example, as shown in FIG. 2B, initially, the second level bit data b
The path metric of ₂₁ is calculated, and then the path metric including the first level bit data b ₁₁ is calculated. In this way, the path metric is serially calculated for each symbol. Therefore, the calculation of the path metric can be performed in series with a single circuit, which saves the circuit.

Also preferably, the decoding according to the two-state trellis is performed in parallel at the first and second levels constituting the two levels, respectively, and each survival of the first and second levels is performed at every decoding cycle (ie, block length). Maximum likelihood judgment is performed on the path. That is, for example, as shown in FIG. 2C, the path metrics P ₂ ^A and P ₂ ^{B for} the _second level bit sequence and the path metrics P ₁ ^A and P ₁ ^B for the first level bit sequence are calculated. The operation and the operation are performed in parallel, and finally P
^A series (P ₂ ^A + P ₁ ^A ) in which ₂ ^A and P ₁ ^A are connected,
The maximum likelihood determination of which series has a higher likelihood is performed with the series (P ₂ ^B + P ₁ ^B ) that connects P ₂ ^B and P ₁ ^B. Therefore, even if the input signal is fast, the path metric can be calculated at high speed.

Further, preferably, in the above-mentioned two-level encoding, a process of inverting the bit sequence of the first or second level forming the two levels including the parity bit is added. On the other hand, as shown in FIG. 2C, the received sequence in this case is, for example, the first level bit sequence inverted from the original b ₁₁ , b ₁₂ , P order to P, b ₁₂ , b ₁₁ order. ing. Therefore, in the two-level decoding unit 7 in this case, the second-level path metric starting at the state A ₀₂ (= 0) and the first-level path metric starting at the state A ₀₁ (= 0) must meet at the center. Therefore, the decoding delay is small on the receiving side and the response can be immediately returned to the transmitting side.

[0022]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. FIG. 3 is a block diagram of a coding apparatus of the embodiment. In the figure, 1 is a serial-parallel conversion unit (SP), 2 is a 2-level coding unit, 21 is a 2-bit register (REG), and 22 is a 5-2 bit register. Selectors (SEL) 23 and 24 are adders (EX-O of MOD2).
R circuit), 25 is a 2-1 bit selector (SEL),
26 is a flip-flop (FF), 27 is a 3-2 bit selector (SEL), 28 is a counter (CTR), 2
9 is a ROM, 4 is a signal point converter, 5 is, for example, 128QA
M modulator.

Although not shown, a speed conversion unit associated with the encoding is provided in the preceding stage of the serial-parallel conversion unit 1. The input serial data is 1 in the serial-parallel converter 1.
7-bit parallel data for each symbol (levels L _{1 to} L
₇ ) is converted. The two-level coding unit 2 has L symbols, for example, data sequences I _x and I of the lower two levels L ₁ and L _2.
A parity bit P of 1 bit is added to _{y as} a whole, and the obtained coded data series O _x and O _y are input to the signal point conversion unit 4. On the other hand, the respective data series of the upper 5 levels L _{3 to} L ₇ are directly input to the signal point conversion unit 4.

The signal point converter 4 converts the vector data O _x , O _y , L _{3 to} L ₇ for each symbol into a two-dimensional signal space X, Y.
(However, in this example, 128 QAM is assumed, and X corresponds to the I axis and Y corresponds to the Q axis, respectively). Then, the modulator 5 outputs the mapped data to 128 QA
Modulate to M signal. FIG. 4 is an operation timing chart of the coding apparatus of the embodiment, and for example, a case where the coding cycle (block length) L = 3 will be described.

In this case, the counter 28 repeats the counting cycle such that the counter 28 counts up to 0 to 5 by the clock signal DCK of one symbol period and returns to 0 again. RO
M29 reads the corresponding control (data) signals C ₁ -C ₃ the count value output ADR of the counter 28 as an address input. Focusing on the encoding cycle L ₁ , the serial-parallel conversion unit 1 provides a data sequence I _x = b ₂₁ to b as shown in the figure.
₂₃ , I _y = b _{11 to} b ₁₃ are input in the same phase for every two levels. The register 21 holds each of the data series I _x and I _y in a phase delayed by one symbol period.

When ADR = 0, the selector 22 inputs
I_x, I_yData bit b_{twenty one}, B ₁₁Select each
M_x, M_yOutput to. On the other hand, the selector 27 is also input
M_x, M _yOutput data bit at this point.
Too O_x, O_yIs b_{twenty one}, B₁₁Is. That is, with ADR = 0
Is input I_x, I_yData bit conversion of signal point
Output to section 4.

On the other hand, the adder 24 adds b ₂₁ and b ₁₁ , and the adder 23 adds the output of the adder 24 and the parity bit storage information P _{m of the} FF 26 (initially 0). That is, the adder 23 has generated the parity bit information P at the present time, and when the addition of (b ₂₁ + b ₁₁ ) +0 is performed, 0 is generated if the number of bits of 1 is even, and 1 is generated if it is odd. The selector 25 selects the parity bit information P when ADR = 0, and the FF 26 stores the result P ₁ of the previous parity bit operation by the generation of the next clock signal DCK.

The same applies when ADR = 1, and F
F26 generates the previous clock due to the generation of the next clock signal DCK.
Result P of the result bit₂Memorize ADR = 2
, The selector 22 receives the input I_x, 0 data bits
b_{twenty three}, 0 is selected. On the other hand, FF26 is
Parity bit information P₂(= B_{twenty one}+ B₁₁+ B_{twenty two}+
b₁₂) Is remembered. The adder 23 is (b_{twenty three}+0) + P
₂And the current parity bit information P₃Generate
It The selector 27 receives the input M when ADR = 2._x,
Output data bit O at this point to select P_x,
O _yIs b_{twenty three}, P₃Becomes On the other hand, the selector 27 selects 0
The FF 26 is reset to select.

Next, the coding period L₂Focus on Syria
Data series I from the ru-parallel conversion unit 1_x= B_{twenty four}~
b₂₆, I_y= B₁₄~ B₁₆To enter. On the other hand, register 2
1 is a data series I in the same manner as above._x, I_y1 each
Holds the phase delayed by the rotation period. ADR = 3 odor
Selector 22 receives input I_x, I_ydData bits
b_{twenty four}, B ₁₃And select M_x, M_yOutput to. one
, The selector 27 is also input M_x, M _yTo select
Output data bit O at_x, O_yIs b_{twenty four}, B
₁₃Is. On the other hand, the FF26 receives the next clock signal
Result of bit operation P₁Memorize When ADR = 4
The case is the same as above, and FF26 is a parity bit
Result P₂Memorize

When ADR = 5, the selector 22 inputs
0, I_ydData bits 0 and b_FifteenSelect On the other hand, F
F26 is the parity bit information P up to the previous column₂(=
b_{twenty four}+ B₁₃+ B_{twenty five}+ B₁₄) Is remembered. Adder 23
Is (b_Fifteen+0) + P₂The current parity bit
Information P₃To generate. And the selector 27 is ADR
= 5 input P, M_yOutput at this point to select
Data bit O_x, O _yIs P₃, B_FifteenBecomes

Thus, the parity bit P ₃ corresponding to the bit position of O _y when ADR = 2 and to the bit position of O _{x when} ADR = 5 is added. According to this embodiment, the parity bit has two levels, that is, the first and second levels.
Since the level positions are attached at the same rate (alternately in this example), the bit deviation of one symbol data can be suppressed within a maximum of 1 bit, and the processing such as decoding is easy.

Further, since the data bits b ₂₃ and b ₁₅ can be inserted at the bit position of O _x when ADR = 2 and at the bit position of O _y when ADR = 5, encoding is performed without changing the 1-bit error correction capability. The rate increases. In ADR = 0 of the next encoding cycle L ₃ , data bits b ₂₆ and b _{16 of} inputs I _x and I _yd are required, so the conversion in the serial-parallel conversion unit 1 is suspended once. At the same time, the transfer to the register 21 is also paused once.

FIG. 5 is a diagram for explaining a two-level coding section of another embodiment. FIG. 5A shows a configuration in which the parity operation is performed serially, and the circuit scale can be reduced when the signal transmission speed is not very high. In the figure,
31 is a parallel-serial converter (PS), 32 is a flip-flop (D), 33 is an adder of MOD2, 34,
Reference numeral 35 is a 2-1 bit selector (SEL), and 36 is a serial-parallel converter (SP). It should be noted that the configuration related to the timing control of the counter 28, the ROM 29, etc. is omitted in the figure.

Referring again to FIG. 4, in the encoding period L ₁ , when ADR = 0, the parallel-serial converter 31 sets the bits b ₂₁ , b ₁₁ of the inputs M _x , M _Y in the order of b ₂₁ , b ₁₁ . Then, the serial-parallel converter 36 outputs b ₂₁ and b ₁₁ to the output data bits O _x and O _y . Further, the parity calculation in this case is performed at a high speed in a cycle of 1/2 of one symbol cycle. That is, the adder 32 has b ₂₁ + P _{m in the} first half.
(However, P _m = 0 at the beginning) is performed, and the result is stored in the flip-flop 32. In the latter half, the parity operation of P _m + b ₁₁ is performed and the result is stored in the flip-flop 32. Therefore, ADR =
The content of P _m when entering 1 is P ₁ = b ₂₁ + b ₁₁ . A
The same is true for DR = 1, and the content of P _m when entering ADR = 2 is P ₂ = P ₁ + b ₂₂ + b ₁₂ .

[0035] ADR = parallel over serial converter 31 in 2 outputs an input M _x, the bit b _23, 0 of M _Y in the order of b _23, 0. The adder 32 performs a parity operation of b ₂₃ + P _{2 in} the first half, and the result is flip-flop 32.
To memorize. At the same time, the data bit b ₂₃ is set to the output data O _x of the serial-parallel converter 36. Further, the adder 32 performs a parity operation of P _m +0 in the latter half thereof to generate a parity bit P ₃ . And
At this point, the control signal C ₃ is inverted and the selectors 34 and 35 are
Respectively select the terminal a side. As a result, the parity bit P ₃ is set in the output data O _y of the serial-parallel converter 36, and 0 is set in the flip-flop 32.

When ADR = 3, the parallel-serial conversion unit 31 converts the bits b ₂₄ and b ₁₃ of the inputs M _x and M _Y into b ₁₃ and b _24.
, And the serial-to-parallel converter 36 outputs b ₂₄ and b ₁₃ to the output data bits O _x and O _y . Less than,
Parity calculation is performed in the reverse order of the above, and ADR = 5
Then, the data bit b ₁₅ is the serial-parallel conversion unit 36.
Of the output data bit O _y and the parity bit P ₃ is set to the output data bit O _x .

FIG. 5B shows a configuration in which parity calculation is performed in parallel, and high-speed calculation is possible even when the signal transmission speed is high. In the figure, 37 is a MOD2 adder. In this case, the parity calculation is performed in parallel for each symbol period. Referring again to FIG. 4, the flip-flop 32 ₁ has P _2x = as the contents of P _m by ADR = 1.
Hold b ₂₁ + b ₂₂ . Further, the flip-flop 32 ₂ holds P _2y = b ₁₁ + b ₁₂ as the contents of P _m by ADR = 1.

When ADR = 2, b is used as inputs M _x and M _Y.
23, 0 is input. As a result, the adder 33 ₁ has P _2x +
b ₂₃ , and the adder 33 ₂ performs P _2y +0. Then, the adder 37 sets the parity bit P as P ₃ = (P
_2x + b ₂₃₎ to generate a + (P _2y +0). On the other hand, the data bit b ₂₃ is output to the terminal O _x via the selector 35 _1, and the parity bit P ₃ is output to the terminal O _y via the selector 35 ₂ when the control signal C _2y is inverted. The same applies to ADR = 3 to 5, but the parity bit P ₃ is output to the terminal O _x via the selector 35 ₁ when the control signal C _2x is inverted.

FIG. 6 is a block diagram of the decoding apparatus of the embodiment.
In the figure, 6 is a demodulator, 7 is a two-level decoding unit, 71, 7
2 is a branch metric calculation unit, 73 is a data selector (SEL), 74 is a branch metric addition and comparison selection unit (ACS), 75 is a path metric memory, 76 is a path memory, 77 is a counter (CTR), and 78 is timing generation. Unit (TG), 8 is a signal determination unit, 9 is a parallel-serial conversion unit (PS), and 10 is a delay unit that absorbs a decoding delay.

Although not shown, speed conversion accompanying decoding
The unit is provided in the subsequent stage of the parallel-serial conversion unit 9. demodulation
The device 6 demodulates the intermediate frequency signal IF of 128 QAM, for example.
And outputs a demodulated baseband signal BBS. level
L₂, L₁Baseband signal sequence R_x, R_YIs 2 level
2 which is input to the decoding unit 7 and takes the parity bit P into consideration.
1-bit error correction decoding is performed according to the state trellis
It Remaining level L₃~ L₇The baseband signal sequence of is
The signal is input to the signal determination unit 8 via the delay unit 10. Return here
No. result (H _x, H_y), The signal point is determined and the level L
₁~ L₇The bit data of is output. Parallel-Siri
Al conversion unit 9 is level L₁~ L₇Bit data of
Convert to Aldata and output.

FIG. 7 shows the operation timing of the decoding apparatus of the embodiment.
It is a chart, for example, the case of decoding cycle L = 3 is demonstrated.
It Decoding cycle L₁Paying attention to, at ADR = 0,
The branch metric calculation unit 71 uses the baseband signal b_{twenty one}
Branch metric b_{twenty one}{That is, the baseband signal b
_{twenty one}And probability information that represents the distance (likelihood) between 0 and 1
And the branch metric calculation unit 72 calculates
Sband signal b₁₁Branch metric b ₁₁Calculate
It

The data selector 73 selects branch metrics b ₂₁ and b ₁₁ of the arithmetic units 71 and 72 in the order of b ₂₁ and b ₁₁ during one symbol period and inputs them to the ACS 74. AC
S74 along with obtaining the path metric value of 2-state trellis as shown on the basis of the branch metric b _21, b _11, and stores the selected path metric value of the maximum likelihood path (2) in the path metric memory 75 . When such calculation is repeated until ADR = 2 is reached, the state A ₆
And two paths to state B _{6 (} not shown) survive.

By the way, assuming even parity,
State A₀The path starting with (= 0) is the parity bit P
₃Status A by receiving₆Do not end with (= 0)
must not. Therefore, the parity bit P₃Received
State A when₆Only the path leading to
74 writes this in the path memory 76. In addition, ACS
74 is the decryption data corresponding to the final survivor path above.
Series of tabits b_{twenty one}~ B_{twenty three}And b₁₁, B₁₂Pass memory
Write to 76. And the decoded data bit b_{twenty one}~ B_{twenty three}
Is terminal H_xTo the decoded data bit b₁₁,
b ₁₂Is terminal H_yRead out.

The same applies to ADR = 3 to 5 in the decoding cycle L ₂ . In this case, if b ₂₄ , b ₁₃ , b ₂₅ ,
When the path metric is calculated in the order of b ₁₄ , P ₃ , and b ₁₅ , A
When DR = 5, the ACS 74 receives the parity bit P ₃ before the data bit b ₁₅ , but there is no problem. Assuming even parity, state A ₆ (= 0)
This is because the path that started with must end in state A ₁₂ (= 0) by receiving the last data bit b ₁₅ .

The decoding cycle L₂ADR = 3-5
Where b₁₃, B_{twenty four}, B₁₄, B _{twenty five}, B_Fifteen, P₃Order of
It is obvious that the path metric can be obtained with.
In the above embodiment, even parity is assumed.
It may be a number parity. In the above embodiment, the state A
₀It started from (= 0), but state B₀From (= 1)
It may be configured to start.

FIG. 8 is a diagram for explaining a coding apparatus according to another embodiment. In the drawing, 3 is a code sequence conversion unit. This code sequence conversion unit 3 is preferably inserted between the path memory 76 and the parallel-serial conversion unit 9 in FIG. Alternatively, instead of providing the code sequence conversion unit 3, the path memory 7
You may devise so that the reading order of the bit sequence from 6 may be changed.

For example, the decoding cycle L₁Pay attention to
The column conversion unit 3 uses the data bit b_{twenty one}~ B _{twenty three}About that
Output in the same order, but data bit b₁₁, B₁₂And
Reity Bit P₃Invert the order of the bit sequence
And output. The reason will be clear in the following explanation.
It FIG. 9 is a block diagram of a decoding device according to another embodiment.
Reference numeral 79 is a maximum likelihood determination unit, 80 is a data selector (SE
L). Also, in this example, a plurality of ACS74₁, 7
4₂, Path metric memory 75₁, 75₂And pasme
Mori 76₁, 76₂Is equipped with the parallel processing
The speed has been increased.

FIG. 10 is an operation timing chart of the decoding apparatus of another embodiment, and the case of the decoding cycle L = 3 will be described. Here, a part of the input sequence to the 2-level decoding unit 7 is inverted by the code sequence conversion unit 3 in FIG. In the decoding cycle L ₁ , the ACS 74 ₁ is in the state A _0x (= 0).
The path metrics P _x ^A and P _x ^B are obtained based on the branch metrics b _{21 to} b ₂₃ beginning with, and two bit sequences b _{21 to} b ₂₃ (final state A _3x ) and b ₂₁ corresponding to these surviving paths are obtained. ~ B ₂₃ (final state B _3x ) is stored in the path memory 76 ₁ . Further, for example, assuming even parity, ACS74 ₂ also states A _0y (= 0) in the beginning branch metric P ₃ based on ~b ₁₁ path metrics P
_y ^A and P _y ^B are obtained, and two bit sequences P _{3 to} b ₁₁ (final state A _3y ) and P _{3 to} b ₁₁ (final state B _3y ) corresponding to these surviving paths are stored in the path memory 76.
Remember in ₂ .

As described above, since the two path metrics P _X and P _Y start from the leading end and the trailing end of the bit sequence of each level, they can join at the center. Here, since there is no other data bit between the data bit b ₂₃ and the data bit b ₁₁ , the two path metrics P _X and P _Y are the states A _3X and A _3y or the states B _3X and B. There is no other than connecting with _3y . Therefore, the maximum likelihood determination unit 7
9 is (P _x ^A + P _{y at} the end timing of ADR = 2.
^{_{A)> (P x B +}} P y B) or ^{_{(P x A + P y A}} ) <(P
_x ^B + P _y ^B ).

Then, (P_x ^A+ P_y ^A)> (P_x ^B+
P_y ^B), The data selector 80 is controlled.
From the pass memory 76₁To bit sequence b_{twenty one}~ B_{twenty three}(State
State A _3x) To select H_xTo the path memory 76
₂To bit sequence P₃~ B₁₁(State A_3y) To select H
_yOutput to. Also (P_x ^A+ P_y ^A) <(P_x ^B+ P
_y ^B), The path memory 76₁To bit sequence b_{twenty one}~
b_{twenty three}(State B_3x) To select H_xOutput to
Mori 76₂To bit sequence P₃~ B₁₁(State B _3y)
Select H_yOutput to. Also (P_x ^A+ P_y ^A) = (P
_x ^B+ P_y ^BIn the case of (), either may be determined as the maximum likelihood.

Incidentally, in this embodiment, in the decoding cycle L ₁ , it is determined that (P _x ^A + P _y ^A )> (P _x ^B + P _y ^B ),
In the decoding cycle L ₂ , (P _x ^A + P _y ^A ) <(P _x ^B + P _y
^B ), and in the decoding cycle L ₃ (P _x ^A + P _y ^A )>
The case where it is determined as (P _x ^B + P _y ^B ) is shown. In this embodiment, the code sequence conversion unit 3 inverts the bit sequence of one level, but the present invention is not limited to this. Even if a parity bit appears in the middle of the path metric by not inverting the bit sequence, for example, assuming even parity, the two 2-state trellis have states A _0x (=
0) and the state A _0y (= 0), the maximum likelihood determination can be performed in the center in the same manner as above.

In the above embodiment, the case where the lowest levels L ₁ and L ₂ are collectively coded / decoded has been described.
It is not limited to this. The present invention is arbitrary 2 in X axis or Y axis.
Obviously, it can be applied to any two levels of coding / decoding across levels or X and Y axes. Although a plurality of preferred embodiments of the present invention have been described above, it is needless to say that various changes in configuration and combination can be made without departing from the spirit of the present invention.

[0053]

As described above, according to the present invention, a parity check code is applied to an arbitrary 2-level bit sequence, and the parity bit to be added to the 2-level bit sequence is 1 bit. By doing so, the ability of the code can be maintained without increasing the number of redundant bits. In addition, error correction decoding can be efficiently performed according to a 2-state trellis in which 1 bit of parity is taken into consideration for the bit sequence of 2 levels.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram for explaining the principle of the present invention.

FIG. 3 is a block diagram of an encoding device according to an embodiment.

FIG. 4 is an operation timing chart of the encoding device according to the embodiment.

FIG. 5 is a diagram illustrating a two-level encoding unit according to another embodiment.

FIG. 6 is a block diagram of a decoding device according to an embodiment.

FIG. 7 is an operation timing chart of the decoding device according to the embodiment.

FIG. 8 is a diagram illustrating a coding device according to another embodiment.

FIG. 9 is a block diagram of a decoding device according to another embodiment.

FIG. 10 is an operation timing chart of a decoding device according to another embodiment.

FIG. 11 is a diagram illustrating a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 serial-parallel conversion part 2 2 level encoding part 3 code sequence conversion part 4 signal point conversion part 5 modulator 6 demodulator 7 2 level decoding part 8 signal determination part 9 parallel-serial conversion part

Claims (10)

[Claims] 1. A binary vector of length m is assigned to each signal point of a digital modulation method having 2 ^m signal points per two dimensions in a one-to-one manner, and two levels in the binary vector are summarized. In a multi-level coded modulation method of encoding by using a parity check code, a parity check code is applied to an arbitrary 2-level bit sequence and the parity bit added to the 2-level bit sequence is set to 1 bit. Characteristic multilevel coded modulation method. 2. The parity bit calculation is performed by accumulating the calculation of the parity bit between the first and second levels forming two levels for each symbol.
Multi-level coded modulation scheme. 3. The parity bit operation is performed in parallel at the first and second levels forming the two levels, and the parity operation between the first and second levels is performed at each encoding cycle. The multi-level coded modulation method according to claim 1. 4. The multi-level coded modulation system according to claim 1, wherein parity bits are attached to bit positions in each of the first and second level coding periods constituting two levels at the same ratio. 5. The bit information of the first axis forming the two-dimensional signal space is assigned to the first level forming the two levels, and the bit information of the second axis is assigned to the second level. The multi-level coded modulation method of Item 1. 6. The multi-level decoding system for decoding a multi-level coded signal according to claim 1, wherein error correction decoding is performed on a 2-level bit sequence according to a 2-state trellis considering one bit of parity. And multi-level decoding method. 7. The multi-level decoding system according to claim 6, wherein the decoding according to the two-state trellis is performed serially for each symbol for the first and second level bit sequences forming two levels. 8. Decoding according to a two-state trellis is performed in parallel at first and second levels forming two levels, and maximum likelihood judgment is performed for each surviving path at the first and second levels for each decoding cycle. The multilevel decoding method according to claim 6, wherein the multilevel decoding method is performed. 9. The multi-level coded modulation method according to claim 1, wherein a bit sequence of a first level or a second level forming two levels is inverted including a parity bit. 10. The multilevel decoding system according to claim 8, wherein decoding is performed by using the bit sequence of claim 9 as an input.