JPH0818399A - Adaptive filtering circuit - Google Patents

Abstract

PURPOSE:To reduce the size and lower the cost by composing the adaptive filtering circuit of a relatively simple 1-bit A/D converter. CONSTITUTION:Counters 2 and 6 which are connected to a signal RAM 3 and a coefficient RAM 7 count the same length as tap length cyclically. The speed of a clock is a speed for generating a clock signal L times in single-time oversampling. The counter 2 on the side af the signal RAM and the counter 6 on the side of the coefficient RAM operate synchronously, but the clock signal is not inputted to only the signal RAM side once in single-time oversampling. A value for rewriting the coefficient RAM is generated from an error signal and past signal data (signal RAM). This value is written repeatedly until the coefficient RAM enters an unwritable state. The write acknowledgement state of the coefficient RAM is set each time the rewrite value is prepared, but reset if a value in the coefficient RAM is different from the rewrite value, so that the coefficient RAM is disabled to be written.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive filtering circuit, and more particularly to an adaptive filtering circuit which is designed to be simplified by using a digital signal.
For example, it is applied to all devices and parts using an adaptive digital filter.

[0002]

2. Description of the Related Art In recent years, active noise control of noise (hereinafter abbreviated as ANC) has attracted attention and has been actively researched, and has been put to practical use in ducts of air conditioners and ear protectors. However, in general, in order to realize an ANC system, a large amount of product-sum operations are required, and an operation part (DSP: Digital Signal P) for processing this is required.
In some cases, the rocessor) occupies a large cost of the ANC device. In particular, the ANC is built into the equipment in the office.
In consideration of the above, unlike a relatively large device (for example, an air conditioning duct of an elevator), an increase in cost is a factor that cannot be ignored. Therefore, ANC in a form that does not require complicated calculation and therefore DSP.
A scheme has been proposed.

First, oversampling 1 bit ΔΣ
The (delta sigma) modulation method will be described. Delta-sigma modulation takes the difference between the output and the input signal, performs integration, and performs feedback control so that the output of this integrator is minimized.The quantization noise included in the code string of the output of the quantizer is used. Is also known as a noise shaping type because it has a property of being biasedly distributed in a high frequency region.
When the signal by this modulation method is used for ANC, there are the following advantages.

Delta-sigma modulation is inaccurate at high frequencies due to quantization noise, but ANC rarely targets high frequencies, and the quantization noise is not a major disadvantage. Since the delta-sigma modulated signal can be basically considered as a signal with noise added to the original signal, it is considered that conventional signal processing and adaptation algorithms can be applied almost as they are. To be

Further, as described above, when sampling is performed in the frequency region of the control target, the high frequency quantization noise portion is included as it is. In order to avoid this, an oversampling method is adopted in which sampling is performed at a frequency higher than the frequency range of the control target. Hereinafter, when it is described as a 1-bit signal without notice, this over-sampled 1-bit delta-sigma modulation signal is shown.

Next, the filtering method will be described. The delta-sigma modulated signal is considered a noisy signal of the original signal. Here is generally AN
FIR (Finite Impulse Respons) used in C
e) Type filtering was used. The 1-bit FIR filtering method is shown below.

[0007]

[Equation 1]

In the equation (1), F is an output signal, f is an input signal, and w is a filter weight. The subscript n is
Indicates the number of sampling. f ¹ and w ¹ are 1-bit signals, respectively. L indicates the number of taps of the FIR filter. Now, looking at the equation (1), it is noticed that the input is a 1-bit signal, but the output signal is the addition of L 1-bit signals and is not 1 bit. When the equation (1) is examined in more detail, the equation (1) is transformed into the following equation (2) by setting g ¹ k = f ¹ nk · w ¹ k, and the equation (1) is It can be seen that it is the output of a certain low-pass filter (moving average filter).

[0009]

[Equation 2]

However, the F ³ n of the output signal is also a signal on the premise of oversampling, and if the oversampling rate of the input signal is M, the actually used signal is a signal P n obtained by low-pass filtering F ³ n. Is.

[0011]

(Equation 3)

However, u is a coefficient of the low-pass filter. By substituting the equation (1) into the equation (3), the following equation (4) is finally obtained.

[0013]

[Equation 4]

However, [x] is the minimum integer that does not exceed x, and x% M is the remainder obtained by dividing x by M. (4)
Expression B is a further extension of the low-pass filter u, and is eventually a low-pass filter. As described above, Pn is the result of the 1-bit operation, f ¹ nk ·
The signal sequence of w ¹ k can be obtained only by passing it through some low-pass filter, and filtering can be performed only by multiplication of the 1-bit signal and the low-pass filter.

In the above description, the filtering can be performed only by the low-pass filter and the 1-bit multiplication. However, in order to simplify the discussion below, the filtering is performed by multiplication and integration (that is, calculation of Σ). As it is). Further, although delta-sigma modulation can be guaranteed for the input signal, the filter coefficient is formed in the adaptive process in adaptive filtering, and it cannot be guaranteed that it becomes a delta-sigma modulated 1-bit filter coefficient string. Therefore, the value of the 1-bit signal string is stochastically guaranteed.

With respect to the original signal f (ω) and the original filter w (ω), the signal f ¹ (ω) represented by a 1-bit string and the filter w
Consider ¹ (ω) as follows. f ¹ (ω) = f (ω) + Nf (ω) w ¹ (ω) = w (ω) + Nw (ω) (5) However, in the above equation, Nf (ω) and Nw (ω) are f (ω) quantization error and w (ω) quantization error.

By using the above equation (5), filtering can be expressed by the following equation (6). f ¹ (ω) ・ w ¹ (ω) = (f (ω) + Nf (ω)) ・ (w (ω) + Nw (ω)) = f (ω) ・ w (ω) + Nf (ω) ・ w (ω) + Nw (ω) · f (ω) + Nf (ω) · Nw (ω) (6) The first term is the filtering result desired to be obtained. Are the influence term of the quantization noise, and the influence term of the filter and the signal quantization noise.

In equation (5), the quantization error of delta sigma modulation is given by the following equation. Nf (ω) · Nf (ω) to Δ ² / 9π · (2πω ₀ / ω) ³ (7) where Δ ² is the maximum power per sampling. If the band is limited to 1 / M: Nf (ω) · Nf (ω) to Δ ² / 9π · (2π / M) ³ (8) Further, regarding the filter, when dither is added and sampling is performed with 1 bit. Consider In this case, since the quantization noise is uniformly distributed in all bands, if the number of bands is L, then Nw (ω) · Nw (ω) to Δ ² / (3 · L) (9) .

On the other hand, assuming white noise in which both the signal and the filter are band-limited to 1 / M, f (ω) f (ω) to MΔ ² / (3L) w (ω) w ( ω) to M · Δ ² / (3 · L) (10) From the above calculation, as the S / N ratio, S / N to M ² / {1 + M + 8π ² / (3 · M ² )} (11) And an S / N ratio of about M can be expected.

As an adaptive algorithm, SA (Sign Alg
orbit (Binary Sign Algori)
thm) was developed. SA is an algorithm for adapting the filter using only the sign of the error signal and the input signal. Although SA is inferior to LMS in terms of convergence speed and convergence value, it has the advantage of light calculation load. SA coefficient update formula, BSA
The coefficient updating formula of is shown below. SA: wk = wk + α · sign (e) · fn-k ... (12) BSA: w 1 k = -1 · w 1 k ... (13) ^{However, w 1 k ≠ sign (e} ) · f 1 nm and f ^The coefficient has not been updated for ¹ nm. Wherein subscript of f letter m is a representative point for updating the coefficient sequence w ¹ k~w ¹ k + x a range, typically, the over-sampling rate as M, the range of the coefficient sequences w ¹ ₀ ^{~w 1 M-1, w 1} M~w 1 2M-1, ... and take, f ¹ n as the corresponding representative point, are choosing f ¹ nm ....

Regarding the conventional adaptive algorithm, "adaptive algorithm [II]" (Kazukazu Kubota, Vol.74, No.6, pp. 597 of the Institute of Electronics, Information and Communication Engineers).
-602, June 1991), regarding the A / D / D-A conversion technology using the oversampling method, see "NIKKEI ELECTRONIC".
S "(1988, 7.25, No. 452, pp277)
-285) and "NIKKEI ELECTRONIC
S "(1988, 8.8, No. 453, pp211-
221). According to this, it is explained as follows.

In the conventional A-D converters up to now, sampling is performed at intervals close to the minimum necessary according to the frequency bandwidth of the analog signal, and the data is converted into digital data. In the oversampling method, the sampling interval is shortened. One of the great advantages of high-speed sampling is that the characteristics of the analog filter required before the A / D converter can be relaxed.

The oversampling A / D conversion technique uses a circuit technique different from the A / D conversion which has been popular in the past. That is, it is a technique called delta modulation or delta sigma modulation. At the root of this technological shift is
Perspectives of limitations over conventional technology and oversample A
There is a recognition that -D conversion technology can exceed this limit.
This technique can be applied not only to analog-to-digital conversion, but also to DA conversion circuits. Analog circuit,
As a circuit technology that mediates digital circuits with high accuracy, it will be applied as an essential technology for future ASICs.

[0024]

The active noise control of the 1-bit signal processing described above is based on oversampling, and therefore requires a number of calculations, and the oversampling ratio M and the total number of taps M × N (that is, When the control target frequency is H (Hz), which corresponds to an N-tap filter in the case where oversampling is not performed, the calculation amount X required for one second is X = 2 · H · N · M ² . When M = 64, H = 250, N = 16, X = 32
768000, which requires a clock frequency of about 33 MHz.

The adaptive filtering processing of digital signals is a technique required in the field of acoustic signal processing and the like. Conventionally, in order to process this, a signal is sampled at 16 bits or the like and adaptive filtering is performed using a DSP. However, in the case of such a circuit configuration, a 16-bit AD converter and a D / D for product-sum calculation are used.
Since the SP and the like are relatively large, it has hindered circuit miniaturization and cost reduction.

The present invention has been made in view of the above circumstances, and is an adaptive filtering circuit in which the circuit is configured by a relatively simple 1-bit A / D converter to achieve miniaturization and cost reduction. Is intended to provide.

[0027]

In order to achieve the above object, the present invention provides (1) filtering an input signal when the input signal is filtered by an unknown system and observed as a first output signal. In the adaptive filtering circuit, which generates a second output signal by filtering using the, and updates the filter so that the difference between the second output signal and the first output signal becomes small, Oversampling is performed as a bit probability density signal, and the difference between the second output signal and the first output signal is set to 1
Sampling as a bit signal,
(2) A delta-sigma modulation method is used as the 1-bit probability density modulation method, and (3) the filter is a 1-bit probability density signal.
(4) The adaptive method of the filter is i
If the second value is to be applied in the positive or negative direction, searching for and updating the filter position j that is closest to the position i and is capable of changing the value in the positive or negative direction;
(5) In the above (4), if the adaptation is desired to be performed quickly, the filter update position is selected densely, and if it is desired to be performed with accuracy, the filter update position is roughly selected. (6) In (1) above, as a method of adapting the filter, a value to be adapted and a sum signal of x times the filter coefficient string are delta-sigma modulated to form a new filter coefficient string, (7) In (6) above, if the adaptation is desired to be performed quickly, the value of x should be reduced,
The feature is that the value of x is increased in order to perform it with high accuracy.

[0028]

According to the adaptive filtering circuit of the present invention having the above-mentioned structure, (1) when an input signal is filtered by an unknown system and observed as a first output signal, the input signal is filtered using a filter, In the adaptive filtering circuit that updates the filter so that the difference between the second output signal and the first output signal is reduced by the method of generating two output signals, the input signal is a 1-bit probability density signal. As a result, the circuit can be configured with a relatively simple 1-bit AD converter by over-sampling and inputting, and by inputting the difference between the second output signal and the first output signal as a 1-bit signal. This leads to downsizing and cost reduction. (2) As a method of 1-bit probability density modulation, delta
By using the sigma modulation method, an accurate signal can be obtained in the signal band. (3) By using a 1-bit probability density signal as the filter, internal filtering calculation can also be configured by 1-bit signal processing, which leads to downsizing of the circuit and cost reduction. (4) As an adaptive method of the filter, when it is desired to adapt the i-th value of the filter in the positive (or negative) direction, the position i
The adaptive signal processing using the 1-bit signal is possible by searching for and updating the filter position j that is closest to, and whose value can be changed in the positive (or negative) direction. (5) When the adaptation is desired to be performed quickly, the update positions of the filter are closely selected, and when it is desired to perform the adjustment accurately, the update positions of the filter are roughly selected, and thus 1 The adaptive speed can be controlled in the adaptive signal processing using the bit signal. (6) As a filter adaptation method, a value to be adapted and a sum signal of x times the filter coefficient string are delta-sigma modulated to form a new filter coefficient string, whereby adaptive signal processing using a 1-bit signal is performed. It will be possible. (7) The adaptive signal using the 1-bit signal described in (6) above is set by decreasing the value of x when performing the adaptation quickly and increasing the value of x when performing the accuracy. The adaptive speed can be controlled in the process.

[0029]

Embodiments will be described below with reference to the drawings. Adaptive filtering is used for system control and estimation, but specifically, acoustic signal processing, especially active noise control is assumed. Active noise control captures the signal of the noise source,
Noise is reduced by estimating how the signal is transmitted to the control point and preparing a control signal in the opposite direction to the noise signal at the control point. For this reason, it is necessary to estimate how the sound is transmitted from the noise source to the control point (system estimation).

The adaptive algorithm used in the present invention is
It is based on the adaptive algorithm described above, and is simply (new weight coefficient) = (old weight coefficient) + (error value) ×
(The value of the signal using the weighting factor). In the above equation, when the weighting coefficient and the signal value are represented by probability densities (when it is desired to know the jth weighting coefficient or the value of the jth signal, the value around the position j is averaged to obtain the value. Therefore, it is not necessary to return the correction value of the weighting coefficient for the position j to the position j exactly, but it is sufficient to return it to the position j. However, since the signal itself is 1 bit, it is necessary to search for a position where overflow does not occur. As described above, the present invention is a method of returning a correction value around the position j while searching for a position that does not overflow.

FIG. 1 is a block diagram for explaining an embodiment (claims 1 to 5) of an adaptive filtering circuit according to the present invention. FIGS. 2 (a) to 2 (g) show signals of respective parts of FIG. Shows,
2A is a basic block, FIG. 2B is a signal RAM rewrite trigger, FIG. 2C is a signal RAM, FIG. 2D is a latch B rewrite trigger, and FIG. 2E is a latch B. 2 (f) shows the coefficient RAM, and FIG. 2 (g) shows the latch A.
In the figure, 1 is a ΔΣ (delta sigma) modulator, 2 is a counter, 3 is a signal RAM, 4 is a 1/6 coefficient unit, 5 is a monomulti, 6 is a counter, 7 is a coefficient RAM, and 8 is a latch (B ), 9 is a 1/9 coefficient unit, 10 is a monomulti, 11 is a clock generator, and 12 is a latch (A).

In the following description, it is assumed that both the input signal and the output signal are low-pass filtered to the control target frequency. Further, the error signal is assumed to be a 1-bit signal of TTL level via the comparator. Further, although the oversampling ratio is 3 and the tap length is 6 for simplification of description, the oversampling ratio and the tap length are not limited to these.

The counters 2 and 6 connected to the signal RAM 3 and the coefficient RAM 7 cyclically count the same length as the tap length. The clock speed is the speed at which the clock signal is generated L times in one oversampling. Although the counter 2 on the signal RAM side and the counter 7 on the coefficient RAM side operate in synchronization, the clock signal is not input only once per oversampling on the signal RAM side.

Error signal and past signal data (signal RA
A value for rewriting the coefficient RAM 7 is generated from M). This value continues to be written every clock until the coefficient RAM 7 becomes unwritable. The write permission of the coefficient RAM 7 is set each time a rewrite value is prepared, but when the value in the coefficient RAM 7 is different from the rewrite value (that is, the value in the coefficient RAM is changed by writing the rewrite value. Hour) and it is not writable. In the figure, a new rewrite value is set once every 9 clocks, but by changing this frequency, the speed and accuracy of adaptation can be changed.

FIG. 3 is a block diagram for explaining another embodiment (claims 6 and 7) of the adaptive filtering circuit according to the present invention. FIGS. 4 (a) to 4 (h) are signals of respective parts of FIG. 4A shows a basic block, and FIG. 4B shows a signal RA.
M rewrite trigger, FIG. 4 (c) is a signal RAM, FIG. 4 (d) is an up (UP) / down (DOWN) counter trigger,
4E is BOLLOW, FIG. 4F is an SR flip-flop, FIG. 4G is a coefficient RAM WE, and FIG.
Indicate the coefficient RAMs.

In the figure, 13 is an up / down counter, 1
4 is an SR flip-flop, 15 is a latch, and other parts having the same functions as those in FIG. For simplicity of explanation, the oversampling ratio is 3,
The tap length is 6, but the oversampling ratio,
The tap length is not limited to this.

The counters 2 and 6 connected to the signal RAM 3 and the coefficient RAM 7 cyclically count the same length as the tap length. The clock speed is the speed at which the clock signal is generated L times in one oversampling. The counter 2 on the signal RAM side and the counter 6 on the coefficient RAM side operate in synchronization, but the clock signal is not input only once per oversampling on the signal RAM side.

Error signal and past signal data (signal RA
A value for rewriting the coefficient RAM 7 is generated from M), and is counted by the UP / DOWN counter 13 every clock. The UP / DOWN counter 13 is adapted to count a numerical value up to 6, for example, and outputs a CARRY signal and a BOLLOW signal in the case of overflow or underflow. As a result, the coefficient RA
The write permission of M7 occurs, and the rewrite value is set at the same time. As in FIG. 1, the write permission of the coefficient RAM 7 is reset when the value in the coefficient RAM 7 is different from the rewrite value (that is, when the value in the coefficient RAM 7 is changed by writing the rewrite value), and writing is disabled. Become. By changing the count size of the UP / DOWN counter 13, the speed and accuracy of adaptation can be changed.

[0039]

As is apparent from the above description, the present invention has the following effects. (1) Effect corresponding to claim 1: When the input signal is filtered by an unknown system and observed as the first output signal, the input signal is filtered using the filter to generate the second output signal The method, the second
In an adaptive filtering circuit that updates the filter so that the difference between the output signal and the first output signal becomes smaller, the input signal is oversampled as a 1-bit probability density signal, and the second output is output. Signal and first
By inputting the difference between the output signals of 1 as a 1-bit signal, the circuit can be configured with a relatively simple 1-bit AD converter, which leads to downsizing and cost reduction. (2) Effect corresponding to claim 2 By using the delta-sigma modulation method as a 1-bit probability density modulation method, an accurate signal can be obtained in the signal band. (3) Effect corresponding to claim 3: By using a 1-bit probability density signal as the filter, it is possible to configure internal filtering calculation by 1-bit signal processing, which leads to circuit miniaturization and low It leads to cost reduction. (4) Effect corresponding to claim 4: When it is desired to adapt the i-th value of the filter in the positive (or negative) direction as an adaptive method of the filter, it is closest to the position i and is in the positive (or negative) direction. By searching for and updating the filter position j whose value can be changed, adaptive signal processing using a 1-bit signal becomes possible. (5) Effect corresponding to claim 5: When the adaptation is desired to be performed quickly, the filter update position is selected densely, and when it is desired to be performed accurately, the filter update position is roughly selected. The adaptive speed can be controlled in the adaptive signal processing using the 1-bit signal described in (4) above. (6) Effect corresponding to claim 6: As a method of adapting a filter, a value to be adapted and a sum signal of x times the filter coefficient string are delta-sigma modulated to form a new filter coefficient string. Adaptive signal processing using bit signals becomes possible. (7) Effect corresponding to claim 7: When the adaptation is desired to be performed quickly, the value of x is decreased, and when it is desired to be performed with high accuracy, the value of x is increased. The adaptive speed can be controlled in the adaptive signal processing using the 1-bit signal.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of an adaptive filtering circuit according to the present invention.

FIG. 2 is a diagram showing signals of respective parts of FIG.

FIG. 3 is a configuration diagram for explaining another embodiment of the adaptive filtering circuit according to the present invention.

FIG. 4 is a diagram showing signals of respective parts of FIG.

[Explanation of symbols]

1 ... ΔΣ (delta sigma) modulator, 2 ... counter, 3
... Signal RAM, 4 ... 1/6 coefficient unit, 5 ... Monomulti, 6
... counter, 7 ... coefficient RAM, 8 ... latch (B), 9 ...
1/9 coefficient unit, 10 ... Monomulti, 11 ... Clock generator, 12 ... Latch (A), 13 ... Up / down counter, 14 ... SR flip-flop, 15 ... Latch.

Claims (7)

[Claims] 1. When an input signal is filtered by an unknown system and observed as a first output signal, the input signal is filtered with a filter to produce a second output signal, the second output signal In the adaptive filtering circuit that updates the filter so that the difference between the output signal and the first output signal becomes small,
Oversampled as a probability density signal of bits,
An adaptive filtering circuit, wherein the difference between the second output signal and the first output signal is sampled as a 1-bit signal. 2. The adaptive filtering circuit according to claim 1, wherein a delta-sigma modulation system is used as the 1-bit probability density modulation system. 3. The adaptive filtering circuit according to claim 1, wherein the filter is a 1-bit probability density signal. 4. When the i-th value of the filter is to be applied in the positive or negative direction as the adaptive method of the filter, the filter position is closest to the position i and the value can be changed in the positive or negative direction. The adaptive filtering circuit according to claim 1, wherein j is searched and updated. 5. The filter update position is selected densely when the adaptation is desired to be performed quickly, and the filter update position is roughly selected when the adjustment is desired to be performed accurately. Adaptive filtering circuit as described. 6. The filter adaptation method according to claim 1, wherein a value to be adapted and a sum signal of x times the filter coefficient string are delta-sigma modulated to form a new filter coefficient string. Adaptive filtering circuit. 7. The adaptive filtering circuit according to claim 6, wherein the value of x is reduced when the adaptation is performed quickly, and the value of x is increased when the adaptation is performed with high accuracy.