JPH08182330A - Power converter - Google Patents

Power converter

Info

Publication number
JPH08182330A
JPH08182330A JP33883794A JP33883794A JPH08182330A JP H08182330 A JPH08182330 A JP H08182330A JP 33883794 A JP33883794 A JP 33883794A JP 33883794 A JP33883794 A JP 33883794A JP H08182330 A JPH08182330 A JP H08182330A
Authority
JP
Japan
Prior art keywords
current
output
voltage
multiplier
waveform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33883794A
Other languages
Japanese (ja)
Other versions
JP3216068B2 (en
Inventor
Toshimasa Tanizaki
谷崎俊正
Akio Imayanada
明夫 今柳田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Electric Manufacturing Ltd
Original Assignee
Toyo Electric Manufacturing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Electric Manufacturing Ltd filed Critical Toyo Electric Manufacturing Ltd
Priority to JP33883794A priority Critical patent/JP3216068B2/en
Publication of JPH08182330A publication Critical patent/JPH08182330A/en
Application granted granted Critical
Publication of JP3216068B2 publication Critical patent/JP3216068B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE: To enable a power converter to have a lagged-phase current which offsets a leading current generated from a capacitor by adding a sinusoidal waveform which is lagged in phase by a specific angle and the output of a multiplier to a reference sinusoidal waveform and using the sum as the input current commanding value of a capacitor output section. CONSTITUTION: The second output waveform of a reference sinusoidal waveform generating section 76 given to a multiplier 77c is lagged in phase from a reference sinusoidal waveform by 90 deg.C. The phase of the second output waveform is lagged from that of the current 1c of a capacitor 5 by 180 deg.C. The sum of a waveform ILAG* obtained by multiplying the second output waveform by an appropriate coefficient and another waveform Id* is found by means of an adder 77b and the sum is used as the new input current command 1* of a capacitor output section 4. The input current IL4 of the section 4 following the command 1* has the same waveform as the command 1* has and this current IL4 is composed of the leading current flowing to the capacitor 5 and the opposite-phase current ILAG. A lagged-phase current which offsets the leading current can be generated by making the gain Ic of the multiplier 77c a little larger.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、交流電圧を直流電圧
に、あるいは直流電圧を交流電圧に変換し、かつ交流電
流を交流電圧に対して力率1の正弦波となるよう制御す
る電力変換装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter for converting an AC voltage into a DC voltage or a DC voltage into an AC voltage and controlling an AC current into a sine wave having a power factor of 1 with respect to the AC voltage. It relates to the device.

【0002】[0002]

【従来の技術】従来の電力変換装置としての正弦波コン
バータの構成および制御方法を図4に示す。図中、1は
交流電源、2はコンバータ装置、3はモータ駆動用や無
停電電源装置用のインバータ回路、蓄電池などの直流負
荷回路である。コンバータ装置2は、半導体スイッチン
グ素子からなるコンバータ出力部4、コンデンサ5、リ
アクトル6、制御回路7、電流検出器8から成る。ここ
で、コンデンサ5およびリアクトル6はフィルタ回路を
構成している。制御回路7は直流電圧制御部71、基準正
弦波発生部72、電流指令部73、電流制御部74、ゲート増
幅部75から成る。
2. Description of the Related Art FIG. 4 shows the configuration and control method of a conventional sine wave converter as a power converter. In the figure, 1 is an AC power supply, 2 is a converter device, 3 is an inverter circuit for driving a motor or an uninterruptible power supply device, and a DC load circuit such as a storage battery. The converter device 2 includes a converter output unit 4 including a semiconductor switching element, a capacitor 5, a reactor 6, a control circuit 7, and a current detector 8. Here, the capacitor 5 and the reactor 6 form a filter circuit. The control circuit 7 includes a DC voltage control unit 71, a reference sine wave generation unit 72, a current command unit 73, a current control unit 74, and a gate amplification unit 75.

【0003】直流電圧制御部71はコンバータ装置2の直
流電圧を取り込み、加算器71aにより直流電圧設定信号
71bとの偏差を求め、さらに制御増幅器71cを介して電
圧制御信号を出力する。基準正弦波発生部72はコンバー
タ装置2の入力端子の電圧と位相が一致した一定振幅の
基準正弦波形を出力する。電流指令部73は掛け算器73a
から成り、直流電圧制御部71からの電圧制御信号と基準
正弦波発生部72からの基準正弦波形とを乗算することに
より位相がコンバータ装置2の入力端子電圧に一致しか
つ振幅が必要とする電流に比例した正弦波形が得られ、
この正弦波形がコンバータ出力部4の入力電流指令Id
*となる。電流制御部74は加算器74a、制御増幅器74b
から成る。ここで入力電流指令Id*波形と電流検出器
8より取り込んだ電流波形との偏差を加算器74aにより
求め、制御増幅器74b、ゲート増幅部75を介してコンバ
ータ出力部4へ送ることにより、コンバータ出力部4の
入力電流が入力電流指令Id*波形と同じになるように
制御できる。
The DC voltage control unit 71 takes in the DC voltage of the converter device 2 and uses the adder 71a to set the DC voltage setting signal.
The deviation from 71b is obtained, and the voltage control signal is output via the control amplifier 71c. The reference sine wave generator 72 outputs a reference sine waveform of constant amplitude whose phase matches the voltage of the input terminal of the converter device 2. The current command unit 73 is a multiplier 73a
The current required for the phase to match the input terminal voltage of the converter device 2 and the amplitude by multiplying the voltage control signal from the DC voltage control unit 71 by the reference sine waveform from the reference sine wave generation unit 72. A sinusoidal waveform proportional to
This sine waveform is the input current command Id of the converter output unit 4.
* The current controller 74 includes an adder 74a and a control amplifier 74b.
Consists of. Here, the deviation between the input current command Id * waveform and the current waveform fetched from the current detector 8 is obtained by the adder 74a and sent to the converter output unit 4 via the control amplifier 74b and the gate amplifying unit 75, whereby the converter output The input current of the unit 4 can be controlled to be the same as the input current command Id * waveform.

【0004】図4におけるコンバータ装置2と交流電源
との関係を等価回路で表したものが図5であり、1aは
交流電源1の等価回路、4aはコンバータ部4の等価回
路、9は交流電源1とコンバータ装置2との間の配線イ
ンピダンスあるいは電源インピダンスである。図6に、
図5の等価回路から求めた各部の電圧・電流のベクトル
図を示す。図6中の各記号は図5中に矢印に添えて示し
た記号を示す。図5、図6とも実線矢印は電流、一点鎖
線矢印は電圧を示す。コンバータ装置2の入力端子電圧
であるコンデンサ5の電圧Vcを基準にしてみると、コ
ンデンサ5にはVcより90度進み位相の電流Icが流
れる。
FIG. 5 shows the relationship between the converter device 2 and the AC power supply in FIG. 4 by an equivalent circuit. 1a is an equivalent circuit of the AC power supply 1, 4a is an equivalent circuit of the converter unit 4, and 9 is an AC power supply. 1 is a wiring impedance between the converter 1 and the converter device 2 or a power source impedance. In Figure 6,
The vector diagram of the voltage / current of each part obtained from the equivalent circuit of FIG. 5 is shown. The symbols in FIG. 6 are the symbols shown with the arrows in FIG. In both FIGS. 5 and 6, the solid line arrow indicates current, and the alternate long and short dash line arrow indicates voltage. When the voltage Vc of the capacitor 5, which is the input terminal voltage of the converter device 2, is used as a reference, a current Ic having a phase leading by 90 degrees from Vc flows through the capacitor 5.

【0005】図4においては掛け算器73aの出力である
コンバータ出力部4の入力電流指令Id*は前述のよう
にコンデンサ5の電圧Vcとまったく位相が一致してお
り、コンバータ出力部4の入力電流およびリアクトル6
の電流IL4もコンデンサ5の電圧Vcと同位相となる。
電源1aおよびリアクトル9にはコンデンサ5の電流I
cとコンバータ出力部4への電流IL4との和の電流IL2
が流れる。この電流IL2はコンデンサ5の電圧Vcより
90度位相の進んだ電流Icの成分により、コンデンサ5
の電圧Vcより進み位相の電流となる。コンデンサ5の
電圧Vcと電源1aの起電圧Eとの位相差は小さいの
で、電源1aおよび配線等のリアクトル9に流れる電流
IL2は、図6に示すように電源1aの起電圧Eから見る
と、進み位相となる。
In FIG. 4, the input current command Id * of the converter output section 4, which is the output of the multiplier 73a, has exactly the same phase as the voltage Vc of the capacitor 5 as described above, and the input current of the converter output section 4 is the same. And reactor 6
The current IL4 of is also in phase with the voltage Vc of the capacitor 5.
The current I of the capacitor 5 is applied to the power source 1a and the reactor 9.
current IL2 which is the sum of c and the current IL4 to the converter output unit 4
Flows. This current IL2 is more than the voltage Vc of the capacitor 5.
Due to the component of the current Ic which leads the phase by 90 degrees, the capacitor 5
The voltage becomes a phase leading current from the voltage Vc. Since the phase difference between the voltage Vc of the capacitor 5 and the electromotive voltage E of the power source 1a is small, the current IL2 flowing in the reactor 9 such as the power source 1a and the wiring is as follows when viewed from the electromotive voltage E of the power source 1a as shown in FIG. The phase is advanced.

【0006】[0006]

【発明が解決しようとする課題】電源がコンバータ装置
の容量に対して充分余裕のある場合には電源に流れる電
流の位相は問題とならないが、電源が発電機で、しかも
容量的に余裕のない場合には、発電機に進み電流を流す
と、発電機が自己励磁を起こし、出力電圧を上昇させ、
過大な電圧を出力してしまう。その電圧は通常電圧の
1.5倍に達することもあり、装置を過電圧により破損
させてしまう恐れがある。また、電源電流の力率が進ん
だり遅れたりして力率が1よりも低下し、無効電力が発
生すると、その分大きな電源設備容量が必要となり不経
済になる。
When the power source has a sufficient margin with respect to the capacity of the converter device, the phase of the current flowing through the power source does not matter, but the power source is a generator and the capacity is not sufficient. In this case, when a current is passed through the generator, the generator causes self-excitation and raises the output voltage.
Outputs excessive voltage. The voltage can reach 1.5 times the normal voltage, which may damage the device due to overvoltage. Further, if the power factor of the power supply current is advanced or delayed and the power factor is reduced to less than 1, and reactive power is generated, a large power supply facility capacity is required, which is uneconomical.

【0007】[0007]

【課題を解決するための手段】かような不具合を回避す
るために、本発明は、交流電源の電圧と位相の一致した
基準正弦波形を出力する基準正弦波発生部、出力直流電
圧と設定信号との偏差を増幅する直流電圧制御部、基準
正弦波発生部と直流電圧制御部の出力を入力とする掛け
算器、掛け算器の出力をコンバータ出力部の入力電流指
令値とする電力変換装置において、基準正弦波形に対し
て、90度位相の遅れた正弦波形と掛け算器出力を加算
し、その出力をコンバータ出力部の入力電流指令値とす
るものである。
In order to avoid such a problem, the present invention provides a reference sine wave generator for outputting a reference sine wave whose phase matches the voltage of an AC power supply, an output DC voltage and a setting signal. A DC voltage control unit that amplifies the deviation between, a multiplier that receives the output of the reference sine wave generator and the DC voltage control unit, and a power converter that uses the output of the multiplier as the input current command value of the converter output unit, A sine waveform delayed by 90 degrees and a multiplier output are added to the reference sine waveform, and the output is used as the input current command value of the converter output section.

【0008】また、基準正弦波形より90度位相の遅れた
正弦波形と交流電源電圧値との積と、掛け算器出力を加
算し、その出力をコンバータ出力部の入力電流指令値と
することによっても同様に不具合を解消することができ
る。
Alternatively, the product of the sine waveform delayed by 90 degrees in phase from the reference sine waveform and the AC power supply voltage value is added to the multiplier output, and the output is used as the input current command value of the converter output section. Similarly, the problem can be resolved.

【0009】[0009]

【作用】このようにすることにより、コンバータ出力部
の入力電流指令Id*は常にコンデンサによる進み電流
Icを打ち消すような遅れ電流の成分を持ち、電源に対
して進み電流が流れることを阻止でき、かつ電源電流の
力率を1にすることができる。
By doing so, the input current command Id * of the converter output section always has a delay current component that cancels the advance current Ic due to the capacitor, and it is possible to prevent the advance current from flowing to the power source. Moreover, the power factor of the power supply current can be set to 1.

【0010】[0010]

【実施例】図1に本発明の第1の実施例による構成を示
す。図1中、7’は制御回路、76は基準正弦波発生部、
77は電流指令部、77aは掛け算器、77bは加算器、77c
は倍率器を示す。なお、図4と同じ符号を付したものは
同じものを示す。ここに、掛け算器77aは図4の掛け算
器73aと同一である。基準正弦波発生部72と基準正弦波
発生部76の相違点は基準正弦波発生部76が第2の出力を
出すようになっており、かつこの出力が基準正弦波より
も位相が90度遅れた波形である点である。 この波形
は、回路的には基準正弦波をフィルタ回路により位相を
遅らせたり、マイクロコンピュータのソフトウェア処理
により正弦波を表すデータテーブルの読み込むポイント
をずらせることにより容易に求めることができる。ま
た、3相交流電源の場合には、例えばR相より90度遅れ
た波形は、S相の電圧または基準正弦波と、T相の電圧
または基準正弦波との差を求めることにより、ソフトウ
ェアにても回路にても求めることができる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration according to the first embodiment of the present invention. In FIG. 1, 7'is a control circuit, 76 is a reference sine wave generator,
77 is a current command unit, 77a is a multiplier, 77b is an adder, 77c
Indicates a multiplier. The same reference numerals as those in FIG. 4 indicate the same elements. Here, the multiplier 77a is the same as the multiplier 73a of FIG. The difference between the reference sine wave generator 72 and the reference sine wave generator 76 is that the reference sine wave generator 76 outputs a second output, and this output is delayed by 90 degrees in phase from the reference sine wave. It is a point that has a corrugated waveform. In terms of circuitry, this waveform can be easily obtained by delaying the phase of the reference sine wave by a filter circuit or shifting the reading point of the data table representing the sine wave by software processing of a microcomputer. In the case of a three-phase AC power supply, for example, if the waveform delayed by 90 degrees from the R phase, the difference between the S phase voltage or the reference sine wave and the T phase voltage or the reference sine wave is calculated by software. You can ask for it either in the circuit or in the circuit.

【0011】電流指令部73と電流指令部77との相違点
は、電流指令部77が掛け算器のほかに加算器77b、倍率
器77cを含む点である。基準正弦波発生部76の第2の出
力は倍率器77cに入力され、倍率器77cの出力と掛け算
器77aの出力は、加算器77bで加算する。このようにす
ることにより、基準正弦波形より90度位相が遅れた波形
に、倍率器77cによりコンデンサ5による進み電流の値
に応じた係数を掛け、加算器77bにて従来のコンバータ
出力部4の入力電流指令Id*に加算し、新たな入力電
流指令I*とする。
The difference between the current command unit 73 and the current command unit 77 is that the current command unit 77 includes an adder 77b and a multiplier 77c in addition to the multiplier. The second output of the reference sine wave generator 76 is input to the multiplier 77c, and the output of the multiplier 77c and the output of the multiplier 77a are added by the adder 77b. By doing so, the waveform whose phase is delayed by 90 degrees from the reference sine waveform is multiplied by the multiplier 77c by a coefficient according to the value of the advance current due to the capacitor 5, and the adder 77b is used to convert the conventional converter output unit 4 The new input current command I * is added to the input current command Id *.

【0012】本実施例による各部の電圧電流のベクトル
図を図2に示す。図2中、図6と同じ符号を付したもの
は同じものを示す。図2中、従来例と同様に、直流電圧
制御部71の出力と基準正弦波発生部76からの基準正弦波
形とを掛け算器77aにより乗算して得られた波形は、位
相が入力端子電圧に一致し、かつ直流電圧制御に必要と
する電流の振幅に比例した正弦波形であり、この正弦波
形のベクトルはId*となる。この正弦波形は純粋に直
流電圧制御に必要な電流成分である。また、倍率器77c
に与えられる基準正弦波発生部76の第2の出力波形は基
準正弦波形より90度位相が遅れた波形であり、コンデン
サ5の電流Icからみれば180度位相が逆の波形であ
る。この波形に倍率器77cにより適切な係数を掛けた波
形ILAG *とId*との和を加算器77bにより求め、新
たなコンバータ出力部4の入力電流指令I*する。
FIG. 2 shows a vector diagram of the voltage and current of each part according to this embodiment. In FIG. 2, the same symbols as those in FIG. 6 denote the same components. In FIG. 2, as in the conventional example, the waveform obtained by multiplying the output of the DC voltage control unit 71 and the reference sine waveform from the reference sine wave generation unit 76 by the multiplier 77a has the phase at the input terminal voltage. It is a sine waveform that matches and is proportional to the amplitude of the current required for DC voltage control, and the vector of this sine waveform is Id *. This sine waveform is purely a current component required for DC voltage control. Also, a multiplier 77c
The second output waveform of the reference sine wave generator 76 given to the above is a waveform whose phase is delayed by 90 degrees from the reference sine waveform, and is a waveform whose phase is 180 degrees opposite to that of the current Ic of the capacitor 5. The adder 77b obtains the sum of the waveforms ILAG * and Id * obtained by multiplying this waveform by an appropriate coefficient by the multiplier 77c, and gives a new input current command I * for the converter output section 4.

【0013】この入力電流指令I*によるコンバータ出
力部4の入力電流IL4はI*と同じ波形であり、この電
流は純粋に直流電圧を制御するために必要な成分IR
と、コンデンサ5に流れる進み電流IC と逆位相の電流
ILAG とからなる電流である。したがって、ILAG がI
cよりも等しいかあるいは若干大きめになるように倍率
器77cのゲインを設定することにより、コンバータ装置
の入力電流IL2を純粋に直流電流制御に必要な成分のみ
にし、装置の入力端子電圧Vcに対して同位相か若干遅
れ位相気味にすることができる。図2は、IL2を装置の
入力端子電圧Vcに対し若干遅れ気味にした例である。
このとき、電源電流IL2は電源や発電機からみた位相も
遅れとなるので発電機が自己励磁を起こさず、過大な電
圧を発生することを防ぐことができる。
The input current IL4 of the converter output unit 4 according to this input current command I * has the same waveform as I *, and this current is a component IR necessary for purely controlling the DC voltage.
And a leading current IC flowing through the capacitor 5 and a current ILAG having an opposite phase. Therefore, ILAG is I
By setting the gain of the multiplier 77c so as to be equal to or slightly larger than c, the input current IL2 of the converter device is made purely only the component necessary for the direct current control, and the input terminal voltage Vc of the device is It is possible to have the same phase or slightly delayed phase. FIG. 2 shows an example in which IL2 is slightly delayed with respect to the input terminal voltage Vc of the device.
At this time, the phase of the power supply current IL2 seen from the power supply and the generator is also delayed, so that the generator does not cause self-excitation and it is possible to prevent generation of an excessive voltage.

【0014】図3に本発明の第2の実施例を示す。図3
中、7”は制御回路、79は電源電圧の大きさを検出する
電源電圧値検出器である。ここに、図1の倍率器77cが
掛算器78dに置き換えられ、基準正弦波発生部76からの
第2の出力と電源電圧値検出器79の出力とが乗算されて
いる。つまり、倍率器77cの倍率を可変にし、電源電圧
値に比例した倍率としている。なお、図1と同一符号を
付したものは同じものを表す。 また、掛け算器78aは掛
け算器73a、掛け算器77aと同一である。
FIG. 3 shows a second embodiment of the present invention. FIG.
7 ”is a control circuit, and 79 is a power supply voltage value detector for detecting the magnitude of the power supply voltage. Here, the multiplier 77c of FIG. 1 is replaced with a multiplier 78d, and a reference sine wave generator 76 is provided. 2 is multiplied by the output of the power supply voltage value detector 79. That is, the magnification of the multiplier 77c is made variable so that the magnification is proportional to the power supply voltage value. Further, the multiplier 78a is the same as the multiplier 73a and the multiplier 77a.

【0015】第1の実施例においては、コンデンサ5に
よる進み電流Icを打ち消すための遅れ電流指令ILAG
*は一定であった。しかし、コンデンサ5による進み電
流Icは電源電圧Vcの大きさに比例して変化する。し
たがって、遅れ電流指令ILAG *が一定ではある電源電
圧の状態ではコンデンサ5による進み電流と遅れ電流I
LAG は丁度打ち消し合い、電源電流IL2は電源電圧と同
位相となるが、電源電圧Vcが変化しコンデンサ5によ
る進み電流が増減すると、電源電流IL2の位相は電源電
圧Vcとずれてしまい、力率1が保てない。特に、電源
電圧Vcが上昇しコンデンサ5の進み電流が大きくなっ
た時には電源電流IL2は電源電圧Vcに対して進みとな
り、前述の不具合が発生する。また、最大の電源電圧に
対しても電源電流IL2が電源電圧Vcに対して遅れ電流
となるように遅れ電流指令ILAG *を大きく設定する
と、通常の電源電圧では電源電流IL2は電源電圧Vcか
らの遅れが大きくなり、電源力率が低下し、大きな電源
容量を必要としてしまう。かくの如き不具合を解消する
ため、第2の実施例では、遅れ電流指令ILAG *を電源
電圧の大きさに比例して変化させ、図2中の遅れ電流I
LAG を、常にコンデンサ5による進み電流Icを丁度打
ち消す大きさに制御する。これにより、電源電流IL2を
常に電源電圧Vcと同位相となるようにすることができ
る。
In the first embodiment, the delay current command ILAG for canceling the advance current Ic by the capacitor 5 is used.
* Was constant. However, the lead current Ic due to the capacitor 5 changes in proportion to the magnitude of the power supply voltage Vc. Therefore, under the condition of the power supply voltage in which the delay current command ILAG * is constant, the advance current and the delay current I by the capacitor 5 are
The LAGs cancel each other out, and the power supply current IL2 has the same phase as the power supply voltage. However, if the power supply voltage Vc changes and the advance current due to the capacitor 5 increases or decreases, the phase of the power supply current IL2 deviates from the power supply voltage Vc, and the power factor I can't keep 1. In particular, when the power supply voltage Vc rises and the advance current of the capacitor 5 becomes large, the power supply current IL2 advances with respect to the power supply voltage Vc, and the above-mentioned problem occurs. Further, if the delay current command ILAG * is set to a large value so that the power supply current IL2 is a delay current with respect to the power supply voltage Vc even with respect to the maximum power supply voltage, the power supply current IL2 is larger than the power supply voltage Vc at the normal power supply voltage. The delay becomes large, the power supply power factor decreases, and a large power supply capacity is required. In order to eliminate such a problem, in the second embodiment, the delay current command ILAG * is changed in proportion to the magnitude of the power supply voltage, and the delay current I in FIG.
The LAG is always controlled to a value that just cancels the leading current Ic due to the capacitor 5. As a result, the power supply current IL2 can always be in phase with the power supply voltage Vc.

【0016】[0016]

【発明の効果】以上説明したように本発明によれば、直
流電圧制御に必要な電源電圧との位相が一致した電流指
令に加えて、コンデンサの進み電流を打ち消すような遅
れ電流成分をオフセットとして重畳してコンバータ電流
指令とすることにより電源電流が進み位相となることを
防ぐことができ、発電機の自己励磁を防ぎ、発電機が過
大な電圧を発生し、コンバータ装置や負荷装置に損害を
与えることを防ぐことができ、厳しい電源環境において
も安定した動作が行える電力変換装置を提供することが
できる。さらに、遅れ電流成分のオフセットの大きさを
電源電圧の大きさに比例して変化させることにより、電
源電圧変動に対しても常に電源の力率を1に保ち電源設
備容量を有効に活用できる。
As described above, according to the present invention, in addition to the current command in phase with the power supply voltage required for DC voltage control, a delay current component for canceling the advance current of the capacitor is used as an offset. By superimposing the converter current command, it is possible to prevent the power supply current from advancing and becoming in phase, prevent self-excitation of the generator, generate excessive voltage in the generator, and damage the converter device and load device. It is possible to provide a power conversion device that can be prevented from being given and can perform stable operation even in a severe power supply environment. Furthermore, by changing the magnitude of the offset of the lagging current component in proportion to the magnitude of the power supply voltage, the power factor of the power supply can always be kept at 1 even when the power supply voltage changes, and the power supply equipment capacity can be effectively utilized.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は本発明の第1の実施例を示す回路構成で
ある。
FIG. 1 is a circuit configuration showing a first embodiment of the present invention.

【図2】図2は第1の実施例による各部のベクトル図で
ある。
FIG. 2 is a vector diagram of each part according to the first embodiment.

【図3】図3は本発明の第2の実施例を示す回路構成で
ある。
FIG. 3 is a circuit configuration showing a second embodiment of the present invention.

【図4】図4は従来の回路構成例である。FIG. 4 is an example of a conventional circuit configuration.

【図5】図5は1相分の等価回路である。FIG. 5 is an equivalent circuit for one phase.

【図6】図6は従来例による各部のベクトル図である。FIG. 6 is a vector diagram of each unit according to a conventional example.

【符号の説明】[Explanation of symbols]

1 交流電源 2 コンバータ装置 3 直流負荷回路 4 コンバータ出力部 5 コンデンサ 6 リアクトル 7 制御回路 7’ 制御回路 7” 制御回路 8 電流検出器 9 リアクトル 71 直流電圧制御部 71a 加算器 71b 直流電圧設定信号 71c 制御増幅器 72 基準正弦波発生部 73 電流指令部 73a 掛け算器 74 電流制御部 74a 加算器 74b 制御増幅器 75 ゲート増幅部 76 基準正弦波発生部 77 電流指令部 77a 掛け算器 77b 加算器 77c 倍率器 78 電流指令部 78a 掛け算器 78b 加算器 78d 掛け算器 79 電源電圧値検出器 1 AC power supply 2 Converter device 3 DC load circuit 4 Converter output unit 5 Capacitor 6 Reactor 7 Control circuit 7'Control circuit 7 "Control circuit 8 Current detector 9 Reactor 71 DC voltage control unit 71a Adder 71b DC voltage setting signal 71c Control Amplifier 72 Reference sine wave generator 73 Current command unit 73a Multiplier 74 Current controller 74a Adder 74b Control amplifier 75 Gate amplifier 76 Reference sine wave generator 77 Current command unit 77a Multiplier 77b Adder 77c Multiplier 78 Current command Part 78a Multiplier 78b Adder 78d Multiplier 79 Power supply voltage value detector

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 交流電源の電圧と位相の一致した基準正
弦波形を出力する基準正弦波発生部、出力直流電圧と設
定信号との偏差を増幅する直流電圧制御部、基準正弦波
発生部と直流電圧制御部の出力を入力とする掛け算器、
該掛け算器の出力をコンバータ出力部の入力電流指令値
とする電力変換装置において、前記基準正弦波形に対し
て90度位相の遅れた正弦波形と前記掛け算器出力を加算
し、その出力をコンバータ出力部の入力電流指令値とす
るよう構成したことを特徴とする電力変換装置。
1. A reference sine wave generator that outputs a reference sine wave whose phase matches the voltage of an AC power supply, a DC voltage controller that amplifies the deviation between the output DC voltage and a setting signal, a reference sine wave generator, and a direct current. A multiplier that receives the output of the voltage controller
In a power converter that uses the output of the multiplier as the input current command value of the converter output section, a sine waveform delayed by 90 degrees with respect to the reference sine waveform and the multiplier output are added, and the output is the converter output. An electric power converter configured to use an input current command value of a section.
【請求項2】 交流電源の電圧と位相の一致した基準正
弦波形を出力する基準正弦波発生部、出力直流電圧と設
定信号との偏差を増幅する直流電圧制御部、基準正弦波
発生部と直流電圧制御部の出力を入力とする掛け算器、
該掛け算器の出力をコンバータ出力部の入力電流指令値
とする電力変換装置において、前期基準正弦波形に対し
て90度位相の遅れた正弦波形と交流電源電圧値との積
と、前記掛け算器出力を加算し、その出力をコンバータ
出力部の入力電流指令値とするよう構成したことを特徴
とする電力変換装置。
2. A reference sine wave generator that outputs a reference sine waveform whose phase matches the voltage of the AC power supply, a DC voltage controller that amplifies the deviation between the output DC voltage and the setting signal, a reference sine wave generator and a DC. A multiplier that receives the output of the voltage controller
In a power converter that uses the output of the multiplier as the input current command value of the converter output section, the product of the sine waveform delayed by 90 degrees in phase with the reference sine waveform and the AC power supply voltage value, and the multiplier output Is added and the output thereof is set as the input current command value of the converter output section.
JP33883794A 1994-12-27 1994-12-27 Power converter Expired - Fee Related JP3216068B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33883794A JP3216068B2 (en) 1994-12-27 1994-12-27 Power converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33883794A JP3216068B2 (en) 1994-12-27 1994-12-27 Power converter

Publications (2)

Publication Number Publication Date
JPH08182330A true JPH08182330A (en) 1996-07-12
JP3216068B2 JP3216068B2 (en) 2001-10-09

Family

ID=18321896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33883794A Expired - Fee Related JP3216068B2 (en) 1994-12-27 1994-12-27 Power converter

Country Status (1)

Country Link
JP (1) JP3216068B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012143045A (en) * 2010-12-28 2012-07-26 Kawasaki Heavy Ind Ltd Control device of synchronous motor, and control device of synchronous generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012143045A (en) * 2010-12-28 2012-07-26 Kawasaki Heavy Ind Ltd Control device of synchronous motor, and control device of synchronous generator

Also Published As

Publication number Publication date
JP3216068B2 (en) 2001-10-09

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