JPH08182017A - Digital video signal recording and reproducing device - Google Patents

Abstract

PURPOSE: To prevent image quality from deteriorating when a signal of the EDTV-2 or a signal of the PAL(phase alternating by line) plus is recorded on a digital VTR employing a compression recording system. CONSTITUTION: Aspect ratio information, an identification signal and a confirmation signal in a video signal of the EDTV-2 (extended definition TV) system are sent to lines 22, 285. When the video signal is compressed and recorded, a signal of the line 285 being a valid line is fixed to a pedestal level. In the case of a video signal of the PALplus, a WSS signal is sent to a line 23. In the case of compressing and recording the video signal, a signal of the line 23 being a valid line is fixed to a pedestal level. Thus, the deterioration in the image quality is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is particularly applicable to ED-TV2.
, PALplus, etc. are transmitted in letterbox format,
The present invention relates to a digital video signal recording device for recording a composite color video signal in which a signal for reinforcing resolution is sent to a non-screen portion or a main screen portion.

[0002]

2. Description of the Related Art In recent years, a broadcasting system, such as EDTV-2, which is designed to have high image quality and a wide screen while maintaining compatibility with television signals of NTSC system or PAL system.
A method and a PALplus method have been proposed. That is, the current NTSC system and PAL system have an aspect ratio of 4: 3. On the other hand, on a wide screen, the aspect ratio is 16: 9 or 14: 9,
The screen is horizontally long compared to the current screen. EDT
The V-2 system and the PALplus system are designed to be able to display a high quality image when displaying a 16: 9 wide screen on a television receiver and also to display the current 4: 3 television. Is.

These EDTV-2 system and PALplus
The method is based on a letterbox type screen. As shown in FIG. 21, the letterbox type is such that the screen is projected in the center and there is no screen above and below the screen. For example, in the case of the NTSC system, a video signal is placed on 360 lines in the central part of the screen, and the 60 lines above and below are not screened. As a result, a 16: 9 horizontally long screen is formed.

[0004] In the case of the EDTV-2, as shown in FIG. 22, the top and bottom of the screen of the letter box, V _T and V _H signal is multiplexed, H _H signal is multiplexed on the main screen portion. The V _T signal is a vertical high frequency component lost in the process of interlacing when an image signal captured by double speed non-interlacing is transmitted by interlacing. V _H signal is 1
It is a vertical luminance high frequency component which is lost when a 6: 9 image signal is made into a letter box type. In other words, when transmitting in the letterbox type, the number of scanning lines is reduced from 480 to 360 in the NTSC system, and the vertical resolution is degraded to about 3/4. The V _H signal reinforces the vertical luminance high frequency component which is lost at this time. The H _H signal is a horizontal luminance high frequency component of 4.2 MHz to 6 MHz. The H _H signal is frequency-shifted and multiplexed in the blowhole in the main screen.

In the case of EDTV-2, as shown in FIG. 23, lines 22 and 285 are provided with NRZ signals (B1 to B4) indicating the aspect ratio, and then V _T ,
Identification signal indicating the presence or absence of V _H and H _H signal components (each of V _T , V _H , and H _H signal components is modulated by the color sub-carrier and is 0 phase or π phase with respect to the color sub-carrier) Is provided), and finally, a 2.04 MHz confirmation signal for identifying the EDTV-2 is provided.

In the case of the PALplus system, as shown in FIG. 24, a helper signal for reinforcing the vertical resolution is multiplexed above and below the letterbox screen. In the case of the PALplus system, as shown in FIG. 25, a WSS (Wide Screen Signal) indicating the aspect ratio and the presence / absence of a helper signal on the line 23 is displayed.
ng) signal is provided and a helper signal is further provided, in the latter half of the line, the subcarrier frequency (4.4
3 MHz) reference burst signal is provided.
Further, the reference signal indicating the level of 100% white is sent to the line 623.

The applicant of the present application prepares for the broadcasting of the EDTV-2 system and the PALplus system by using the digital VTR of the compression recording system, and the EDTV-2 system and the PALpl system.
We have proposed a device that can record us signals.

That is, a compression recording type digital VTR
Then, the signal of ED-TV2 is compressed by the digital V
When recording in TR, the V _T and V _H signals sent to the upper and lower non-screen portions of the screen are treated and recorded as luminance signals. The H _H signal of the main screen portion is decoded, multiplexed with the luminance signal of the main screen portion, and recorded. Line 22,
The aspect ratio information of 285 is unchanged, the identification signal is decoded, and these pieces of information are stored as VAUX data (video preliminary data).

When recording a PALplus video signal, a helper signal sent to the upper and lower non-screen portions of the screen is demodulated, treated as a luminance signal and recorded. The WSS signal on the line 23 is extracted from the PALplus signal, and the data of this WSS signal is stored as VAUX data.

By the way, in the digital VTR, only the effective screen is extracted and compression-coded, and the data in the vertical blanking period and the horizontal blanking period are dropped. In the compression type digital VTR as described above, NTSC is used.
In the case of the system (525-60 system), as shown in FIG. 26, the lines 23 to 262 in the field 1 and the lines 285 to 524 in the field 2 are defined as effective lines. Also, the PAL system (625-50 system)
27, in the case of field 1, lines 23-310 in field 1 and lines 335-6 in field 2
22 is defined as an effective line.

When the effective line is determined in this way, NTS
In the case of the C system (525-60 system), the line 22
The image signals of 0.5H on line 263 and 525 are lost, and in the case of the PAL system, the image signal of 0.5H on line 623 is lost. However, since these lost image signals are hidden positions at the top and bottom of the screen in the current television system having an aspect ratio of 4: 3, there is no practical problem.

[0012]

However, when the effective line is set in this way, in the case of the EDTV-2 system, the line 285 becomes the effective line. This line 28
A signal indicating the aspect ratio of EDTV-2, an identification signal indicating the presence / absence of each signal component, and a confirmation signal of 2.04 MHz (FIG. 23) are sent to 5.

In the case of the PALplus system, the line 23 is the effective line. The line 23 has a WSS signal (FIG. 2) indicating the aspect ratio and the presence / absence of a helper signal.
5) and the reference signal are sent.

Thus, the line 285 of the EDTV-2 is
If the line 23 of the PALplus system is in the valid screen, the following problems occur.

First, the signal on the line 285 of the EDTV-2 and the signal on the line 23 of the PALplus contain a signal related to subcarriers. These signals are treated as chroma signal components and recorded in the digital VTR. The compression type digital VTR is recorded at 4: 1: 1 or 4: 2: 0, and the amount of information assigned to the chroma signal is small. If these signals are recorded as the chroma signal, the original chroma signal is recorded. As a result, the color reproducibility is significantly deteriorated.

The NRZ signal is contained in these lines. Since the NRZ signal contains a wide range of frequency components from DC to a very high frequency band, the compression effect by DCT is small. For this reason, a coarse quantization table is used in the quantization, and the image quality deteriorates.

Furthermore, when a signal indicating the presence or absence of a signal for reinforcing the aspect ratio and resolution stored in VAUX is added at the time of reproduction, if the line to be inserted is an effective line, it is recorded at the time of recording. EDTV-2 when not only the data restored from the VAUX data but also the data compressed / recorded / expanded and reproduced as the real screen due to the clock phase difference between the EDTV-2
The decoder or PALplus decoder may malfunction.

Therefore, the object of the present invention is to provide an EDTV.
-2 signal or PALplus signal is recorded,
It is an object of the present invention to provide a digital video signal recording device which prevents deterioration of image quality.

[0019]

SUMMARY OF THE INVENTION The present invention is a digital video signal transmitted in a letterbox format, and a composite color video signal in which a signal for enhancing resolution is multiplexed in a non-screen portion is compressed and recorded in a recording medium. In the recording device, the effective portion of the video signal is extracted, the effective portion of the video signal is compressed and recorded, and the data sent to a predetermined line is saved as spare data, and the predetermined line to which the data is sent. Is included in the effective portion, the digital video signal recording apparatus is characterized in that the signal of a predetermined line is set to a fixed level.

The present invention relates to a digital video signal reproducing apparatus for reproducing a recording medium on which a composite color video signal transmitted in a letterbox format and having a resolution enhancing signal multiplexed therein is compressed and recorded. , Expand and play the effective part of the video signal,
The data sent to a predetermined line is reproduced from the spare data, and the data of the predetermined line reproduced from the spare data is added to the effective portion of the expanded video signal. It is a digital video signal reproducing device.

[0021]

In the EDTV-2 video signal, the line 22,
At 285, the aspect ratio information, the identification signal, and the confirmation signal are sent. Of the lines 22 and 285, the line 285 is a valid line. When the video signal is compressed and recorded, the signal on the line 285 is fixed to the pedestal level, for example.

In the PALplus video signal, the WSS signal is sent to the line 23. This line 23 is on the effective line. When the video signal is compressed and recorded, the signal on the line 23 is fixed to, for example, the pedestal level.

As described above, EDTV-2 and PALplus
In s, when the line to which the information indicating the aspect ratio and the like is sent is in the effective screen, the signal of this line is fixed to the pedestal level, for example. As a result, deterioration of image quality can be prevented.

[0024]

Embodiments of the present invention will be described in the following order.
This will be described with reference to the drawings. a. Overall configuration for EDTV-2 b. EDTV-2 recording processing circuit c. Digital VTR recording system for EDTV-2 d. Digital VTR playback system for EDTV-2 e. EDTV-2 reproduction processing circuit f. Overall configuration in case of PALplus g. PALplus recording processing circuit h. Digital VTR recording and playback systems for PALplus i. PALplus playback processing circuit

A. Overall Configuration of EDTV-2 FIGS. 1 and 2 show an embodiment in which a signal of the EDTV-2 is recorded and reproduced. In FIG. 1, 1 is a tuner, 2 is an EDTV-2 recording processing circuit, and 3 is a digital VTR. The tuner 1 receives the EDTV-2 system signal. For the EDTV-2 signal, for example, V is displayed above and below the screen.
_T and V _H signal is multiplexed, H _H signal is multiplexed on the main screen portion. Then, a signal indicating the aspect ratio, an identification signal indicating the presence / absence of each signal component of V _T , V _H , and H _H , and a signal of 2.04 MHz for identifying the EDTV-2 are provided on the lines 22 and 285. And a confirmation signal of. The received signal of the EDTV-2 system is supplied to the EDTV-2 recording processing circuit 2.

The EDTV-2 recording processing circuit 2 processes an EDTV-2 system signal so that the digital VTR 3 can record the EDTV-2 signal. The EDTV-2 recording processing circuit 2 decodes the H _H signal of the main screen portion, multiplexes it with the luminance signal of the main screen portion, and at the same time, V _T and V _H sent to the non-screen portions above and below the screen.
An offset is added to the signal so that it can be recorded as a luminance signal. At the same time, the identification signal sent to the lines 22 and 285 is decoded from the signal of the EDTV-2, and the data indicating the presence / absence of each signal component of the aspect ratio, V _T , V _H , and H _H is extracted. The digital VTR3 is
Since the processing is performed at the sampling frequency of 13.5 MHz, it is possible to record up to a band of about 6 MHz. EDTV
The −2 recording processing circuit 2 outputs the component color signals Y, C _R , and C _{B, which} are supplied to the digital VTR 2. Further, the aspect ratio, the data regarding the presence / absence of each signal component of V _T , V _H , and H _H , and the color phase information are sent to the digital VTR 3.

The digital VTR 3 digitizes the component color signals Y, C _R and C _B , compresses them using DCT and a variable length code, and records them on a magnetic tape by a rotary head. When recording the EDTV-2 signal, the EDTV-2 recording processing circuit 2 gives data such as the aspect ratio and the presence / absence of each signal component of V _T , V _H , and H _H , and these are digitalized. VAU on VTR3
It is saved as X data. At this time, in this embodiment,
Since the H _H signal is decoded and the signal is restored in the band of 6 MHz, the H _H signal is stored as no signal.
When recording a video signal with the digital VTR 3, only the effective portion is extracted. Of the lines 22 and 285 to which the identification signal and the like are sent, the line 22 is outside the valid line, but the line 285 is inside the valid line. In this embodiment, the signal on line 285 is replaced with a pedestal level signal. As a result, these signals are not recorded as an effective screen, and deterioration of color reproducibility and deterioration of image quality are prevented.

FIG. 2 shows the structure of the reproducing system.
In FIG. 2, component color video signals Y, C _R and C _B are output from the digital VTR 5. The component color video signals Y, C _R and C _B are
As described above, the luminance signal reproduced from the main screen is H
_{The H} signal is a multiplexed signal, and the luminance signals of the upper and lower non-screen portions of the screen are V _T and V _H to which an offset is added.
It is a signal. This component color video signal Y,
C _R, is C _B is supplied to the EDTV-2 reproduction processing circuit 6. Further, from the VAUX data, the digital VTR 5 outputs data such as the aspect ratio, the presence / absence of each signal component of V _T , V _H , and H _H , and the color phase data. These data are supplied to the EDTV-2 reproduction processing circuit 6.

The EDTV-2 reproduction processing circuit 6 removes the offsets of the V _T and V _H signals in the non-screen portion. Further, data of the aspect ratio, an identification signal indicating the presence or absence of each signal component of V _T , V _H , and H _H , and a confirmation signal of 2.04 MHz for identifying the EDTV-2 are generated, These are multiplexed on line 22 and line 285.

The output of the EDTV-2 reproduction processing circuit 6 is supplied to the wide-screen television receiver 7. The television receiver 7 has an EDTV-2 decoder. The television receiver 7 decodes the EDTV-2 system signal and displays it on the television screen.

In this embodiment, the luminance signal is returned to the band of 6 MHz. In a normal composite video input or S input, the band of 6 MHz can be transmitted from the digital VTR 3 as it is, so that high quality can be obtained without any processing.

B. EDTV-2 Recording Processing Circuit FIG. 3 is an example of the EDTV-2 recording processing circuit 2. In FIG. 3, an EDTV-2 signal is supplied to the input terminal 11. The signal from the input terminal 11 is supplied to the three-dimensional Y / C separation circuit 12. The luminance signal Y and the chroma signal C are separated by the three-dimensional Y / C separation circuit 12. At the same time, the three-dimensional Y / C separation circuit 12 extracts the signal multiplexed in the blow-out hole and supplies it to the H _H signal demodulation circuit 13. In H _H signal demodulating circuit 13, H _H signal which has been multiplexed to the Fukinuki hole is demodulated. This H
_From the output of the _H signal demodulation circuit 13, the frequency 4.2 to 6 MH
A high frequency horizontal luminance component of z is obtained. The output of the H _H signal demodulation circuit 13 is supplied to the addition circuit 14.

From the Y / C separation circuit 12, the frequency 4.2.
A luminance signal Y up to MHz and a chroma signal C are output. The luminance signal Y is supplied to the adding circuit 14. In the adding circuit 14, the luminance signal Y up to the frequency of 4.2 MHz is
The high frequency horizontal luminance component of frequency 4.2 to 6 MHz from the H _H signal demodulation circuit 13 is added. The output of the adder circuit 14 is supplied to the terminal 15A of the switch circuit 15. The chroma signal from the Y / C separation circuit 12 is supplied to the switch circuit 16.

The signal from the input terminal 11 is supplied to the offset adding circuit 17 and the identification signal decoding circuit 18. Further, the sync signal in the signal from the input terminal 11 is detected by the sync separation circuit 20. The output of the sync separation circuit 20 is supplied to the line decoder 21. The output of the line decoder 21 is supplied to the identification signal decoding circuit 18 and the switch control circuit 22.

The offset adding circuit 17 gives an offset to the V _T and V _H signals sent to the non-image portion so that they can be processed as luminance signals. The output of the offset adding circuit 17 is the terminal 15 of the switch circuit 15.
Supplied to B.

The identification signal detection circuit 18 has lines 22, 2
Data on the presence / absence of the aspect ratio, V _T , V _H , and H _H signal components sent to 85 are detected. The output of the identification signal detection circuit 13 is output from the data output terminal 19. The state of the three-dimensional Y / C separation circuit 12 is set according to the identification signal detected by the identification signal detection circuit 18.

The switch control circuit 22 forms a switch control signal for switching between the main screen portion and the non-screen portion. This switch control signal is supplied to the switch circuits 15 and 16. By this switch control signal, the switch circuit 15
And 16 are switched between the main screen and the non-screen.

That is, in the main screen portion in the center of the screen, the switch circuit 15 is set to the terminal 15A side and the switch circuit 16 is turned on. In the upper and lower non-screen portions, the switch circuit 15 is set to the terminal 15B side and the switch circuit 16 is turned off. Therefore, the switch circuit 15 outputs the luminance signal Y to which the horizontal high-frequency component H _H is added in the main screen portion, and the vertical resolution enhancement signals V _T and V _H to which the offset is added in the non-screen portion. Is output. The chroma signal C is output from the switch circuit 16 in the main screen portion, and no signal is output in the non-screen portion.

The output of the switch circuit 15 is output from the output terminal 23. The output of the switch circuit 16 is the color demodulation circuit 2
4 is supplied. The color demodulation circuit 24 demodulates the color difference signals C _R and C _B from the chroma signal C. This color difference signal C _R ,
C _B is output from the output terminals 25 and 26.

C. Digital VT for EDTV-2
R Recording System FIG. 4 shows the configuration of the recording system of the digital VTR 3. In FIG. 4, component color video signals Y, C _R and C _B are supplied to input terminals 31, 32 and 33. This component color video signal Y,
C _R and C _B are supplied to the A / D converter 34. A /
The D converter 34 receives the component signals Y, C _R , and C.
_B is digitized with a sampling clock having a frequency of 13.5 MHz. In the case of the NTSC system, the color difference signals C _R , C for the information amount 4 of the luminance signal Y
The information amount of _B is set to 1 and digitized by so-called 4: 1: 1. The output of the A / D converter 34 is supplied to the masking circuit 38.

Further, the input video signal is a sync separation circuit 35.
Is supplied to. The sync separation circuit 35 detects the sync signal. The output of the sync separation circuit 35 is the line decoder 3
6. The output of the line decoder 36 is supplied to the masking signal generation circuit 37. The masking signal generation circuit 37 is supplied from the controller 30 with a signal indicating whether the signal is of the EDTV-2 system. The masking signal generation circuit 37 generates a masking signal on the line 285 when an EDTV-2 system signal is input. This masking signal is supplied to the masking circuit 38.

The masking circuit 38 allows the EDTV-2
When the system signal is input, the signal on the line 285 is masked to a predetermined value (for example, the value 16 indicating the pedestal level).

The output of the masking circuit 38 is supplied to the effective information extraction circuit 39. In the valid information extraction circuit 39, the data outside the valid screen such as the vertical blanking period and the horizontal blanking period is dropped, and only the data within the valid screen is extracted. Here, the effective line is field 1
Line 23-262 and Field 2 285
Lines to 524 lines. In the EDTV-2, the data of the aspect ratio, the identification signal such as the presence or absence of each signal component of V _T , V _H , and H _H , and the confirmation signal of 2.04 MHz for identifying the EDTV-2 line are provided. Two
2 and line 285, but line 22 is not in the valid line and is removed here. Line 2
Although the value 85 is within the effective line, it is replaced with the pedestal level by the masking circuit 38.

The output of the effective information extraction circuit 39 is supplied to the blocking and shuffling circuit 40. The blocking and shuffling circuit 40 blocks into (8 × 8) blocks, the compression is averaged over the entire screen, and data is intensively lost due to head clogs or tape damage. Shuffling is done to prevent this.

The output of the blocking and shuffling circuit 40 is supplied to the compression circuit 41. The compression circuit 41 is DC
The video data is compressed by T conversion and variable length coding. That is, the compression circuit 41 uses a DCT conversion circuit, a quantizer for quantizing the DCT-converted data, an estimator for estimating the total code amount and determining an optimum quantizer, and a two-dimensional Huffman code. And a variable length coding circuit for compressing data. Compression circuit 41
Then, the (8 × 8) time domain data is converted into (8 × 8) frequency domain coefficient data, which is quantized and variable length coded.

The output of the compression circuit 41 is the framing circuit 42.
Is supplied to. In the framing circuit 42, video data is packed in a predetermined sync block according to a predetermined rule. The output of the framing circuit 42 is the VAUX addition circuit 43.
Is supplied to.

VAUX data is supplied from the VAUX generation circuit 44 to the VAUX addition circuit 43. VAUX
The generation circuit 44 receives data VA from the controller 30.
UX data is given. VA with the VAUX addition circuit 43
The video data added with the UX data is supplied to the multiplexer 45.

At the terminal 46, from the EDTV-2 recording processing circuit 2 (FIG. 3), aspect ratio data, identification signal data (whether or not each signal component of V _T , V _H , H _H , etc.), color phase information are obtained. Is supplied. The VAUX data generated from the VAUX generation circuit 44 includes these data.

Specifically, the TR shown in FIG. 12 is added to VAUX.
A pack (header 66h) is provided, and the data of the identification signal is recorded in this TR pack. Also, the aspect ratio information is the DISP (Display Se) of the VAUX source control pack (header PC0 = 61h).
Lect Mode). In addition, a source pack whose color phase information is VAUX (header PC0 =
60h) CLF (Color Frame Iden)
It is recorded as a specification code).

An audio signal is supplied to the input terminal 47. This audio signal is supplied to the A / D converter 48. The A / D converter 48 digitizes the audio signal. This audio signal is supplied to the audio signal processing circuit 49. The audio processing circuit 49 packs the audio data in a predetermined sync block. The output of the audio signal processing circuit 49 is supplied to the AAUX adding circuit 50.

Under the control of the controller 30, the AAUX generating circuit 51 supplies the AAUX adding circuit 50 with A
AUX data is provided. With the AAUX additional circuit 50,
AAUX data is added to the audio data. The audio data to which the AAUX data is added is supplied to the multiplexer circuit 45.

The subcode generating circuit 52 generates a subcode. The subcode data is used during high speed search. This subcode data is supplied to the multiplexer circuit 45.

The multiplexer circuit 45 switches between video data, audio data, and subcode data. The output of the multiplexer circuit 45 is supplied to the error correction coding circuit 54. The error correction coding circuit 54 adds an error correction code to the recorded data.
The output of the error correction coding circuit 54 is the channel code 55.
Is supplied to. Channel coder 55 has 2 recorded data
4/25 converted. Here, the coding process of partial response class 4 suitable for digital recording is further performed. The output of the channel coder 55 is supplied to the head 56 via a recording amplifier (not shown).

In the video track, as shown in FIG.
Tracks are formed. At the beginning of each track, ITI
An area is provided, followed by an audio area, a video area, and a subcode area.
The ITI area is a timing block for surely performing post-recording, and is used for accurately performing positioning when post-recording and rewriting data written in subsequent areas. Audio data is recorded in the audio area. Compressed video data is recorded in the video area. The sub code area is used for high speed search. When recording NTSC format data,
One video frame is recorded with 10 tracks.

6 and 7 show the structure of data in the audio area. As shown in FIG. 6, one sync block is composed of 90 bytes. The first 5 bytes of the data part are presync and postsync, and the data part is 77 bytes (72 bytes of audio data and AA
UX5 bytes). Data part is horizontal parity C
It is protected by 1 (8 bytes) and vertical parity C2 (5 sync blocks). As shown in FIG. 7, 14 sync blocks are arranged per track. The first 5 bytes of the data section are for AAUX. One pack consists of these 5 bytes.

8 and 9 show the structure of data in the video area. One sync block in the video area is composed of 90 bytes. The first 5 bytes of the data part are presync and postsync, and the data part is 77 bytes. As shown in FIGS. 8 and 9, it is protected by a horizontal parity C1 (8 bytes) and a vertical parity C2 (11 sync blocks).

FIG. 9 shows a vertical arrangement of 149 sync blocks in the video sector. As shown in FIG. 9, the upper two sync blocks and the two sync blocks immediately before the C2 parity are reserved for VAUX. VAUX
For video data and C2 parity. In FIG. 9, 135 sync blocks in the central portion are the storage areas for video signals. In the figure, BUF0 to BU
F26 indicates a buffering unit, respectively. One buffering unit is composed of 5 sync blocks, and one track includes 27 buffering units. There are 270 buffering units for 1 video frame and 10 tracks. That is, an area effective as an image is extracted from the image data of one frame, sampled and collected 270
Individual groups are formed. One group is one buffering unit.

For each buffering unit, data compression is attempted by DCT conversion, quantization, variable length coding, etc.
It is evaluated whether the generated code amount is equal to or less than the target data. Then, a quantization step is determined so that the amount of generated data is less than or equal to the target, and actual encoding is performed using this quantization step. Then, the generated encoded data is packed in one buffering unit and five sync blocks.

FIG. 10 shows the data structure of the sub code area. The sub-code area is composed of 12 sync blocks, as shown in FIG. One sync block is 12 bytes, which is shorter than one sync block in the video area or audio area. This is to enable high speed search. At the beginning of one sync block, a 1-byte presync and postsync are provided. Following this, 3 bytes of ID data consisting of ID0 and ID1 and IDP which is a parity for ID0 and ID1 are added. Next, a 5-byte main data area is provided, and 2-byte parity is further added. The main data area stores the time code, recording date, etc. necessary for high-speed search.

As shown in FIGS. 10C and 10D, the ID
0 means F / for detecting an address during high-speed search.
An R flag is provided. Subsequently to this, as shown in FIG. 10C, in sync block numbers SB0 and SB6, application ID (AP
I3) is arranged, and the absolute track number is arranged so as to straddle the next ID1. For other sync block numbers, as shown in FIG. 11D, an F / R flag is provided, followed by an index ID, a skip ID,
A photo picture ID is provided, so that it straddles ID1.
An absolute track number is provided. The ID1 is provided with an absolute track number and a sync number.

Preliminary data AAUX of the audio area,
Preliminary data VAUX in the video area, subcode data, and data (not shown) in the cassette with memory are shown in FIG.
It is described by a common pack structure as shown in. The pack is basically composed of 5 bytes (PC0 to PC4), the first 1 byte is a header, and the remaining 4 bytes are data.

The header is divided into high-order 4 bits and low-order 4 bits to have two layers, and can further be extended to a layer below it by bit assignment of data. With this layering, the contents of the pack are clearly organized,
The expansion will be ready. Then, the space of 256 by the upper header and the lower header becomes a pack header table,
Prepared with the contents of the pack. Each area is described using this. The pack structure is basically 5 bytes, but as an exception, when writing a character in the cassette with memory, it has a variable length.

FIG. 12 shows a VAUX storing an identification signal.
2 shows the structure of the TR pack of FIG. TR pack is
The header byte PC0 is set to "66h". The data type (DATA TYPE) is 4 bits and distinguishes various signals. This data type (DATA TYPE)
Is defined as follows.

0000 = VBID 0001 = WSS 0010 = EDTV-2 in 22 lines 0011 = EDTV-2 in 285 lines 0100 = No Information Other = undefined

When the EDTV-2 signal is recorded, the TR pack stores the data of the identification signals of the line 22 and the line 285 as described above. The data part is prepared for 28 bits. Then, the data closer to the horizontal synchronizing signal is set as the LSB, and the data is sequentially packed.

FIG. 13 shows V where color phase information is stored.
1 shows the structure of an AUX source pack. In the source pack, the header byte PC0 is "60h".
A color frame identification code (CLF) is stored in the PC 1. Color frame identification code (CLF) is 5
In the 25/60 system, it is defined as follows.

00 = color frame A 01 = color frame B Others are reserved

Further, in the 625/50 system, it is defined as follows. 00 = first and second fields 01 = third and fourth fields 10 is fifth and sixth fields 11 = seventh and eighth fields

FIG. 14 shows the structure of a VAUX source control pack in which aspect ratio information is stored. The source control pack has a header byte P
C0 is set to "61h". The PC2 is provided with a display select mode (DISP). The display select mode (DISP) defines the aspect ratio as follows.

000 = 4: 3 normal 001 = 4: 3 letterbox 010 = 16: 9

D. Digital VT for EDTV-2
R Playback System FIG. 15 shows an example of the configuration of the playback system 5 of the digital VTR. In FIG. 15, the reproduction signal of the head 61 is transmitted through the reproduction amplifier (not shown) to the channel decoder 62.
Is supplied to. The reproduced signal is demodulated by the channel decoder 62. The output of the channel decoder 62 is supplied to the error correction circuit 63. By the error correction circuit 63,
Error correction processing is performed. The output of the error correction circuit 63 is supplied to the demultiplexer 64.

By the demultiplexer 64, the reproduction data of the audio area and the reproduction data of the video area,
It is separated from the reproduction data in the sub code area.

The reproduction data of the audio area is supplied to the audio processing circuit 67. Further, the AAUX data in the reproduced data in the audio area is detected by the AAUX decoding circuit 68. This AAUX data is supplied to the controller 60. The audio processing circuit 67 performs processing such as time axis conversion and interpolation. The output of the audio processing circuit 67 is supplied to the D / A converter 70. D
The output of the / A converter 70 is output from the output terminal 71.

The reproduction data of the video area is supplied to the deframe circuit 65. Further, the VAUX data in the reproduced data in the video area is detected by the VAUX decoding circuit 66. This VAUX data is supplied to the controller 60.

Data of the identification signals of the line 22 and the line 285 can be obtained from the VAUX TR pack. Color phase information is obtained from the VAUX source pack. Aspect information can be obtained from the VAUX source control pack. This information is
It is output from the data output terminal 79 and sent to the EDTV-2 reproduction processing circuit 6 (FIG. 6).

The reproduced data in the sub code area is detected by the sub code decoding circuit 69. This subcode data is supplied to the controller 60.

The output of the deframe circuit 65 is the expansion circuit 72.
Is supplied to. The decompression circuit 72 decodes the variable length code,
The inverse DCT conversion converts the compressed and recorded video signal into the original time domain video signal. The output of the decompression circuit 72 is supplied to the deshuffling and deblocking circuit 73. From deshuffling and deblocking circuit 73, the reproduction component color video signals Y, is C _R C _B obtained. The reproduction component color video signals Y, C _R C _B is supplied to the information adding circuit 74. The information adding circuit 74 is for adding a horizontal synchronizing signal, a vertical synchronizing signal, and the like. The output of the information adding circuit 74 is supplied to the D / A converter 75. The output of the D / A converter 75 is output from the output terminals 76, 77, 78.

When the video signal of the EDTV-2 is reproduced, in this embodiment, the reproduction luminance signal Y of the main screen portion has a frequency of 4.2 to 6 MHz in addition to the luminance signal up to the frequency of 4.2 MHz. The high-frequency luminance component of is added.
Further, the reproduction luminance signal Y of the non-screen portion is the V _T and V _H signals to which the offset is added. Further, from the data output terminal 79, aspect ratio information, color phase information,
The data regarding the presence / absence of each of the V _T , V _H , and H _H signal components is extracted. The line 22 for arranging the identification signal and the like is
Since it is outside the effective screen, it is at the pedestal level. Further, the line 285 is within the effective screen, but is replaced with the pedestal level by the masking circuit 38 of the recording system of the VTR.

E. EDTV-2 Playback Processing Circuit FIG. 16 shows the configuration of the EDTV-2 playback processing circuit 6. In FIG. 16, the reproduction luminance signal Y is supplied to the input terminal 81, and the reproduction color difference signals C _R and C _B are supplied to the input terminals 82 and 83. In addition, the data input terminal 84
, Aspect ratio information, color phase information, V _T , V _H ,
Data on the presence or absence of each signal component of H _H is given.

The reproduction luminance signal from the input terminal 81 is supplied to the switch circuit 85, and the sync signal of the input signal is detected by the sync separation circuit 86. Input terminals 82 and 8
The reproduced color difference signals C _R and C _B from the signal No. ₃ are supplied to the modulation circuit 90. In the modulation circuit 90, from the color difference signals C _R and C _B ,
A chroma signal C is formed. The output of the modulation circuit 90 is supplied to the switch circuit 91.

The output of the sync separation circuit 86 is supplied to the line decoder 87. The line decoder 87 decodes the number of lines. The output of the line decoder 87 is supplied to the switch control circuit 88, and the identification signal generating circuit 8
9. The switch control circuit 88 forms a switch control signal for switching between the main screen portion and the non-screen portion.
This switch control signal is supplied to the switch circuits 85 and 91. This switch control signal switches the switch circuits 85 and 91 between the main screen and the non-screen. That is, in the main screen portion in the center of the screen, the switch circuit 85
Is set to the terminal 85A side, and the switch circuit 91
Is turned on. In the upper and lower non-screen areas, the switch circuit 85
Is set to the terminal 85B side, and the switch circuit 91
Is turned off.

In the main screen portion, the switch circuit 85 is set on the side of the terminal 85A, and the signal from the input terminal 81 is supplied to the adding circuit 95 via the switch circuit 85.
The switch circuit 91 is turned on in the main screen portion. Therefore, the adder circuit 95 is supplied with the chroma signal C from the modulator circuit 90. The adder circuit 95 combines the luminance signal Y and the chroma signal C. The output of the adder circuit 95 is supplied to the adder circuit 97.

In the non-screen portion, the switch circuit 85 is connected to the terminal 8
The signal from the input terminal 81, which is set to the 5B side, is supplied to the offset removing circuit 96. Offset removal circuit 9
At 6, the offset is removed. The output of the offset removing circuit 96 is supplied to the adding circuit 97. Adder circuit 97
Is supplied to the adder circuit 98.

The data from the data input terminal 84 is supplied to the identification signal generating circuit 89. Identification signal generation circuit 89
Is supplied with the output of the line decoder 87. The identification signal generating circuit 89 generates the signals on the lines 22 and 285. That is, the identification signal generating circuit 89 is
And 285, the NRZ signal indicating the aspect ratio and V
An identification signal indicating the presence or absence of each signal component of _T , V _H , and H _H ;
2.04MH for identifying the EDTV-2
and a z confirmation signal. This signal is supplied to the adder circuit 98.

Lines 22 and 28 are added by adder circuit 98.
5, the NRZ signal indicating the aspect ratio, V _T ,
An identification signal indicating the presence or absence of each of the V _H and H _H signal components, and ED
A 2.04 MHz confirmation signal for identifying TV-2 is added. Thus, lines 22 and 2
When adding the signal to 85, the reproduced signals on the lines 22 and 285 were at the pedestal level, so that data can be added without error. The output of the adder circuit 98 is taken out from the output terminal 99.

The signal thus output is the EDT
Since it is a signal of the V-2 system, if it is supplied to a television receiver compatible with EDTV-2, a high quality playback screen can be enjoyed on a wide screen.

F. Overall Configuration for PALplus Next, the case of the PALplus system will be described. 17 and 18 show an example of recording a PALplus system signal.

In FIG. 17, 101 is a tuner and 10
2 is a PALpus recording processing circuit, 103 is a digital V
TR. The tuner 101 receives the PALplus signal. A helper signal for reinforcing the vertical resolution is multiplexed at the top and bottom of the screen in the PALplus signal. In the case of the PALplus system, the WSS indicating the aspect ratio and the presence / absence of the helper signal on the line 23.
When a (Wide Screen Signaling) signal is provided and a helper signal is further provided, the subcarrier frequency (4.43 MHz) is provided in the latter half of the line.
Reference burst signal is provided. Further, the reference signal indicating the level of 100% white is sent to the line 623. The received signal of this PALplus is PAL
It is supplied to the plus recording processing circuit 102.

The PALplus recording processing circuit 102 uses the PALplus so that the digital VTR 103 can perform recording.
It processes the plus signal. This PALpl
The us signal processing 102 decodes the helper signals sent to the upper and lower non-screen portions of the screen, adds an offset, and records them as a luminance signal. Along with this, the WSS signal sent to the line 23 is decoded from the PALplus signal, and aspect ratio information, information indicating the presence or absence of a helper signal, and the like are sent to the digital VTR 103.

The digital VTR 103 digitizes the component color signals Y, C _R and C _B, and outputs the DCT signal.
And a variable length code are used for compression, and recorded on a magnetic tape by a rotary head. Further, when recording the PALplus signal, data such as the aspect ratio and the presence / absence of the helper signal is given, and these are supplied to the digital VTR.
It is recorded as VAUX data 103. When recording a video signal with the digital VTR 103, only the effective portion is extracted. The line 23 to which the WSS signal is sent is in the valid line. In this embodiment, the signal on the line 23 is replaced with a pedestal level signal. As a result, these signals are not recorded as an effective screen, and deterioration of color reproducibility and deterioration of image quality are prevented.

FIG. 18 shows the structure of the reproducing system. In FIG. 18, from the digital VTR 105,
The component color video signals Y, C _R and C _B are output. This component color video signal Y,
C _R and C _B are supplied to the PALplus reproduction processing circuit 106. Also, from the digital VTR 105, VAU
Data indicating the presence or absence of a helper signal and the aspect ratio is output from the X data. These data are PALplus
It is supplied to the s reproduction processing circuit 106.

The PALplus reproduction processing circuit 106 removes the offset of the helper signal in the non-screen portion and modulates it. Further, data of the aspect ratio, a WSS signal indicating the presence or absence of a helper signal, and a reference signal are generated, and these are multiplexed on the line 23.

The output of the PALplus reproduction processing circuit 106 is supplied to the wide screen television receiver 107. The television receiver 107 is equipped with a PALplus decoder. Television receiver 107
Then, the signal of the EDTV-2 system is decoded, and this is displayed on the television screen.

G. PALplus Recording Processing Circuit FIG. 19 is an example of the PALplus recording processing circuit 102. In FIG. 19, PALplus is connected to the input terminal 111.
s signal is provided. The signal from the input terminal 111 is
It is supplied to the Y / C separation circuit 112. Y / C separation circuit 1
By 12, the luminance signal Y and the chroma signal C are separated. The luminance signal Y from the Y / C separation circuit 112 is supplied to the terminal 114A of the switch circuit 114. The chroma signal from the Y / C separation circuit 112 is supplied to the switch circuit 120.

Further, the signal from the input terminal 111 is supplied to the helper signal demodulation circuit 113, and at the same time, the WSSS signal is supplied.
It is supplied to the signal decoding circuit 116. Further, the sync signal in the signal from the input terminal 111 is detected by the sync separation circuit 117. The output of the sync separation circuit 117 is supplied to the line decoder 118. The output of the line decoder 118 is supplied to the WSS signal decoding circuit 116 and the switch control circuit 119.

The helper signal demodulation circuit 113 demodulates the helper signal. The output of the helper signal demodulation circuit 113 is supplied to the offset addition circuit 115. The offset adding circuit 115 can process as a luminance signal,
An offset is added to the demodulated helper signal. The output of the offset adding circuit 115 is supplied to the terminal 114B of the switch circuit 114.

The WSS signal detection circuit 116 uses the line 23
To detect the WSS signal sent to. The output of the WSS signal detection circuit 116 is output from the data output terminal 125.

The switch control circuit 119 forms a switch control signal for switching between the main screen portion and the non-screen portion. This switch control signal is supplied to the switch circuits 114 and 120. This switch control signal switches the switch circuits 114 and 120 between the main screen and the non-screen.

That is, in the main screen portion in the center of the screen, the switch circuit 114 is set to the terminal 114A side and the switch circuit 120 is turned on. In the upper and lower non-screen portions, the switch circuit 114 is set to the terminal 114B side and the switch circuit 120 is turned off. Therefore, the switch circuit 114 outputs the luminance signal Y in the main screen portion and the helper signal to which the offset is added in the non-screen portion. The chroma signal C is output from the switch circuit 120 in the main screen portion, and no signal is output in the non-screen portion.

The output of the switch circuit 114 is the output terminal 12
It is output from 2. The output of the switch circuit 120 is supplied to the color demodulation circuit 121. The color demodulation circuit 121 demodulates the color difference signals C _R and C _B from the chroma signal C. The color difference signals C _R and C _B are output from the output terminals 123 and 124.

H. Digital V for PALplus
TR recording / reproducing system Digital VT for recording / reproducing PALplus signals
The configurations of R103 and 105 are the same as in the case of recording the above-mentioned EDTV-2 signal. However, PALplus
When recording the s signal, the component color video signal is digitized at 4: 2: 0 by the A / D converter 34 in FIG. Further, the masking signal generation circuit 37 generates a masking signal on the line 23 and replaces the WSS signal on the line 23 with a pedestal level signal. Then, one video frame is recorded on 12 tracks. Further, WAUX data is recorded in the VAUX TR pack, and aspect ratio information is recorded in the VAUX source control pack.

I. PALplus Reproduction Processing Circuit FIG. 20 shows the configuration of the PALplus reproduction processing circuit 106. In FIG. 20, the reproduction luminance signal Y is supplied to the input terminal 131, and the reproduction color difference signals C _R and C _B are supplied to the input terminals 132 and 133. In addition, the data input terminal 134 is provided with aspect ratio information and data regarding the presence / absence of a helper signal.

The reproduction luminance signal from the input terminal 131 is supplied to the switch circuit 135, and the sync signal of the input signal is detected by the sync separation circuit 136. Input terminal 13
The reproduced color difference signals C _R and C _B from 2 and 133 are supplied to the modulation circuit 140. In the modulation circuit 140, the color difference signal C
_A chroma signal C is formed from _R and C _B. The output of the modulation circuit 140 is supplied to the switch circuit 141.

The output of the sync separation circuit 136 is supplied to the line decoder 137. The line decoder 137 decodes the number of lines. The output of the line decoder 137 is supplied to the switch control circuit 138 and the WSS signal generation circuit 139. Switch control circuit 13
Reference numeral 8 forms a switch control signal for switching between the main screen portion and the non-screen portion. This switch control signal is supplied to the switch circuits 135 and 141. This switch control signal switches the switch circuits 135 and 141 between the main screen and the non-screen. That is, in the main screen portion in the center of the screen, the switch circuit 135 is set to the terminal 135A side and the switch circuit 141 is turned on. In the upper and lower non-screen portions, the switch circuit 135 is set to the terminal 135B side and the switch circuit 141 is turned off.

In the main screen portion, the switch circuit 135 is set on the side of the terminal 135A, and the signal from the input terminal 131 is supplied to the adding circuit 142 via the switch circuit 135. The switch circuit 141 is turned on in the main screen portion. Therefore, the adder circuit 142 is supplied with the chroma signal C from the modulator circuit 140. Adder circuit 14
In 2, the luminance signal and the chroma signal are combined. The output of the adder circuit 142 is supplied to the adder circuit 143.

In the non-screen portion, the helper signal is supplied to the input terminal 131. This helper signal is supplied to the offset removing circuit 144 via the switch circuit 135. The offset removal circuit 144 removes the offset. The output of the offset removal circuit 144 is the modulation circuit 1
45. The helper signal is modulated by the modulation circuit 145. The output of the modulation circuit 145 is supplied to the addition circuit 143.

The data from the data input terminal 134 is W
It is supplied to the SS signal generation circuit 139. The output of the line decoder 137 is supplied to the WSS signal generation circuit 139. The WSS signal generation circuit 139 receives the WS signal on the line 23.
Generate an S signal. This signal is supplied to the adding circuit 146.

WS is added to the line 23 by the adder circuit 146.
The S signal is added. When adding a signal to line 23,
Since the reproduced signal on the line 23 is at the pedestal level, data can be added without error. The output of the adder circuit 146 is taken out from the output terminal 147. Since the signal thus output is a PALplus system signal, if it is supplied to the PALplus-compatible television receiver 107, a wide-screen, high-quality playback screen can be enjoyed.

[0109]

According to the present invention, in the video signal of the EDTV-2, the aspect ratio information, the identification signal, and the confirmation signal are sent to the lines 22 and 285. This line 2
Of the lines 2 and 285, the line 285 is an effective line. This line 2 is used when compressing and recording video signals.
85 signals are fixed at the pedestal level, for example. In addition, in the PALplus video signal, on line 23,
WSS signal is sent. This line 23 is on the effective line. This line 2 is used when compressing and recording video signals.
The signal of 3 is fixed to the pedestal level, for example. In this way, in the EDTV-2 or PALplus, when the line to which the information indicating the aspect ratio or the like is sent is in the effective screen, the signal of this line is fixed to the pedestal level, for example. As a result, deterioration of image quality can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram used for explaining a case of recording a signal of EDTV-2.

FIG. 2 is a block diagram used for explaining a case of reproducing a signal of EDTV-2.

FIG. 3 is a block diagram of an example of an EDTV-2 recording processing circuit.

FIG. 4 is a block diagram of a recording system of a digital VTR to which the present invention is applied.

FIG. 5 is a schematic diagram used for explaining a track configuration in a digital VTR to which the present invention is applied.

FIG. 6 is a schematic diagram used for explaining audio data in a digital VTR to which the present invention is applied.

FIG. 7 is a schematic diagram used for explaining audio data in a digital VTR to which the present invention is applied.

FIG. 8 is a schematic diagram used for explaining video data in a digital VTR to which the present invention is applied.

FIG. 9 is a schematic diagram used to explain video data in a digital VTR to which the present invention is applied.

FIG. 10 is a schematic diagram used for explaining subcode data in a digital VTR to which the present invention is applied.

FIG. 11 is a schematic diagram used to describe a pack structure.

FIG. 12 is a schematic diagram used to describe a pack.

FIG. 13 is a schematic diagram used to describe a pack.

FIG. 14 is a schematic diagram used to describe a pack.

FIG. 15 is a block diagram of a reproducing system of a digital VTR to which the present invention is applied.

FIG. 16 is a block diagram of an example of an EDTV-2 reproduction processing circuit.

FIG. 17 is a block diagram used for explaining a case of recording a PALplus signal.

FIG. 18 is a block diagram used for explaining a case of reproducing a PALplus signal.

FIG. 19 is a block diagram of an example of a PALplus recording processing circuit.

FIG. 20 is a block diagram of an example of a PALplus reproduction processing circuit.

FIG. 21 is a schematic diagram used to describe a letterbox format.

FIG. 22 is a schematic diagram used to describe an EDTV-2 signal.

FIG. 23 is a schematic diagram used to describe an EDTV-2 signal.

FIG. 24 is a schematic diagram used to describe a PALplus signal.

FIG. 25 is a schematic diagram used to describe a PALplus signal.

FIG. 26 is a schematic diagram used to describe an effective line in the 525/60 system.

FIG. 27 is a schematic diagram used for explaining an effective line in the 625/50 system.

[Explanation of symbols]

 2 EDTV-2 recording processing circuit 3, 5 digital VTR 6 EDTV-2 reproduction processing circuit 38 masking circuit

Claims (5)

[Claims] 1. A digital video signal recording apparatus for compressing and recording a composite color video signal, which is transmitted in a letterbox format and in which a signal for enhancing resolution is multiplexed in a non-screen portion, on a recording medium for recording. Extract the part, compress and record the video signal of the effective part, save the data sent to a predetermined line as preliminary data, and include the predetermined line to which the data is sent in the effective part. In this case, the digital video signal recording apparatus is characterized in that the signal on the predetermined line is set to a fixed level. 2. A composite color video signal transmitted in the letterbox format and having a resolution-enhancing signal multiplexed in a non-screen portion is an EDTV-2 signal, and the predetermined line to which the data is transmitted is 2. The digital video signal recording apparatus according to claim 1, wherein the signal of the predetermined line which is the line 22 and the line 285 and which has the fixed level is the signal of the line 285. 3. A composite color video signal transmitted in the letterbox format and having a signal for reinforcing resolution multiplexed in a non-screen portion is a PALplus signal,
The digital video signal recording apparatus according to claim 1, wherein the predetermined line to which the data is sent is the line 23, and the signal of the predetermined line which is the fixed level is the signal of the line 23. 4. The digital video signal recording apparatus according to claim 1, wherein the fixed level is a pedestal level. 5. A digital video signal reproducing apparatus for reproducing a recording medium recorded by compressing and recording a composite color video signal transmitted in a letterbox format, in which a signal for enhancing resolution is multiplexed in a non-screen portion. The effective part of the signal is expanded and reproduced, and the data sent to the predetermined line is reproduced from the spare data, and the expanded effective part of the video signal is the data of the predetermined line reproduced from the spare data. And a digital video signal reproducing device characterized by being added.