JPH0818024A - Amplification-type solid image pickup element and its manufacturing method - Google Patents

Abstract

PURPOSE:To suppress the scattering in element characteristics by forming an overflow barrier region by implanting a second conductive type impurity ion, forming a depletion layer stopper region by implanting a first conductive type impurity ion, and setting the ion concentration of the impurity to a distribution closer to normal distribution. CONSTITUTION:A p-type depletion layer stopper region with an ion implantation center position x1 is formed at a specific depth of a p-type silicon substrate 1. An n-type overflow barrier region with a position which is shallower than center position x1 as ion implantation center position x2 is formed. A p-type signal accumulation region 6 is formed at the surface part of the silicon substrate 1. A plane-ring-shaped gate electrode 3 is formed at a part which becomes a picture element at the upper part of the signal accumulation region 6 of the silicon substrate 1 via an insulation layer 2 and an n-type drain region 7D is formed around an n-type source region 7 and a gate electrode 3 at a part surrounded by the gate electrode 3 in the signal accumulation region 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification type solid-state image pickup device in which each pixel serving as a photoelectric conversion part has a gate electrode on a p-type semiconductor substrate via an insulating layer, and a method for manufacturing the same. Regarding the method.

[0002]

2. Description of the Related Art Recently, in response to a demand for higher resolution of solid-state image pickup devices, research on an internal amplification type solid-state image pickup device capable of amplifying optical signal charges as a configuration of each pixel to be a photoelectric conversion unit, Development is in progress.

The main components of the internal amplification type solid-state image pickup device are currently electrostatic induction transistors (SIT), amplification type MIS imagers (AMI), charge modulation devices (CM).
D), various image pickup devices such as a substrate charge modulation type imager are known.

Regarding the above-mentioned amplification type MIS imager (AMI), "Journal of the Television Society: 1075 to 108".
Page 2, vol-41, No. 11, 1987 ”, regarding the charge modulation device (CMD),
"Journal of the Television Society: 1047-1053, vo
l-41, No. 11, 1987 ”. Regarding the lateral static induction transistor, there is a prior art described in Japanese Patent Laid-Open No. 61-136388, and regarding the substrate charge modulation type imager, US Pat. 4,901,129 (Japanese Patent Laid-Open No. 64-149
59) and Japanese Patent Laid-Open No. 2-180071.

Here, a substrate charge modulation type imager will be mainly described as a typical example of the internal amplification type solid-state image pickup device. The configuration of each pixel arranged in a matrix in the image pickup region of the imager is as follows. As shown in FIG. 5, a gate electrode 103 made of, for example, a conductive polycrystalline silicon layer or a refractory metal silicide layer is formed on a p-type silicon substrate 101 with an insulating layer 102 made of SiO 2 or the like interposed therebetween. Has been done.

Specifically, the p-type silicon substrate 10 is used.
On the first depletion layer stopper region 104, a first p-type well region is formed, and an n-type well region as an island region surrounded by the depletion layer stopper region 104 is formed. Furthermore, the signal storage region 106 is surrounded by the overflow barrier region 105.
A second p-type well region is formed as an island region. Then, the signal storage region 1 of the silicon substrate 101
06, a planar ring-shaped gate electrode 103 is formed in a pixel portion via an insulating layer 102, and an n-type source region 107S is formed in a portion surrounded by the gate electrode 103 in the signal storage region 106. An n-type drain region 107D is formed around the gate electrode 103 to form a pixel of this substrate charge modulation type imager.

In the light receiving operation of this imager, first, in the charge accumulation period, for example, the source region 107S is at the ground potential, the drain region 107D is at the positive potential, and the gate electrode 103.
Is set to a negative potential having a large absolute value (that is, a low level potential). At this time, when light is incident on each pixel, photo-generated electrons are generated in the source region 107S, the drain region 107D or the overflow barrier region 10 depending on the generation position.
Outflow to 5. On the other hand, the photogenerated holes are stored in the p-type signal storage region 106.

Next, at the time of reading, the gate electrode 1
Negative potential whose absolute value is small in 03 (that is, high level potential)
Is applied. At this time, the effect of the back gate is added according to the charge amount of the photo-generated holes accumulated in the p-type signal accumulation region 106, whereby the surface charge of the silicon substrate 101 is modulated, and this modulated surface is obtained. The source / drain current changes depending on the amount of charges (the number of electrons) of, and as a result, it becomes possible to read according to the optical signal charges.

Here, a method of forming a pixel in the substrate charge modulation type imager will be described with reference to FIGS. 6 and 7.

First, as shown in FIG. 6A, p-type impurities such as boron (B) are diffused on the surface of the p-type silicon substrate 101. This diffusion is the silicon substrate 101.
Is placed in a furnace (temperature of 800 to 1200 ° C.) and an inert gas containing necessary impurities (boron (B) in this case) is caused to flow. At this time, the p-type silicon substrate 10
A p-type impurity introduction region 111 is formed on the surface of No. 1.

Next, as shown in FIG. 6B, the silicon substrate 101 is heat-treated at a temperature of about 1100 ° C. for about 24 hours in a nitrogen atmosphere. By this heat treatment, the p-type impurity introduction region 1 formed on the surface of the silicon substrate
P-type impurities are thermally diffused from 11 in the thickness direction of the silicon substrate 101 to form a first p-type well region having a large diffusion depth, that is, a p-type depletion layer stopper region 104.

Next, as shown in FIG. 6C, an n-type impurity such as phosphorus (P) is diffused into the surface of the depletion layer stopper region 104. This diffusion is performed on the silicon substrate 10.
1 is placed in a furnace (temperature of 800 to 1200 ° C.), and an inert gas containing necessary impurities (in this case, phosphorus (P)) is flowed. At this time, the depletion layer stopper region 10
An n-type impurity introduction region 112 is formed on the surface of No. 4.

Next, as shown in FIG. 7A, the silicon substrate 101 is heat-treated at a temperature of about 1100 ° C. for about 24 hours in a nitrogen atmosphere. By this heat treatment, n-type impurities are thermally diffused in the thickness direction of the silicon substrate 101 from the n-type impurity introduction region 112 formed on the surface of the depletion layer stopper region 104, and the diffusion depth is the above-mentioned depletion layer stopper region. An n-type well region shallower than 104, that is, an n-type overflow barrier region 105 is formed.

Next, as shown in FIG. 7B, p-type impurities such as boron (B) are formed on the surface of the silicon substrate 101.
To spread. At this time, the overflow barrier region 1
A second p-type well region, that is, a p-type signal storage region 106 is formed on the surface of 05.

After that, as shown in FIG. 5, an insulating layer 102 made of, for example, SiO 2 is formed on the silicon substrate 101 on which the various impurity diffusion regions are formed, and then a polycrystalline silicon layer or a refractory metal is formed on the entire surface. To form a silicide layer or polycide layer (hereinafter, simply referred to as a polycrystalline silicon layer or the like). After that, the polycrystalline silicon layer or the like is patterned to leave the polycrystalline silicon layer or the like at the portion corresponding to the pixel, and the gate electrode 103 is formed from the polycrystalline silicon layer or the like.

Next, using the gate electrode 103 as a mask, an n-type impurity, for example, phosphorus (P) is ion-implanted into the surface of the signal storage region 106 to form an n-type source region 107.
The S and drain regions 107D are formed. Thereafter, although not shown, various wiring layers are formed through an insulating layer, and a light-shielding layer made of an Al layer and a passivation film and a color filter layer are formed on the entire surface where the wiring layers are formed. A substrate charge modulation imager is produced.

[0017]

By the way, in the conventional substrate charge modulation type imager, the p-type depletion layer stopper region 104 and the n-type overflow barrier region 10 are used.
In order to form 5 at a deep position from the surface of the silicon substrate 101, the thermal diffusion method is used.

In summary of the above-mentioned manufacturing method, p-type impurities introduced into the surface of the silicon substrate 101 are diffused deep into the silicon substrate 101 by thermal diffusion to form a p-type depletion layer stopper region 104, and thereafter, silicon is formed. Board 101
The n-type impurities introduced into the surface of the n are diffused shallower than the depletion layer stopper region 104 by thermal diffusion to form the n-type overflow barrier region 105.

The carrier concentration distribution and the impurity concentration distribution with respect to the depth from the surface of the silicon substrate 101 in this case are shown in FIGS. 8A and 8B, respectively.

As shown in FIG. 8B, the n-type overflow barrier region 105 and the depletion layer stopper region 104 in this conventional substrate charge modulation type imager have n-type impurities (phosphorus (P)) and p-type impurities. It is formed by the difference in the impurity concentration distribution of (boron (B)). Specifically, since the impurity concentration of phosphorus (P) is higher than that of boron (B) from the lower end y1 to the depth y2 of the p-type signal storage region, this region in the depth direction (depth y1-y2
Region), the n-type carrier concentration becomes dominant, resulting in the formation of an n-type well region (n-type overflow barrier region 105) as shown in FIG. .

Next, a position y3 which is deeper than the depth y2.
Since the impurity concentration of boron (B) becomes higher than that of phosphorus (P), the region in the depth direction (depth y
2 to y3), the p-type carrier concentration becomes dominant, and as a result, a p-type well region (p-type depletion layer stopper region 104) is formed as shown in FIG. Will be.

As described above, the n-type overflow barrier region 105 and the p-type depletion layer stopper region 104 are formed.
Is formed by the difference in concentration distribution between the p-type impurity (boron (B)) and the n-type impurity (phosphorus (P)).

Therefore, slight variations in the manufacturing process, for example, ion implantation amounts of n-type impurities and p-type impurities,
If there are variations in implantation energy, temperature during thermal diffusion, time, etc., the carrier concentration in the overflow barrier region 105 and the depletion layer stopper region 104 is greatly affected, resulting in large variations in device characteristics after fabrication as a pixel. The problem of causing it occurs.

The n-type overflow barrier region 1
In order to form 05, phosphorus (P) introduced into the surface of the silicon substrate 101 increases the n-type impurity concentration on the surface of the silicon substrate 101 (FIG. 8).
(Refer to point a in (b)), the control range of the impurity concentration distribution of the signal accumulation region 106 using boron (B) formed thereafter is narrowed, and the p-type carrier concentration is controlled at a low concentration. Becomes difficult.

Further, in order for the p-type signal storage region 106 formed on the surface of the silicon substrate 101 to function as a charge modulation region, the p-type impurity concentration must be increased, and as a result, the background voltage is read during charge reading. In order to satisfactorily perform charge modulation by the gate effect, it is necessary to increase the gate potential applied to the gate electrode 103, which causes a problem that the tendency of reducing the drive power supply voltage cannot be dealt with.

The present invention has been made in view of the above problems. An object of the present invention is that the controllability of the impurity concentration of various impurity diffusion regions formed in a semiconductor substrate is good,
An object of the present invention is to provide an amplification type solid-state image pickup device having almost no variation in device characteristics when manufactured as a pixel.

Another object of the present invention is to provide an amplification type in which the control range of the impurity concentration distribution of the signal storage region formed on the surface of the semiconductor substrate can be wide and the degree of freedom in process design can be increased. It is to provide a solid-state image sensor.

Another object of the present invention is to make it possible to control the impurity concentration of the signal storage region formed on the surface of the semiconductor substrate at a low concentration, and to improve the charge modulation due to the back gate effect during charge reading. Therefore, there is no need to increase the gate potential applied to the gate electrode, and it is an object of the present invention to provide an amplification type solid-state imaging device that can sufficiently cope with the tendency of reducing the driving power supply voltage.

Further, according to the present invention, it is possible to improve the controllability of the impurity concentration of various impurity diffusion regions formed on the semiconductor substrate, and to suppress the variation in the element characteristics when it is manufactured as a pixel. It is to provide a method for manufacturing a solid-state image sensor.

Another object of the present invention is to provide an amplification type device capable of widening the control range of the impurity concentration distribution of the signal storage region formed on the surface of the semiconductor substrate and increasing the degree of freedom in process design. It is to provide a method for manufacturing a solid-state image sensor.

Another object of the present invention is to control the impurity concentration of the signal accumulating region formed on the surface of the semiconductor substrate at a low concentration so that the charge modulation due to the back gate effect can be favorably performed during charge reading. Since it is not necessary to increase the gate potential applied to the gate electrode, the amplification type solid-state imaging device capable of easily manufacturing the amplification type solid-state imaging device capable of coping with the reduction tendency of the driving power supply voltage can be easily manufactured. To provide a method.

[0032]

According to the present invention, each pixel serving as a photoelectric conversion portion has an insulating layer 2 on a semiconductor substrate 1 of the first conductivity type.
In the amplification type solid-state imaging device including the gate electrode 3 formed through the gate electrode 3 and the source region 7S and the drain region 7D of the second conductivity type formed on the surface of the semiconductor substrate 1, the semiconductor substrate 1 Of the impurity diffusion regions formed therein, at least the lower part of the gate electrode 3 is formed in order from the surface of the semiconductor substrate 1 by a signal storage region 6 of the first conductivity type and an overflow barrier formed by ion implantation of impurities of the second conductivity type. The region 5 and the depletion layer stopper region 4 formed by the ion implantation of the first conductivity type impurities are formed.

In this case, the first conductivity type region 8 having an impurity concentration lower than the impurity concentration of the signal storage region 6 may be formed between the signal storage region 6 and the overflow barrier region 5. Good.

Further, in the above structure, the first conductivity type impurity which becomes the ion implantation source in the formation of the depletion layer stopper region 4 is more than the second conductivity type impurity which becomes the ion implantation source in the formation of the overflow barrier region 5. It is desirable that the impurities have a long range of ion implantation.
In this case, the second conductivity type impurity can be phosphorus (P) and the first conductivity type impurity can be boron (B).

Further, according to the present invention, each pixel serving as a photoelectric conversion portion is formed on the surface of the semiconductor substrate 1 and the gate electrode 3 formed on the semiconductor substrate 1 of the first conductivity type via the insulating layer 2. Second conductivity type source region 7S and drain region 7D
And a step of forming a first conductivity type depletion layer stopper region 4 by ion-implanting a first conductivity type impurity into a deep position of the semiconductor substrate 1 in the method for manufacturing an amplification type solid-state imaging device including And the depletion layer stopper region 4 of the semiconductor substrate 1.
Forming a second conductivity type overflow barrier region 5 by ion-implanting a second conductivity type impurity at a position shallower than the formation position of the first conductivity type, and a signal accumulation region 6 of the first conductivity type on the surface of the semiconductor substrate 1. And a step of forming.

In this case, as the first conductivity type impurity which becomes the ion implantation source in the formation of the depletion layer stopper region 4, more ion implantation than the second conductivity type impurity which becomes the ion implantation source in the formation of the overflow barrier region 5 is performed. An impurity having a long range can be used, phosphorus (P) can be used as the second conductivity type impurity, and boron (B) can be used as the first conductivity type impurity.

Further, in the above manufacturing method, the ion implantation energy of the first conductivity type impurities and the ion implantation energy of the second conductivity type impurities are made the same.

[0038]

In the amplification type solid state image pickup device according to the present invention,
During the charge accumulation period, for example, a low level gate potential is applied to the gate electrode 3. At this time, when light is incident on each pixel, one of the charges generated by the light incidence flows out to the source region 7S and the drain region 7D or the overflow barrier region 5 according to the generation position, and the other charge is discharged. , Are stored in the signal storage area 6.

Next, at the time of reading, the gate electrode 3
A high level gate potential is applied to. At this time, the effect of the back gate is added according to the amount of electric charge accumulated in the signal accumulating region 6, whereby the surface charge of the semiconductor substrate 1 is modulated, and the modulated amount of electric charge on the surface causes the source The drain current changes, and as a result, it becomes possible to read out according to the optical signal charge.

In particular, in the present invention, since the overflow barrier region 5 is formed by ion implantation of the second conductivity type impurity and the depletion layer stopper region 4 is formed by ion implantation of the first conductivity type impurity. The impurity concentration distribution of the region becomes a distribution close to a normal distribution or a Gaussian distribution having a concentration peak at the position where impurities are implanted by ion implantation, and there are few components that cancel each other out.

Therefore, the carrier concentration of each region becomes a value corresponding to the impurity implantation amount without being influenced by the shape of the impurity concentration distribution. As a result, unlike the conventional case where the substrate 1 is formed by thermal diffusion in the depth direction of the substrate 1 by heat treatment for a long time, the carrier concentration of each region can be directly controlled by the implantation amount at the time of ion implantation. It will be possible. In addition, the carrier concentration of each region can be controlled individually by the ion implantation amount without being influenced by the impurity concentration of other regions.

As a result, the controllability of the impurity concentrations of the overflow barrier region 5 and the depletion layer stopper region 4 is improved, and there is almost no variation in device characteristics when the device is manufactured as a pixel.

Further, since the impurities are directly ion-implanted to form the overflow barrier region 5 and the depletion layer stopper region 4, the problem that the impurity concentration on the surface of the semiconductor substrate 1 becomes high is solved. It is possible to avoid the inconvenience of increasing the impurity concentration of the signal storage region 6 formed on the surface. This leads to control of the impurity concentration of the signal storage region 6 at a low concentration.

Therefore, the control range of the impurity concentration distribution of the signal storage region 6 formed on the surface of the semiconductor substrate 1 can be widened, and the degree of freedom in process design can be increased. Moreover, since it is not necessary to increase the gate potential applied to the gate electrode 3 in order to favorably perform charge modulation by the back gate effect during charge reading, it is possible to sufficiently cope with the tendency of reduction of the driving power supply voltage.

Particularly, the impurity of the first conductivity type which becomes the ion implantation source in the formation of the depletion layer stopper region 4 is implanted more than the impurity of the second conductivity type which becomes the ion implantation source in the formation of the overflow barrier region 5. When the impurities having a long range are used, for example, when the first conductivity type impurities and the second conductivity type impurities are ion-implanted with the same implantation energy, the first conductivity type impurities and the second conductivity type impurities are first implanted deeper from the surface of the semiconductor substrate 1.
The conductivity type impurities will be implanted, and the second conductivity type impurities will be implanted at a shallower position than that. As a result, the depletion layer stopper region 4 due to the first conductivity type impurities is formed at a position deeper than the overflow barrier region 5 due to the second conductivity type impurities.

In this case, the depletion layer stopper region 4 of the first conductivity type impurity is easily formed at a position deeper than the overflow barrier region 5 of the second conductivity type impurity even by using the ion implantation apparatus with the limited acceleration energy. This makes it possible to eliminate the problem of changing the specifications of the ion implanter and purchasing a custom-made product. This leads to a reduction in the manufacturing cost associated with ion implantation, which in turn can contribute to a reduction in the overall manufacturing cost when manufacturing an amplification type solid-state imaging device.

Next, in the method of manufacturing an amplification type solid-state imaging device according to the present invention, the first conductivity type impurities are ion-implanted into the semiconductor substrate 1 at a deep position to form the first conductivity type depletion layer stopper region 4. After that, the second conductivity type impurities are ion-implanted at a position shallower than the position where the depletion layer stopper region 4 is formed on the semiconductor substrate 1 to form the second conductivity type overflow barrier region 5, and then the semiconductor is formed. A signal storage region 6 of the first conductivity type is formed on the surface of the substrate 1.

In this manufacturing method, the overflow barrier region 5 is formed by directly ion-implanting the second conductivity type impurity, and the depletion layer stopper region 4 is directly formed into the first region.
Since it is formed by ion-implanting conductivity type impurities, the impurity concentration of each region has a value corresponding to the amount of impurity implantation at the time of ion implantation. Therefore, unlike the conventional case where thermal diffusion is performed in the depth direction of the substrate 1 by a long-time heat treatment, the impurity concentration of each region can be directly controlled by the implantation amount at the time of ion implantation. Becomes Moreover, the impurity concentration of each region can be individually controlled by the ion implantation amount without being influenced by the impurity concentrations of the other regions.

As a result, the controllability of each impurity concentration in the overflow barrier region 5 and the depletion layer stopper region 4 can be improved, and variations in element characteristics when the device is manufactured as a pixel can be suppressed.

Further, since the impurity is directly ion-implanted to form the overflow barrier region 5 and the depletion layer stopper region 4, the problem that the impurity concentration on the surface of the semiconductor substrate 1 becomes high is solved, and therefore, the semiconductor substrate 1 is prevented. It is possible to avoid the inconvenience of increasing the impurity concentration of the signal storage region 6 formed on the surface. This leads to control of the impurity concentration of the signal storage region 6 at a low concentration.

Therefore, the control range of the impurity concentration distribution of the signal storage region 6 formed on the surface of the semiconductor substrate 1 can be widened, and the degree of freedom in process design can be increased. From this, according to the manufacturing method of the present invention, it is not necessary to increase the gate potential applied to the gate electrode 3 in order to favorably perform the charge modulation by the back gate effect at the time of reading the charge, and the drive power supply voltage is not required. It is possible to easily manufacture an amplification type solid-state imaging device which can sufficiently cope with the tendency of reduction.

Particularly, as the first conductivity type impurity which becomes the ion implantation source in the formation of the depletion layer stopper region 4, the ion conductivity of the ion implantation becomes larger than that of the second conductivity type impurity which becomes the ion implantation source in the formation of the overflow barrier region 5. Since the impurities having a long range are used, for example, when the first conductivity type impurities and the second conductivity type impurities are ion-implanted with the same implantation energy, the first conductivity type impurities are deeply located from the surface of the semiconductor substrate 1. Will be injected, second
The conductivity type impurity is implanted at a shallower position than that. As a result, the depletion layer stopper region 4 due to the first conductivity type impurities is formed at a position deeper than the overflow barrier region 5 due to the second conductivity type impurities.

Therefore, the depletion layer stopper region 4 due to the first conductivity type impurities is easily formed at a position deeper than the overflow barrier region 5 due to the second conductivity type impurities even if an ion implantation apparatus with limited acceleration energy is used. This makes it possible to eliminate the problem of changing the specifications of the ion implanter and purchasing a custom-made product. this is,
This leads to a reduction in the manufacturing cost associated with ion implantation, which in turn can contribute to a reduction in the overall manufacturing cost when manufacturing an amplification type solid-state imaging device.

[0054]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the amplification type solid-state image pickup device according to the present invention is applied to a substrate charge modulation type imager (hereinafter, simply referred to as a solid-state image pickup device according to the embodiment) will be described with reference to FIGS. explain.

As shown in FIG. 1, the solid-state image pickup device according to this embodiment, in particular, the configuration of a large number of pixels arranged in a matrix in the image pickup region of the solid-state image pickup device is, for example, p.
A gate electrode 3 made of, for example, a conductive polycrystalline silicon layer, a refractory metal silicide layer, or the like is formed on a silicon substrate 1 in the shape of an insulating layer 2 made of, for example, SiO 2.

Specifically, a p-type depletion layer stopper region 4 having an ion implantation center position x1 at a predetermined depth of the p-type silicon substrate 1 is formed, and a position shallower than the center position x1 is ion-implanted. An n-type overflow barrier region 5 having a center position x2 is formed, and a p-type signal storage region 6 is formed on the surface portion of the silicon substrate 1. A planar ring-shaped gate electrode 3 is formed on the signal storage region 6 of the silicon substrate 1 in a pixel portion via the insulating layer 2. In the signal storage region 6, a gate electrode 3 is surrounded by the gate electrode 3. The n-type source region 7S is formed, and the n-type drain region 7D is formed around the gate electrode 3 to form the pixel of the solid-state imaging device according to this embodiment.

The p-type depletion layer stopper region 4 is formed by directly implanting p-type impurities (for example, boron (B)), and the n-type overflow barrier region 5 is formed by n-type impurities (for example, phosphorus ( P)) is directly ion-implanted, and the p-type signal storage region is formed by diffusion. The detailed manufacturing method will be described later.

In this embodiment, the ion implantation center position x1 of the p-type depletion layer stopper region 4 and the ion implantation center position x2 of the n-type overflow barrier region 5 are used.
The relationship between the distance d1 and the distance d2 between the diffusion center position x3 of the p-type signal storage region and the ion implantation center position x2 of the n-type overflow barrier region 5 is d1 <d2. Since d2 is set to be relatively long, the impurity concentration of the region 8 on the surface side of the overflow barrier region 5 in the silicon substrate 1 is almost equal to the substrate concentration in the state before the signal storage region 6 is formed. Since the same, the p-type signal storage region 6 is formed in a p-type region having a low concentration almost equal to the substrate concentration.

In the light receiving operation of this imager, first, in the charge accumulation period, for example, the source region 7S is set to the ground potential,
The drain region 7D is set to a positive potential and the gate electrode 3 is set to a negative potential (that is, a low level potential). At this time, when light is incident on each pixel, the photo-generated electrons flow out to the source region 7S, the drain region 7D or the n-type overflow barrier region 5 depending on the generation position. On the other hand, the photogenerated holes are
It is stored in the p-type signal storage region 6.

This state will be described based on the potential distribution below the gate electrode 3 in FIG. 2A.
When g is low level, the potential distribution in the depth direction is
As shown by the solid line a, the distribution has a minimum point p1 at the depth corresponding to the ion implantation center position x2 of the n-type overflow barrier region 5. Therefore, in the region shallower than the minimum point p1, the photogenerated holes h move along the potential gradient, and the photogenerated holes h are accumulated in the p-type signal accumulating region 6.

Next, at the time of reading, the gate electrode 3
A positive potential (that is, a high level potential) is applied to. At this time, the effect of the back gate is added according to the charge amount Qh of the photo-generated holes h accumulated in the p-type signal accumulation region 6, whereby the surface charge of the silicon substrate 1 is modulated,
By this modulated surface charge amount (number of electrons) Qe,
The source / drain current changes, and as a result, the optical signal hole h
It becomes possible to read out according to the charge amount Qh.

This state will be described based on the potential distribution below the gate electrode 3 in FIG. 2B.
When g is at a high level, the potential distribution in the depth direction is
As indicated by the solid line b, the surface potential of the signal storage region 6 becomes higher along with the gate potential Vg, which causes the surface of the silicon substrate 1 and the n-type overflow barrier region 5 described above.
The distribution has a maximum point p2 between the ion implantation center position x2 and the minimum point p1.

Then, when the photo-generated holes h are accumulated in the signal accumulating region 6 when the gate potential Vg is at a high level, the potential distribution is as shown by the one-dot chain line c. This potential distribution has the maximum point p
2 also has a maximum point p3 at a position corresponding to 2, and the ion implantation center position x2 of the n-type overflow barrier region 4
The distribution has a minimum point p4 at a position corresponding to (the minimum point p1).

The photo-generated holes h are accumulated at the maximum point p3, and the surface (gate electrode) of the silicon substrate 1 is determined according to the charge amount Qh of the photo-generated holes h accumulated at the maximum point p3. Channel 3) will be formed.

That is, the effect of the back gate is added according to the accumulated charge amount Qh of the photogenerated holes h, and the number of electrons Qe in the surface channel is modulated. The source / drain current is changed by the modulated charge amount (electron number) Qe of the surface, and as a result, it becomes possible to read out according to the charge amount Qh of the photogenerated hole h.

Next, a method of manufacturing the amplification type solid-state image pickup device according to this embodiment, particularly the pixel portion thereof will be described with reference to FIG. The same reference numerals are given to those corresponding to FIG.

First, as shown in FIG. 3A, a p-type impurity such as boron (B) is injected into the low-concentration p-type silicon substrate 1 by an implantation amount of 0.3 × 10 ^{12 to} 3. 0 x 10 ¹²
[Ions / cm ² ], injection energy = 2 [MeV]
Is ion-implanted to form a p-type depletion layer stopper region 4. At this time, in the silicon substrate 1, a p-type low concentration region 8 having an impurity concentration substantially the same as the substrate concentration exists on the surface side of the depletion layer stopper region 4.

When the silicon substrate 1 is used as the target, the range Rb of boron (B) when the acceleration energy is 3 MeV is about 2.85 μm, and the boron (B) is the surface of the silicon substrate 1. It is driven centered on the position of depth x1.

Next, as shown in FIG. 3B, an n-type impurity such as phosphorus (P) is injected into the p-type silicon substrate 1 this time, the implantation amount is 0.5 × 10 ^{11 to} 5. 0x10
¹¹ [ions / cm ² ], injection energy = 2 [Me
V] is ion-implanted to form the n-type overflow barrier region 5. At this time, in the silicon substrate 1, a p-type low concentration region 8 having an impurity concentration substantially the same as the substrate concentration exists on the surface side of the overflow barrier region 5.

When the silicon substrate 1 is used as a target, the range Rp of phosphorus (P) when the acceleration energy is 3 MeV is about 1.98 μm, and the phosphorus (P) is the surface of the silicon substrate 1. To the above boron (B)
Will be driven centered on a position x2 that is shallower than the depth at which was driven.

Next, as shown in FIG. 3C, a p-type impurity such as phosphorus (P) is diffused into the p-type silicon substrate 1 this time. This diffusion is performed by placing the silicon substrate 1 in a furnace (temperature of 800 to 1200 ° C.) and flowing an inert gas containing necessary impurities (boron (B) in this case). By this diffusion process, the p-type signal storage region 6 is formed in the low concentration region 8 on the surface of the silicon substrate 1.

Thereafter, although not shown, a heat treatment is performed to improve the crystal defects generated in the silicon substrate by the above ion implantation.

Then, as shown in FIG. 1, the silicon substrate 1 on which the various impurity diffusion regions (p-type depletion layer stopper region 4, n-type overflow barrier region 5 and p-type signal storage region 6) are formed. After forming an insulating layer 2 made of, for example, SiO 2 or the like, a polycrystalline silicon layer or a silicide layer or a polycide layer made of a refractory metal (hereinafter simply referred to as a polycrystalline silicon layer or the like) is formed on the entire surface.
After that, the polycrystalline silicon layer or the like is patterned to leave the polycrystalline silicon layer or the like in the portion corresponding to the pixel, and the gate electrode 3 is formed of the polycrystalline silicon layer or the like.

Next, using the gate electrode 3 as a mask,
An n-type impurity such as phosphorus (P) is ion-implanted into the surface of the p-type signal storage region 6 to form an n-type source region 7S and drain region 7D. After that, although not shown,
Various wiring layers are formed through an insulating layer, and a light-shielding layer made of an Al layer and a passivation film and a color filter layer are formed on the entire surface of the wiring layer. An image sensor is manufactured.

As described above, in the solid-state image pickup device according to the above-described embodiment, the overflow barrier region 5 is formed by phosphorus (P) ion implantation, and the depletion layer stopper region 4 is formed by boron (B) ion implantation. Therefore, as shown in FIG. 4B, the impurity concentration distribution of each region (the depletion layer stopper region 4, the overflow barrier region 5, and the signal storage region 6) is the position x1 at which the impurity is implanted by the ion implantation. And x2 and the diffusion center position x3 are distribution peaks close to the normal distribution, and the components canceling each other are reduced.

Therefore, as shown in FIG. 4A, each region (depletion layer stopper region 4, overflow barrier region 5)
Also, the carrier concentration of the signal storage region 6) has a value corresponding to the impurity implantation amount without being influenced by the shape of the impurity concentration distribution. As a result, unlike the conventional case where the substrate is formed by thermal diffusion in the depth direction of the substrate by heat treatment for a long time, each region (depletion layer stopper region 4, overflow barrier region 5, and signal storage region 6) is formed. It is possible to directly control the carrier concentration by the implantation amount at the time of ion implantation. In addition, the carrier concentration of each region can be controlled individually by the ion implantation amount without being influenced by the impurity concentration of other regions.

As a result, the controllability of the impurity concentrations of the overflow barrier region 5 and the depletion layer stopper region 4 is improved, and there is almost no variation in element characteristics when the device is manufactured as a pixel.

Further, since the overflow barrier region 5 and the depletion layer stopper region 4 are formed by directly ion-implanting phosphorus (P) and boron (B), respectively, the impurity concentration on the surface of the silicon substrate 1 is almost the substrate concentration (low). It is possible to maintain the value close to (concentration) and avoid the disadvantage that the impurity concentration of the signal storage region 6 formed on the surface of the silicon substrate 1 must be increased. This leads to control of the impurity concentration of the signal storage region 6 at a low concentration.

Therefore, the control range of the impurity concentration distribution of the signal storage region 6 formed on the surface of the silicon substrate 1 can be widened and, at the same time, the degree of freedom in process design can be increased. It becomes easy to make the carrier concentration distribution of 6 as designed. Moreover,
Since it is not necessary to increase the gate potential Vg applied to the gate electrode 3 in order to favorably perform the charge modulation by the back gate effect at the time of reading the charge, it is possible to sufficiently cope with the reduction tendency of the driving power supply voltage.

In particular, the p-type impurity which becomes the ion implantation source in the formation of the depletion layer stopper region 4 is more than the n-type impurity (phosphorus (P)) which becomes the ion implantation source in the formation of the overflow barrier region 5. Since the ion implantation has a long range (boron (B) in this embodiment), the p-type impurity (boron (B)) and the n-type impurity (phosphorus (P)) are implanted with the same implantation energy. When the ions are implanted, the p-type impurity (boron (B)) is implanted at a deep position from the surface of the silicon substrate 1, and the n-type impurity (phosphorus (P)) is implanted at a shallower position than that. Will be. As a result, the depletion layer stopper region 4 due to the p-type impurity (boron (B)) is formed at a position deeper than the overflow barrier region 5 due to the n-type impurity (phosphorus (P)).

In this case, the depletion layer stopper region 4 due to the p-type impurity (boron (B)) is used as the n-type impurity (phosphorus (P)) even if an ion implantation apparatus with limited acceleration energy is used.
It is possible to easily form it at a position deeper than the overflow barrier region 5, and there is no problem of changing the specification of the ion implantation apparatus or having to purchase a custom-made product. This leads to a reduction in the manufacturing cost associated with ion implantation, which in turn can contribute to a reduction in the overall manufacturing cost when manufacturing an amplification type solid-state imaging device.

[0082]

As described above, according to the amplification type solid-state image pickup device of the present invention, each pixel serving as a photoelectric conversion portion is formed on the semiconductor substrate of the first conductivity type through the insulating layer. In an amplification type solid-state imaging device including an electrode and a second conductivity type source region and a drain region formed on the surface of the semiconductor substrate, in an impurity diffusion region formed in the semiconductor substrate, , At least under the gate electrode, in order from the surface of the semiconductor substrate, formed by a signal accumulation region of the first conductivity type, an overflow barrier region formed by ion implantation of impurities of the second conductivity type, and ion implantation of impurities of the first conductivity type. Since the depletion layer stopper region of the first conductivity type is formed as described above, the controllability of the impurity concentration of various impurity diffusion regions formed in the semiconductor substrate is improved,
It is possible to suppress variations in element characteristics when manufactured as pixels.

Moreover, the control range of the impurity concentration distribution of the signal storage region formed on the surface of the semiconductor substrate can be widened, and the degree of freedom in process design can be increased.
Further, it becomes possible to control the impurity concentration of the signal storage region formed on the surface of the semiconductor substrate at a low concentration, and in order to favorably perform charge modulation due to the back gate effect during charge reading, it is applied to the gate electrode. It is not necessary to increase the gate potential, and it is possible to sufficiently cope with the tendency of reducing the driving power supply voltage.

Further, according to the amplification type solid-state imaging device of the present invention, in the above structure, the first conductivity type impurity which becomes an ion implantation source in the formation of the depletion layer stopper region is formed in the overflow barrier region. In this case, since the ion implantation range is longer than that of the second conductivity type impurity which is the ion implantation source, even if the ion implantation device with limited acceleration energy is used,
It is possible to easily form the depletion layer stopper region due to the conductivity type impurity at a position deeper than the overflow barrier region due to the second conductivity type impurity, which leads to a reduction in the manufacturing cost for the ion implantation, and thus the amplification type solid-state imaging. This can contribute to the reduction of the overall manufacturing cost when manufacturing the element.

Further, according to the method for manufacturing an amplification type solid-state image pickup device according to the present invention, each pixel to be a photoelectric conversion portion has a gate electrode formed on the semiconductor substrate of the first conductivity type via an insulating layer. A method for manufacturing an amplification type solid-state imaging device having a source region and a drain region of the second conductivity type formed on the surface of the semiconductor substrate, wherein an impurity of the first conductivity type is provided at a deep position of the semiconductor substrate. Ion implantation, first
A step of forming a conductivity type depletion layer stopper region, and ion implantation of a second conductivity type impurity into the semiconductor substrate at a position shallower than a position where the depletion layer stopper region is formed to form a second conductivity type overflow barrier region. Since the step of forming and the step of forming the signal accumulation region of the first conductivity type on the surface of the semiconductor substrate are included, the controllability of the impurity concentration of various impurity diffusion regions formed in the semiconductor substrate is excellent. Therefore, it is possible to suppress variations in device characteristics when the device is manufactured as a pixel.

Moreover, the control range of the impurity concentration distribution of the signal storage region formed on the surface of the semiconductor substrate can be widened, and the degree of freedom in process design can be increased.
Then, the impurity concentration of the signal storage region formed on the surface of the semiconductor substrate can be controlled at a low concentration, and the gate applied to the gate electrode in order to favorably perform the charge modulation by the back gate effect during charge reading. It is not necessary to increase the potential, and an amplification type solid-state imaging device that can sufficiently cope with the tendency of reducing the driving power supply voltage can be easily manufactured.

Further, according to the method for manufacturing an amplification type solid-state image pickup device according to the present invention, in the above-mentioned manufacturing method, the overflow as the first conductivity type impurity which becomes an ion implantation source in the formation of the depletion layer stopper region. In forming the barrier region, since an impurity having a longer ion implantation range than that of the second conductivity type impurity serving as an ion implantation source is used, even if an ion implantation apparatus with limited acceleration energy is used, It is possible to easily form the depletion layer stopper region due to the first conductivity type impurity at a position deeper than the overflow barrier region due to the second conductivity type impurity, which leads to a reduction in the manufacturing cost for the ion implantation, and thus an amplification type solid state. This can contribute to a reduction in the overall manufacturing cost when manufacturing the image pickup device.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of an embodiment (hereinafter, simply referred to as a solid-state image pickup device according to the embodiment) in which an amplification type solid-state image pickup device according to the present invention is applied to a substrate charge modulation type imager, particularly a configuration of a pixel portion thereof. It is a figure.

FIG. 2 is a potential diagram under a gate electrode during a signal accumulating period and a signal reading period of the solid-state imaging device according to the example.

FIG. 3 is a process drawing showing the manufacturing method of the solid-state imaging device according to the embodiment.

FIG. 4 is a characteristic diagram showing a carrier concentration distribution and an impurity concentration distribution in the depth direction of various impurity diffusion regions under the gate electrode of the solid-state imaging device according to the example.

FIG. 5 is a cross-sectional view showing a configuration of a solid-state imaging device according to a conventional example, particularly a configuration of a pixel portion thereof.

FIG. 6 is a process diagram (1) showing a method for manufacturing a solid-state imaging device according to a conventional example.

FIG. 7 is a process diagram (2) showing the method for manufacturing the solid-state imaging device according to the conventional example.

FIG. 8 is a characteristic diagram showing a carrier concentration distribution and an impurity concentration distribution in a depth direction of various impurity diffusion regions under a gate electrode of a solid-state imaging device according to a conventional example.

[Explanation of symbols]

 1 Silicon Substrate 2 Insulating Film 3 Gate Electrode 4 Depletion Layer Stopper Region 5 Overflow Barrier Region 6 Signal Storage Region 7S Source Region 7D Drain Region

Claims (8)

[Claims] 1. A pixel electrode, which serves as a photoelectric conversion unit, is formed on a semiconductor substrate of a first conductivity type via an insulating layer, and a source of a second conductivity type is formed on the surface of the semiconductor substrate. In an amplification type solid-state imaging device having a region and a drain region, among the impurity diffusion regions formed in the semiconductor substrate,
At least a portion below the gate electrode is formed in order from the surface of the semiconductor substrate by a signal storage region of the first conductivity type, an overflow barrier region formed by ion implantation of impurities of the second conductivity type, and an ion implantation of impurities of the first conductivity type. An amplification type solid-state imaging device having a depletion layer stopper region of the first conductivity type. 2. A first conductivity type region having an impurity concentration lower than that of the signal storage region is formed between the signal storage region and the overflow barrier region. The amplification type solid-state imaging device described. 3. The impurity of the first conductivity type, which is an ion implantation source in the formation of the depletion layer stopper region, is more ion-implanted than the impurity of the second conductivity type, which is an ion implantation source in the formation of the overflow barrier region. 3. An impurity having a long range of
The amplification type solid-state imaging device described. 4. The amplification type solid-state imaging device according to claim 3, wherein the second conductivity type impurity is phosphorus (P), and the first conductivity type impurity is boron (B). 5. A pixel electrode, which serves as a photoelectric conversion unit, is formed on a semiconductor substrate of a first conductivity type via an insulating layer, and a source of a second conductivity type is formed on the surface of the semiconductor substrate. A method for manufacturing an amplification type solid-state imaging device having a region and a drain region, wherein a first conductivity type impurity is ion-implanted into a deep position of the semiconductor substrate to form a first conductivity type depletion layer stopper region. Forming a second conductivity type overflow barrier region by ion-implanting a second conductivity type impurity at a position shallower than a position where the depletion layer stopper region is formed in the semiconductor substrate; And a step of forming a signal storage region of the first conductivity type on the surface of the solid-state image pickup device. 6. The impurity of the first conductivity type which serves as an ion implantation source in the formation of the depletion layer stopper region,
6. An impurity having a longer ion implantation range than the second conductivity type impurity, which serves as an ion implantation source in the formation of the overflow barrier region, is used.
A method for manufacturing the amplification type solid-state imaging device described. 7. The phosphorus (P) as the second conductivity type impurity
7. The method for manufacturing an amplification type solid-state image pickup device according to claim 6, wherein boron (B) is used as the first conductivity type impurity. 8. The amplification type solid-state imaging device according to claim 5, wherein the ion implantation energy of the first conductivity type impurities and the ion implantation energy of the second conductivity type impurities are the same. Manufacturing method.