JPH08172657A - Serial data receiver - Google Patents

Abstract

PURPOSE: To realize flexibility and low power consumption at low cost by comparing a received ID code with an ID code allocated in advance bit by bit corresponding to each other so as to attain processing by a low speed clock signal. CONSTITUTION: A synchronization circuit 2 establishes the synchronization of serial data 1 and the data are subjected to error correction processing. An ID collation circuit 4 is used to sequentially write in serial and parallel conversion data of plural IDs from a microprocessor circuit B to a reference register circuit 17, and when the writing is finished, a comparator circuit 15 outputs a data request signal 19 to an error correction circuit 3 based on an end signal 18. When succeeding reception data are transferred to the comparator circuit 15, the result of comparison is received by the microprocessor B via a database 10 and when the number of noncoincidence of the storage signals is a prescribed value or over, it is discriminated to be noncoincident and when any coincident ID exists, the data are received successively. Thus, the reception processing is attained by a clock signal of a slow speed while reducing the number of registers storing ID codes and the receiver has provision for increase in ID codes with a small circuit scale flexibly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ID-controlled portable serial data receiver used in pagers and the like.

[0002]

2. Description of the Related Art As an ID-controlled portable serial data receiving device used in a pager or the like, a block structure shown in FIG. 2 has been conventionally used. This receiver includes a decoder circuit A having a synchronization circuit 2, an error correction circuit 3, an ID collation circuit 4 and a control circuit 5, and a CPU.
It comprises a microprocessor circuit B having a core circuit 6, a data RAM 7 and a program ROM 8, and a register circuit 9 for bridging the data from the decoder circuit A.

In FIG. 2, the serial data input 1 is
It is input to the synchronizing circuit 2 in the decoder circuit A. When the synchronization is established by the synchronization circuit 2, data is continuously taken in. The fetched data is subjected to necessary corrections by the error correction circuit 3, and the ID collation circuit 4 confirms whether or not it matches the ID. If the ID match is confirmed, then the message is received. Error correction is applied to the received message in the same manner as the ID. Then, the register circuit 9 stores the received ID information, message and error information associated with them. When the ID match or the ID information or message is stored in the register circuit 9, the decoder circuit A
An interrupt request is generated by the interrupt control signal 12 from the control circuit 5 to the CPU core circuit 6 of the microprocessor circuit B. The microprocessor circuit B accesses the register circuit 9 in response to the interrupt request.
In this way, the received address information and message information are taken into the microprocessor circuit B.

Some ID verification methods described below are conventionally known. The simplest method is to incorporate an ID code register in the ID collation circuit 4. In this way, since the ID code can be collated in real time when received, it does not become a load on the microprocessor circuit B. FIG. 3 is a block diagram showing the circuit configuration of a conventional serial data receiving apparatus for performing this method.

In FIG. 3, the serial data input 1 is
It is input to the synchronizing circuit 2. When the synchronization is established by the synchronization circuit 2, data is continuously taken in.
The fetched data is subjected to necessary correction by the error correction circuit 3, and the buffer register XX in the ID collation circuit 4 is subjected to the necessary correction.
Sent to The content of the buffer register XX is confirmed by the comparison circuit XY whether it matches the ID stored in the ID register circuit YY. At the time of confirmation, the control circuit 5 operates the selector circuit ZZ in accordance with the synchronization signal for the serial data input, and collation is performed for all IDs of the ID register circuit YY. The content of the buffer register XX is one of the IDs of the ID register circuit YY.
If the two match, the message is subsequently received.

As another method, when the ID code is received, a plurality of ID codes stored in advance in the data RAM are sequentially transferred from the microprocessor circuit B to the ID verification circuit 4 to perform verification. As another method, it is conceivable that the ID code is entirely collated by the operation of the microprocessor circuit B. In this case, the ID collation circuit 4 becomes unnecessary.

Due to the spread of wireless communication systems and the diversification of services in recent years, IDs assigned to portable wireless terminals
The number of is increasing year by year. In the future, as communication and services become more liberalized, terminals that can flexibly deal with diversification of communication systems and services will be required.

[0008]

However, in such a conventional serial data receiving apparatus, when the number of ID codes assigned to the terminal increases, the number of registers increases, or a microprocessor for verification is used. It is necessary to speed up the operation clock of the circuit B.

ID code matching usually tolerates a few bits of error rather than an exact match. Therefore, the verification by software is complicated and requires a large number of steps. Therefore, while receiving serial data, I
In order to check the D code, it is necessary to increase the clock speed of the microprocessor circuit B. In such a case, there is a problem that the power consumption increases and the receiving sensitivity decreases due to the generated noise. On the other hand, when the ID code is collated by hardware, there has been a problem in that the cost increases and the lack of flexibility accompanying the increase in the scale of the hardware.

[0010]

In order to solve the above-mentioned conventional drawbacks, the present invention incorporates the minimum necessary hardware for ID verification and pre-assigns the received ID code. By comparing each bit with the corresponding bit of the ID code, it is possible to realize a flexible receiving device that can be processed by a low-speed clock at low cost.

[0011]

In the serial data receiving device configured as described above, the decoder circuit establishes synchronization with the serial data input, performs error correction, and then, after inputting the ID of the data to be successively input, bit by bit. Match. The ID verification is performed by the comparison circuit for the plurality of assigned reference ID codes, sequentially corresponding to the received bits from the first bit of each. Since the reference ID input to the comparison circuit is stored in the RAM of the microprocessor in advance, it can be freely increased or decreased. Further, since the comparison is carried out by transferring the data from the RAM every time 1 bit is received, it suffices to have a clock of several times to several tens times the bit rate.

To further facilitate the receiving operation, a plurality of reference IDs may be serial / parallel converted and stored in the RAM. As a result, it is possible to compare the received bit and the corresponding bit of the plurality of reference IDs with one data transfer from the RAM to the comparison circuit.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The serial data receiving apparatus of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment of a serial data receiving apparatus according to the present invention, which comprises an ID collation circuit including a register circuit and a comparison circuit connected to a microprocessor circuit, a synchronization circuit for synchronizing with serial data, and an error correction circuit. Is shown by a block diagram.

In FIG. 1, when the serial data input 1 is input to the synchronizing circuit 2, synchronization is established for inputting data with respect to the input signal. After the communication error is detected and corrected by the error correction circuit 3 in the fetched data, the ID collation circuit 4 determines whether or not the data should be received. When it is determined that the data should be received due to the ID match, the data (message) is continuously fetched.

The ID collation circuit 4 comprises a register circuit 20 connected to the data bus 10 and a comparison circuit 15 for comparing the output of the error correction circuit with the reference register circuit 17. In the reference register circuit 17, serial / parallel converted data of a plurality of IDs are sequentially written from the built-in RAM of the microprocessor circuit B from the first bit. For example, assuming that an 8-bit CPU is used, up to 8 IDs can be compared at the same time. If more IDs are assigned, the data will be transferred to the reference register circuit 17 twice or more every time one bit is received. Reference register circuit 1
When the data is written in 7, the write end signal 18 causes the comparison circuit 15 to compare the received data. When the comparison is completed, the data request signal 19 is output from the comparison circuit 15 to the error correction circuit 3. Upon receiving the data request signal 19, the error correction circuit 3 receives the next received data 1
The bit is transferred to the comparison circuit 15. Then, the comparison is performed on the next bit of the ID.

The compared results are fetched by the microprocessor circuit B via the data bus 10. The microprocessor circuit B accumulates the result of the non-coincidence and considers the non-coincidence by the program when a certain number of bits or more do not coincide. If all the IDs do not match, reception ends. When even one matching ID is found, the data (message) is continuously received.

[0017]

As described above, according to the present invention, in the serial data receiving operation, the reception processing can be performed by using the relatively slow clock while reducing the registers for storing the ID code, so that the circuit scale is small. It is possible to flexibly deal with the increase of the ID code, and it is also effective for improving the battery life and the receiving sensitivity due to the low power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a serial data receiving device of the present invention.

FIG. 2 is a block diagram showing a conventional serial data receiving device.

FIG. 3 is a block diagram showing a conventional serial data receiving device: 1 serial data input signal 2 synchronization circuit 3 error correction circuit 4 ID collation circuit 5 control circuit 6 CPU core circuit 7 program ROM 8 data RAM 9 register circuit 10 data Bus 11 Address bus 12 Control signal 13 Selector circuit 14 ID register circuit 15 Comparison circuit 16 Buffer register 17 Reference register circuit 18 Write end signal 19 Data request signal A Decoder circuit B Microprocessor circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichi Izumu 6-31-1, Kameido, Koto-ku, Tokyo Seiko Denshi Kogyo Co., Ltd.

Claims (3)

[Claims] 1. A selective call signal (hereinafter referred to as an ID) ID-controlled receiving device for fetching data in synchronization with serial data transmitted through a communication channel, I
When the D code is received, the selected 1 bit in the ID code and a plurality of IDs assigned to the receiving device
Compare the corresponding bits of the code simultaneously in parallel and subsequently select the next bit of the received ID code,
A serial data receiving apparatus, characterized in that each bit of the received ID code is sequentially compared. 2. The ID code is compared by comparing a latch means for storing 1 bit of received data, a RAM and a plurality of registers controlled by a microprocessor, an output of the latch means and an output of the plurality of registers. The serial data receiving device according to the first aspect, which is performed by using a comparison circuit as an input. 3. A plurality of I's assigned to the receiving device
The D code is converted into serial / parallel in advance and the RA
The serial data receiving device according to the second item, which is stored in M.