JPH08171485A - Development supporting method and development supporting device for signal processing system, signal processor and signal processing method - Google Patents

Abstract

PURPOSE: To automatically prepare the control information of a signal input part by graphically inputting the format of a processing object signal by extracting the information of an area to be taken in the format of the inputted processing object signal and generating the control information to the input part of a signal processing system. CONSTITUTION: An optional signal included in video signals is specified by using a signal specifying means 400 and a signal flow chart is inputted by using a signal flow chart input means 406. Then, the signal flow structure list extraction means 411 of a central processing unit 403 extracts the structure list of the signal flow chart, a signal area extraction means 409 extracts a signal area to be taken in the signal format of the specified signal in the video signals and a signal input part control information generation means 410 generates the control information or the like of the signal input part. Then, a video processing part control information generation means 412 generates the control information or the like of a signal processing module and the generated control information is displayed at a CRT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a development support method and apparatus for developing a signal processing program provided to a DSP (digital signal processor) in a signal processing system, and the development thereof. The present invention relates to a signal processing device and method using a program.

[0002]

2. Description of the Related Art In recent years, a broadcasting system called EDTV (Extended Definiton TV, so-called clear vision) has been put into practical use due to the demand for higher image quality of television images. Also, MUSE (Multiple Sub-nyqui), which is a type of HDTV (High Definiton TV, so-called high-definition) system.
New high-definition broadcasting such as st Sampling Encoding) has been proposed and partially put to practical use. EDTV II in the future
(2nd generation EDTV), digital broadcasting, etc. will be implemented. Along with this, a television receiver (hereinafter,
It is called a TV receiver. ) And video tape recorders (below,
It is called VTR. 2) and other video signal processing devices are required to support a plurality of broadcasting systems including the current NTSC (National Television System Committee) system.
For example, in a conventional TV receiver, a plurality of boards corresponding to each of a plurality of broadcasting systems are built in, and a board to be used is switched according to a broadcasting system of a signal to be received.

However, the conventional TV receiver described above has a drawback that the cost increases because a plurality of boards are incorporated.

Therefore, the present applicant has filed Japanese Patent Application No. 5-8471.
No. 2 (US application 8 / 226,663), the hardware is shared by a plurality of broadcasting systems, and the processing by the common hardware is changed by switching the software so that the video signals of different broadcasting systems are Also proposes to provide a low-priced video signal processing device that enables appropriate processing for each video signal.

[0005]

By the way, when the signal to be processed is a video signal as described above, the video signal includes a control signal such as inter-field sub-sampling phase, It is necessary to change the content of signal processing in the common hardware (signal processing unit) according to the content of this control signal.

[0006] In recent years, as the number of signal processing systems using DSP has increased, the development of applications for the DSP control programs or control parameters (hereinafter referred to as control information) is supported. Development support method and development support device, such as "PicPEn
-Real-Time Video Signal Processor-Programming Environment for Picot- "(Television Society, Vol. 44,
No. 11, pp. 1570 to 1578) and JP-A-4-
274518 "DSP image signal processing program creating apparatus" has been proposed.

However, a video signal or the like is input according to a predetermined format in which video data and control signals are arranged in a predetermined order. Therefore, if the developer of the control information does not fully understand the format, the video signal is input. It is not possible to create control information for the signal input unit to capture a signal. In the conventional development support method and apparatus, a signal consisting only of data is a signal to be processed, and there is no mention of creating control information for a signal processing system such as a video signal having a predetermined format.

Further, in the conventional development supporting method and apparatus, since the signal to be processed is a signal which does not include the control signal, the conventional development supporting method and apparatus are applied to the video signal. However, it is not possible to create control information that can change the signal processing in the signal processing unit according to the content of the control signal included in the video signal.

Further, in order to create appropriate control information, it is necessary to examine and evaluate each of a plurality of algorithms, but the conventional development support method and apparatus described above handle and examine various algorithms. I can't.

The present invention has been made in view of the above-mentioned drawbacks, and an object thereof is to provide a development support method in which a designer can easily and automatically create control information of a signal input section if a designer schematically inputs a format of a signal to be processed. To provide a device.

Another object of the present invention is to provide a development support capable of easily creating control information for a signal to be processed including a control signal, which can instruct signal processing according to the content of the control signal. A method and apparatus are provided.

Still another object of the present invention is to provide a development supporting method and apparatus capable of managing a plurality of algorithms of a signal processing application and facilitating examination and evaluation of the plurality of algorithms.

In addition, another object of the present invention is to provide a signal processing apparatus and method for performing signal processing using control information created so as to instruct signal processing according to the content of a control signal. is there.

[0014]

In order to achieve the above object, in the present invention, a designer graphically inputs a format of a signal to be processed.

Further, in the present invention, the functional description of the signal processing unit is set to include the name of the control signal, and when a signal to be processed including the control signal is input, the functional description is described by the actual value of the control signal. The control signal name in will be replaced.

Further, according to the present invention, any one of several kinds of signal processing algorithms can be selected, and a history of examination of the algorithms is left.

That is, in the signal processing system development supporting method according to the first aspect of the present invention, there is provided a signal processing system development supporting method for developing the control information in a signal processing system for performing predetermined signal processing according to control information. ,
The signal format input step of inputting the format of the processing target signal composed of a plurality of signals, the designating step of designating a part or all of the signals included in the processing target signal, and the signal designated in the designating step A signal area extracting step of extracting information of an area to be taken in the format of the signal to be processed input in the signal format input step, and the signal based on the information of the signal area extracted in the signal area extracting step. An input unit control information generating step of generating control information for the input unit of the processing system.

According to a second aspect of the present invention, in the signal processing system development supporting method according to the first aspect, in the step of designating a signal, the designated signal is selected from a plurality of input ports on the signal processing system. It is also characterized in that the input port to input is also specified.

In the invention according to claim 3, in the method for supporting development of a signal processing system according to claim 1 or 2, when a plurality of signals are designated in the designation step, each designated signal is given. Then, the specifying step, the signal area extracting step, and the input section control information generating step are executed.

In the signal processing system development support method according to the present invention, in the signal processing system development support method for developing the control information in the signal processing system that performs predetermined signal processing according to the control information, A function input step of inputting function description information described by using the name of a control signal included in a signal to be processed, which is a function description of a signal processing unit included in the processing system, and registration of derivation information of the content of the control signal. And a signal processing unit control information generation step of generating control information of the signal processing unit from the function description information input in the function input step and derivation information of the content of the control signal registered in the registration step. It is characterized by having.

According to a fifth aspect of the present invention, in the signal processing system development support method according to the fourth aspect, the signal processing unit control information generating step includes the function description information input in the function input step as a control signal. A generation step of generating control information of the signal processing section described using a name, a reading section generation step of generating a reading section for reading the content of the control signal from the derivation information of the content of the control signal registered in the registration step, Of the control information of the signal processing unit generated in the generating step, a replacement unit generating a replacement unit that replaces the portion described by using the name of the control signal with the content of the control signal read in the reading step. And a step.

According to a sixth aspect of the invention, in the signal processing system development support method according to the fourth or fifth aspect, the function input step inputs the function description information of a plurality of signal processing units, and further, It is characterized by further comprising a connection information generation step of generating connection information for connecting the plurality of signal processing units based on the function description information of the plurality of signal processing units input in the function input step.

According to a seventh aspect of the invention, in the signal processing system development support method according to the first aspect,
The signal format input step of inputting the format of the processing target signal composed of a plurality of signals, the designating step of designating a part or all of the signals included in the processing target signal, and the signal designated in the designating step A signal area extraction step of extracting an area to be taken in the format of the signal to be processed input in the signal format input step, and an input of the signal processing system based on the signal area extracted in the signal area extraction step An input unit control information generating step of generating control information for the unit.

According to an eighth aspect of the invention, in the signal processing system development support method according to the fourth or seventh aspect, the function input step includes a signal processing algorithm and a function of a signal processing unit used for the signal processing. Is composed of a flow input step of inputting by a signal flow diagram focusing on the flow of a signal to be processed, and a structural information extraction step of extracting the structural information from the signal flow diagram input in the flow input step. The information generating step is characterized in that the control information of the signal processing unit is generated from the structure information extracted in the structure information extracting step and the derivation information of the control signal registered in the registering step.

According to a ninth aspect of the present invention, there is provided a signal processing system development supporting method, wherein in the signal processing system developing method for developing the control information in the signal processing system for performing predetermined signal processing according to the control information, the signal processing is performed. Is a signal flow diagram focusing on the flow of a signal to be processed, and the functions of a plurality of signal processing units used for the signal processing of the algorithm are configured by a plurality of signal paths between two predetermined signal processing units. A flow input step of inputting, a routing step of selecting one signal path among a plurality of signal paths taken between two predetermined signal processing units in the signal flow diagram, and a signal input in the flow input step In the flow diagram, the structure information is extracted for the part excluding the signal path not specified in the above-mentioned routing step. And having a forming information extraction step, a signal processing unit control information generating step of generating control information for the signal processing unit from the extracted structure information in the structure information extraction step.

According to a tenth aspect of the present invention, in the signal processing system development support method according to the first, fourth or ninth aspect, a signal processing algorithm and a plurality of signal processing units used for the signal processing are provided. From the structure information extracted in the structure information extraction step, the flow input step of inputting the function by the signal flow diagram focusing on the flow of the signal to be processed, the structural information extraction step of extracting the structural information from the signal flow diagram It is characterized by comprising a calculation step of calculating a signal rate of each signal processing section and a display step of displaying the signal rate calculated in the calculation step.

In the signal processing system development support device according to the present invention, a plurality of signal processing system development support devices for developing the control information in a signal processing system for performing predetermined signal processing according to control information can be provided. Signal format input means for inputting the format of the processing target signal composed of the signal, designating means for designating a part or all of the signals included in the processing target signal, and the signal designated by the designating means, A signal region extracting unit that extracts information on a region taken in the format of the signal to be processed input by the signal format input unit, and the signal processing based on the information on the signal region extracted by the signal region extracting unit. And an input unit control information generating means for generating control information for the input unit of the system.

According to a twelfth aspect of the present invention, the first aspect
In the signal processing system development support device described in 1, the designation means for designating a signal also designates an input port to which the designated signal is to be input, out of a plurality of input ports on the signal processing system. To do.

According to a thirteenth aspect of the invention, there is provided the above first aspect.
13. The signal processing system development support apparatus according to claim 1 or 12, further comprising format storage means for storing a format of a signal to be processed input by the signal format input means, when a plurality of signals are designated by the designating means. Reads out the format of the signal to be processed stored by the format storage means, sequentially designates the signal by the designation means, extracts the area by the signal area extraction means, and inputs the control information for each designated signal. It is characterized in that the generation of the control information for the input unit is executed by the generation means.

According to a fourteenth aspect of the present invention, there is provided a signal processing system development supporting apparatus, wherein a signal processing system development supporting apparatus for developing the control information in a signal processing system for performing a predetermined signal processing according to the control information includes: A function input means for inputting function description information described by using a control signal included in a signal to be processed, which is a function description of a signal processing unit included in a processing system, and a registration means for registering derivation information of the control signal. And a signal processing unit control information generation unit that generates control information of the signal processing unit from the function description information input by the function input unit and the derivation information of the control signal registered by the registration unit. To do.

According to a fifteenth aspect of the invention, there is provided the above first aspect.
In the signal processing system development support device described in 4, the signal processing unit control information generation unit generates the control information of the signal processing unit in which the function description information input by the function input unit is described using a control signal. First generating means,
Of the control information derived from the control signal derivation information registered by the registration means, a reading section generating means for generating a reading section for reading the contents of the control signal, and the control information of the control information of the signal processing section generated by the first generating means is used. And a replacement portion generating means for generating a replacement portion for replacing the portion described by the above with the contents of the control signal read by the reading means.

According to a sixteenth aspect of the present invention, the first aspect
The signal processing system development support apparatus according to claim 4 or claim 15, wherein the function input means inputs the function description information of the plurality of signal processing sections, and further the functions of the plurality of signal processing sections input by the function input section. It is characterized by further comprising connection information generating means for generating connection information for connecting the plurality of signal processing units based on the description information.

According to a seventeenth aspect of the present invention, there is provided the above-mentioned first aspect.
4. The signal processing system development support apparatus according to 4, further comprising a signal format input means for inputting a format of a processing target signal composed of a plurality of signals, and a part or all of the signals included in the processing target signal. Specifying means, a signal area extracting means for extracting an area in which the signal specified by the specifying means is taken in the format of the signal to be processed input by the signal format input means, and the signal area extracting means And an input unit control information generating means for generating control information for the input unit of the signal processing system based on the signal region thus generated.

According to the eighteenth aspect of the present invention, the first aspect of the present invention is provided.
4 or the development support device for a signal processing system according to claim 17, wherein the function input means uses a signal flow diagram focusing on the flow of the signal to be processed, for the function of the signal processing algorithm and the signal processing unit used for the signal processing. It comprises a flow input means for inputting and a structure information extracting means for extracting the structure information from the signal flow diagram input by the flow input means, and the signal processing unit control information generating means is the structure extracted by the structure information extracting means. The control information of the signal processing unit is generated from the information and the derivation information of the control signal registered by the registration means.

According to a nineteenth aspect of the present invention, there is provided a signal processing system development supporting apparatus, wherein the signal processing system developing apparatus develops the control information in a signal processing system for performing predetermined signal processing according to the control information. Is a signal flow diagram focusing on the flow of a signal to be processed, and the functions of a plurality of signal processing units used for the signal processing of the algorithm are configured by a plurality of signal paths between two predetermined signal processing units. Flow input means for inputting, route specifying means for selecting one signal path among a plurality of signal paths taken between two predetermined signal processing sections in the signal flow diagram, and signal input by the flow input means A structure information extractor for extracting the structure information of a part of the flow diagram excluding the signal path not specified by the path specifying means. When, characterized in that a signal processing unit control information generating means for generating control information for the signal processing unit from the extracted structure information in the structure information extraction means.

According to the invention of claim 20, the invention according to claim 1
In the signal processing system development support apparatus according to claim 1, claim 14 or claim 19, a signal flow diagram focusing on the flow of a signal to be processed, with respect to the function of a signal processing algorithm and a plurality of signal processing units used for the signal processing. Flow input means for inputting, structure information extraction means for extracting the structure information from the signal flow diagram, calculation means for calculating the signal rate of each signal processing unit from the structure information extracted by the structure information extraction means, Display means for displaying the signal rate calculated by the calculation means.

According to a twenty-first aspect of the present invention, in the signal processing device, a signal input section for inputting a processing target signal including a control signal and a processing target signal input to the signal input section are controlled according to input control information. A signal processing unit to be processed and a processing target signal input to the signal input unit while storing control information generated in advance using the name of a control signal included in the processing target signal input to the signal input unit And a control unit that replaces the control signal name included in the control information with the content of the control signal included in the input processing target signal and outputs the control information including the content of the control signal to the signal processing unit. It is characterized by having.

The invention according to claim 22 is the same as claim 21.
In the signal processing device according to the description, the control unit has a storage unit that stores control information generated using the name of the control signal, and a method of deriving the content of the control signal included in the control information from the processing target signal in advance. Based on the registered registration means and the derivation method registered in the registration means,
An input unit for extracting the content of the control signal corresponding to the control signal name included in the control information from the input processing target signal, and a control included in the control information with the content of the control signal extracted by the input unit. It is characterized by including a replacing unit for replacing a signal name, and an output unit for outputting control information including contents of the control signal replaced by the replacing unit to the signal processing unit.

The invention according to claim 23 is the same as claim 21.
In the described signal processing device, the input processing target signal is a video signal.

The invention according to claim 24 is the same as claim 23.
In the signal processing device described above, one of a plurality of types of video signals respectively corresponding to a plurality of broadcasting systems is input to the signal input unit, and the signal processing unit processes a plurality of video signals of different broadcasting systems. The control unit prestores a plurality of control information corresponding to a plurality of broadcasting systems, and includes a system detection unit for detecting the broadcasting system of the video signal input to the signal input unit. The control information corresponding to the broadcast system is output to the signal processing unit.

The invention of claim 25 is the same as claim 23.
In the signal processing device described above, the control signal included in the video signal is a sampling phase signal.

The invention according to claim 26 is the same as claim 24.
In the signal processing device described above, a plurality of types of broadcasting systems respectively corresponding to a plurality of types of video signals are NTSC system and M
It is characterized by including a USE method.

The signal processing method according to the twenty-seventh aspect of the present invention is
In advance, control information is generated using the name of the control signal included in the processing target signal to be input, and then,
Input a processing target signal including the control signal,
Next, the control signal name included in the control information is replaced with the content of the control signal included in the input processing target signal, and then the input processing target signal is processed using the control information including the content of the control signal. It is characterized by doing.

The invention according to claim 28 is the above-mentioned claim 27.
In the signal processing method described, when replacing the control signal name included in the control information with the content of the control signal included in the input processing target signal, change the content of the control signal corresponding to the control signal name included in the control information. It is characterized by using derivation information for deriving from the signal to be processed.

The invention according to claim 29 is the above claim 27.
In the signal processing method described above, the input processing target signal is a video signal.

The invention according to claim 30 is the above-mentioned claim 29.
In the signal processing method described above, any one of a plurality of types of video signals corresponding to a plurality of types of broadcasting systems is input, and then the broadcasting system of the input video signal is detected, and then the above The control information corresponding to the detected broadcast system is output from the plurality of control information stored in advance corresponding to each of the plurality of broadcast systems, and then the processing of a plurality of video signals of different broadcast systems is performed. It is characterized in that the input video signal is processed on the basis of the output control information by using the signal processing unit shared by the above.

The invention of claim 31 is the same as that of claim 29.
In the described signal processing method, the control signal included in the video signal is a sampling phase signal.

The invention of claim 32 is the same as claim 30.
In the described signal processing method, the plurality of types of broadcasting systems respectively corresponding to the plurality of types of video signals are NTSC system and M system.
It is characterized by including a USE method.

According to the above-mentioned structure, any one of claims 1 to 3 can be obtained.
According to the inventions of claims 11 to 13, the format of the signal to be processed is graphically input, the information of the signal format is held, and the designer specifies the signal included in the signal to be processed. For example, since the area information of the designated signal is extracted from the format of the signal to be processed, the control information of the signal input unit is generated based on the area information of the designated signal. Therefore, the designer only needs to input the format of the signal to be processed graphically, and can easily control the signal input unit without storing all detailed knowledge and information about the control of the signal input unit or repeatedly searching. It is possible to generate information and the like.

Further, in the inventions of claims 4 to 6 and 8 and claims 14 to 16 and 18, the designer specifies the function description information of the signal processing unit and the name of the control signal. Input in the form that includes it, and register the method of deriving the content (actual value) of the control signal.
After that, when a processing target signal including the control signal is input, the content of the control signal included in the processing target signal is replaced with the name of the control signal in the function description information. Information is easily generated.

Further, in the invention of claim 7, both the action of the invention of claim 1 and the action of the invention of claim 4 are obtained, and in the invention of claim 17, the invention of claim 17 Both the function of the invention described and the function of the invention described in claim 14 can be obtained.

In addition, in the invention described in claims 9 and 19, the designer inputs a signal flow diagram, and in the flow diagram, a plurality of signal paths existing between two predetermined signal processing sections are input. Any one of them is selected and designated, the structure information is extracted from the signal flow diagram formed by this designation, and the control information of the signal processing unit is generated based on the extracted structure information. Therefore, when the selection and designation of any one of the plurality of signal paths, the extraction of the structural information, and the generation of the control information are sequentially repeated, the history of the algorithm of the signal processing application remains, so that the examination of the algorithm or , It is easy to develop appropriate control information after the examination.

In addition, in the invention described in claims 10 and 20, the signal flow diagram is input, the structural information is extracted from the signal flow diagram, and the signal rate of each signal processing unit is calculated from the structural information. Since the obtained signal rates are displayed to the designer, control information and the like for each signal processing section can be easily generated without investigating and searching for the signal rate of each signal processing section.

Further, in the signal processing device and the processing method according to the twenty-first to thirty-second aspects of the present invention, when the processing target signal including the control signal is input, the control signal name in the control information is input. The control information including the contents of the control signal is output to the signal processing unit. Therefore, in the signal processing unit, the signal processing for the signal to be processed is changed according to the content of the input control signal.

Particularly, in the invention described in claims 24 and 30, when the video signal is input, the broadcasting system of the video signal is detected, and the control information corresponding to the broadcasting system is output to the signal processing unit. Therefore, even if there are a plurality of broadcasting systems, the signal processing unit can be shared by the processing of video signals of different broadcasting systems.

[0056]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

First, a hardware configuration of a video (signal) processing system which is a target of the following embodiments of the invention will be described.

A video signal input to the video processing system is referred to as a source signal (processing target signal), and a signal processed and output by the signal processing system is referred to as an output signal.

FIG. 1 shows an example of a video signal processing system using a DSP.

Reference numeral 101 denotes a signal input section, which is a block for inputting a source signal to the video processing section 102. The source signal includes a luminance signal, a color signal, and an audio signal, and also includes a video control signal such as a subsampling phase signal.

A video processing unit 102 executes various video signal processing algorithms.

Reference numeral 103 denotes a control unit, which is the signal input unit 1
01 and a control program 106 for controlling the video processing unit 102. This control program 106 has a plurality of broadcasting systems, such as NTSC system and MUSE system.
It is composed of a plurality (two) of control programs respectively corresponding to one broadcasting system, and one of the control programs is transferred (downloaded) to each signal processing module 105 (described later) of the signal input unit 101 and the video processing unit 102. ) Will be done. The control by the control unit 103 is performed for each field, and by the control, the processing content of the signal processing can be changed for each field.

The video processing unit 102 includes a signal input unit 101.
A plurality of signal input ports 104 for inputting a signal from the device and a plurality of signal processing modules (signal processing units) 105 for realizing video processing are built in. This signal processing module 105
The number of s, depends on the type of target video processing,
For example, it is about 70.

A bus switch 106 connects the line buffers 104 to the signal processing modules 105.

FIG. 30 shows the control when the control unit 103 is the control unit of the television receiver. In the figure, the control unit 103 is reset when the switch is powered on.
An arithmetic unit, a register, and the like (not shown) built in are initialized (step 1001). Next, the broadcasting system is detected (step 1002) (the system detecting means 301 is constituted by this step 1002), and the result of the broadcasting system detection (step 1002) is N in the case of the NTSC system.
NTS that selects a control program compatible with the TSC system and transfers (downloads) it to the signal processing module 105.
While branching to C processing (step 1005), MUSE
In the case of the system, the process branches to the MUSE process (step 1007) of selecting a control program corresponding to the MUSE system and transferring (downloading) it to the signal processing module 105. After that, it becomes an infinite loop, and each video processing is performed until an interrupt signal is input. The N
When a video processing switching request (that is, a channel change request in the television receiver) is generated during the TSC processing (step 1005), an interrupt is generated (step 1004),
The process returns to the detection of the broadcasting system (step 1002). MU
When a video processing switching request is generated during the SE processing (step 1007), an interrupt is similarly generated (step 1006).

FIG. 2 shows an example of the configuration of the signal processing module 105.

In FIG. 2, reference numeral 201 denotes a signal processing module.

The signal processing module 201 is operated by the external clock signal 211. Further, the signal processing module 201 has two systems of inputs 207 and 208,
It has two outputs 209 and 210.

Reference numeral 202 denotes an internal register which receives and stores the data from the input 208.

Reference numeral 203 denotes an internal register which receives and stores the data from the input 207.

Reference numeral 204 is an internal register which receives data from the internal register 203 and stores it.

Reference numeral 205 denotes an internal register which receives data from the internal register 204 and stores it.

Reference numeral 206 denotes an arithmetic unit which inputs data from the internal registers 202, 203, 204 and 205 and performs arithmetic operations. Calculations include addition, subtraction, multiplication and division, and maximum / minimum value calculation. The calculation result is output from the output 210.

The output 209 outputs the data of the internal register 205.

Reference numeral 212 denotes a program storage section, which stores a program for controlling the signal processing module 201. This stored program corresponds to the control unit 10
3 is transferred (downloaded).

The signal processing module 201 is controlled by an assembler program stored in the program storage section 212 and executes signal processing. Specifically, an assembler program indicated by a program counter (not shown) is sequentially read and executed, and when this assembler program is executed to the end, the assembler program returns to the beginning and is repeatedly executed.

When the video signal includes various video control signals such as sampling phases, it is necessary to change the contents of the video processing depending on the value of the video control signal. Generally, this video control signal is prepared for each field. In addition, a signal derived from the video control signal, such as a logical negation signal, is also conceivable.

In the present embodiment, the above-mentioned two types of signals are treated as video control signals.

Since the control unit 103 controls for each field, it is possible to control the processing of the signal input unit 101 and the video processing unit 102 by the video control signal.

In the embodiments described below, a video signal having the signal format shown in FIG. 3 will be described as an example.

The video signal shown in FIG. 3 has 4 fields per field.
It is a signal having 80 pixels and 565 lines of pixels.

In practice, the pixel (1,1),
(1,2), ..., (1,480), (2,1), ...,
(2,480), ..., (565,1), ..., (565,
480) is transmitted, received, and taken into the storage device 404. Further, for example, it may be read out from a recording medium such as a disk to the storage means of the present system. Further, the video signal from the receiving unit may be directly taken out without being taken into the storage means. In this case, the pixel position is obtained from the time when the pixel is taken in.

The data structure of the signal format of the video signal of FIG. 3 will be described. The b-th pixel on the a-th line is expressed as (a, b). 301 is a luminance signal “Y”, which starts from (47, 107) of the video signal. A color signal “C” 302 starts from (43, 3) of the video signal. 303 is a video control "Ctrl" signal, which starts from (559, 3) of the video signal. Also, 30
Reference numeral 4 is a frame pulse inserted in the first and second lines, which is for vertical synchronization in frame units. Reference numeral 305 is voice information and its additional information.

(First Embodiment) FIG. 4 is a diagram showing a hardware configuration of a program development support system for a video processing system using a DSP.

401 is an input device, 402 is an output device, 4
Reference numeral 03 is a central processing unit and 404 is a storage device.
The schematic configuration will be described.

The input device 401 is composed of a pointing device such as a mouse and a keyboard, and a program design developer for DSP (hereinafter referred to as a designer) inputs the algorithm / function of the signal processing application and the format of the input signal. In order for the designer to input the signal format input means (signal format input means) 405 for the designer to input the signal format of the video signal shown in FIG. 3 and the signal flow diagram shown in FIG. 12 or 24. Signal flow diagram input means (flow input means) 406
And a signal flow diagram shown in FIG. 24, that is, in the case of inputting a signal path in which a plurality of signal paths (signal paths) are formed between two signal processing units, any one of the plurality of signal paths is input. A signal path designating unit (route designating unit) 407 for the designer to select and designate, and a control signal registration for registering the method of deriving the control signal when the input video signal includes the control signal. Means (registration means) 408 and a part or all of the signals included in the input video signal (processing target signal),
For example, a designer arbitrarily selects and specifies a C signal or a Y signal, and includes a signal specifying unit (designating unit) 400 for specifying an input port for inputting the specified signal.

Further, in the storage device 404, a signal format information storage means (format storage means) 415 for storing the information of the signal format input to the signal format input means 401, and the signal flow diagram input means 4
A signal flow diagram data information storage means 416 for storing the data information of the signal flow diagram input to the control signal 06, and a control signal information storage means 417 for storing the method of deriving the control signal registered in the control signal registration means 408. Prepare

Further, the central processing unit 403 is a signal area for extracting information of an area taken by the signal designated by the signal designating means 409 in the format of the video signal input by the signal format inputting means 405. Based on the information of the signal area extracted by the extracting means 409 and the signal area extracting means 409, the signal input section control information generating means 4 for generating control information for the signal input section 101 of FIG.
10 and a signal flow structure list extraction means (structure information extraction means) 41 for extracting the structure information from the signal flow diagram input by the signal flow diagram input means 406.
1, the structure information extracted by the signal flow structure list extraction means 411, and the control signal registration means 40.
A video processing unit control information generating unit (signal processing unit control information generating unit) 412 for generating control information of the signal processing module 105 from the derivation information of the control signal registered in 8.
With.

In addition, the output device 402 includes a display unit such as a CRT, and outputs the control information of the signal input unit 101 generated by the signal input unit control information generation unit 410. A means 413 and a video processing section control information output means 414 for outputting the control information and the like of the video processing module 105 generated by the video processing section control information generating means 412 are provided. The input information and the processing result are displayed on the CRT.

Next, the operation of the hardware configuration of the program development support system for the video processing system shown in FIG. 4 will be described with reference to FIG.

In FIG. 29, first, step 2901.
Then, the designer inputs the signal format of the video signal by using the signal format input means 405, and the information of the signal format of the input video signal is stored in the signal format information storage means 415 and at the same time, the signal designating means 4
The designer uses 09 to specify an arbitrary signal (for example, Y signal) included in the video signal. Also, step 2902
Then, the designer inputs the signal flow diagram shown in FIG. 12 or FIG. 24 using the signal flow diagram input means 406, and the information of the input signal flow diagram is stored in the signal flow diagram data information storage means 416.

Thereafter, in step 2903, it is determined whether or not the control signal included in the video signal is used for the video processing by the video processing module 105. If the control signal is used, the designer operates the control signal input means 408 in step 2904. The control signal derivation method is registered by using the information of the registered control signal and stored in the control signal information storage means 417.

Subsequently, it is judged whether or not a plurality of signal paths (signal paths) are present in the signal flow diagram input in step 2905, and if they are present, that is, the signal flow diagram shown in FIG. 24 is input. In case, step 2
At 906, the designer uses the signal path designating unit 407 to select and designate any one of the plurality of signal paths.

After that, in step 2907, the signal flow structure list extracting means 411 of the central processing unit 403.
Extracts the structure list of the input signal flow diagram. Then, in step 2908, the signal area extraction unit 40
9 is a signal specified in the video signal (for example, Y signal)
Extracts the signal region taken in the signal format, and in step 2909, the signal input unit control information generating means 4
10 generates control information of the signal input unit 101 and the like. Then, in step 2910, when the control information for the signal input unit 101 is not generated for all of the designated signals, the steps 2908 and 2909 are performed.
No signal input for each designated signal 101
It is repeated to generate the control information of.

Finally, in step 2911, the video processing unit control information generation means 412 causes the signal processing module 105 to perform processing based on the extracted structure information of the signal flow diagram and the registered derivation information of the control signal. Generates control information, etc., and CR generates the generated control information
Display on T and exit.

Next, FIG. 5 shows a processing flowchart of the signal input unit development support system.

Step 501 (Signal format input step)
Then, the designer graphically inputs the format of the source signal. Here, a signal of the format shown in FIG. 3 is taken as an example.

The designer inputs the signal format in the signal format input editor 604 as shown in FIG.

In FIG. 6, 600 is a central processing unit, 601 is a monitor, 602 is a keyboard, and 60 is a monitor.
Reference numeral 3 is a mouse, 604 is an execution screen of a signal format input editor, and 605 is a signal format of a video signal being input.

The signal format of the input video signal is stored in the storage device 404.

FIG. 7 shows the data structure of the signal format of the input video signal. In the figure, “Y” and “C” are signal names, and the signal Y is “(47,107).
− (562,480) ”is the vertex (47,107), (5
62,480) has a rectangular area with a diagonal line, and the signal C is "(43,13)-(558,106)".
Indicates that it has a rectangular area having vertices (43, 13) and (558, 106) as diagonal lines.

Step 502 of FIG. 5 (designating step)
Then, the designer specifies one of the signals to be input by the input unit. In this example, the mouse 603 moves the pointer cursor to the area of the target signal Y on the screen of the output device 402,
Then, the mouse button is clicked and the signal input port (line memory 104) for inputting the specified signal Y is specified from the signal input unit 101. The target signal Y
Can also be designated by inputting the signal name "Y".

Then, in step 503 (signal area extraction step), information of the area taken by the designated target signal Y in the input signal format of FIG. 3 is extracted from the storage device 404. When the Y signal is extracted, the information on the first line in FIG. 7 is extracted. In the present embodiment, the Y signal is a rectangular area (47, 107) in the original video signal.
-(562,480) is occupied.

In step 504 (signal input section control information generation step), signal input section control information is generated from the extracted signal area.

FIG. 8 shows a processing flowchart of the signal input section control information generation processing in step 504.

Details of the processing flowchart of FIG. 8 will be described below.

That is, in step 801, the address of the start pixel of the signal area is extracted. In this example, (47,10
7).

At step 802, the interval between the number of pixels in one line of the signal area and the next pixel is obtained as an increment of the address. In this example, the number of pixels 374 in one line is obtained.
The increment is 1.

In step 803, the number of lines in one field of the signal area and the number of pixels between lines are obtained as an address increment between lines. In this example, the number of lines is 516 and the increment between lines is 47.

In step 804, signal input section control information is generated based on the value obtained in the above step and the specification information of the signal input section 101.

The above-mentioned specification information of the signal input section 101 is
This is information for controlling the signal input unit, and is the number and contents of built-in registers of the signal input unit.

9 (a) and 9 (b) show examples of the signal input section control information.

FIG. 9A shows a case where the video input unit has several registers such as a counter and a register for increment value. The address of the pixel (47, 107) of the original video signal is set as the initial value of the counter, 1 is set as the increment of the counter, and the repetition period is 374, that is, one line, and the increment of the counter at the end of the processing of one line is set. 47
Has been set as.

FIG. 9B shows a control program in a high-level language such as C language. The address of the pixel (107, 47) of the original video signal is set as an initial value in a variable src, and the video processing unit 102 is set as an initial value in a variable dst.
The address of port_1, which is one of the input ports of the, is set. This is a program for transferring pixel data while incrementing the variables src and dst by one. When the transfer for one line is completed, 47 is added to the variable src and it is set to point to the address of the next line, and the variable dst sets the start address of port_1.

In the above description, the case where one signal (Y signal) of the video signals is designated has been described.
When a plurality of signals (for example, Y signal and C signal) are designated, the designation step 50 of FIG. 5 is performed for each signal.
2. The signal area extraction step 503 and the signal input unit control information generation step 503 are sequentially executed.

As described above, according to the present embodiment, the designer can input the signal format diagrammatically so that the signal input section control information can be obtained without the need for knowledge of the control of the signal input section. Can be generated.

(Second Embodiment) FIG. 10 shows a flow chart of a video processing system development support method.

At step 1001 (flow input step) in the figure, the designer inputs the function at the processing algorithm level of the video application to be developed as shown in FIG. 11 by the signal flow diagram using the function diagram editor. To do.

In FIG. 11, 1100 is a central processing unit, 1101 is a monitor, 1102 is a keyboard, 1103 is a mouse, 1104 is an execution screen of a functional diagram editor, 1105 is a signal flow diagram during input. Reference numeral 1106 is a screen for specifying the function of the processing block “HF1” being input.

FIG. 12 shows an example of a signal flow diagram of 1105. The signal flow diagram shows the processing of a video signal according to the flow of the signal.

In FIG. 12, reference numerals 1201 and 1202 denote input ports, which are blocks for inputting a current field signal and inputting a previous field signal, respectively. Is entered.

1203, 1204, 1205, 1 in FIG.
Reference numeral 206 denotes a video processing block, and 120
3, 1204 is a 12 MHz low-pass filter processing block, 1205 is an inter-field interpolation processing block, 120
Reference numeral 6 is a frequency conversion processing block.

An output port 1207 in FIG. 12 outputs an output signal processed by the video processing system from this block.

Incidentally, in FIG. 12, "PORT0" and "P"
ORT1 ”“ HF0 ”“ HF1 ”“ SEL0 ”“ HF
2 ”“ PORT2 ”is an identifier of each processing block (hereinafter,
This is called an ID), and a unique one is automatically given by this system.

In step 1001 of FIG. 10, the symbol 110 shown in FIG.
As shown by 6, the function of the video processing unit 105 is designated. FIG. 13A shows the function description of the 12 MHz low-pass filter processing block 1203, and FIG. 13B shows the function description of the inter-field interpolation processing block 1205.
The 12 MHz low pass filter is a 5-tap symmetrical filter. The inter-field interpolation processing is an interpolation selector, which alternately outputs two series of input pixels.

At this time, the function may be described by using the video control signal included in the video signal.

For example, FIG. 13B is a description of the function including the video control signal. Here, FSS is a video control signal, which represents an inter-field sub-sampling phase, and is a signal which becomes 1 when the sampling point is on the right.
The video control signal is shown with a "$" symbol at the beginning. In the inter-field interpolation processing, if the signal FSS is 0, the input 0 (current field signal),
The input 1 (previous field signal) is alternately output pixel by pixel. When the pixel is 1, the input 1 and the input 0 are output alternately pixel by pixel.

Next, in step 1002 (registration step) in FIG. 10, the video control signal used for the signal flow diagram input and function designation in step 1001 is registered. Here, the video control signal name and the method of deriving the value are input.

The video control signal may be a video control signal included in the source signal and a signal newly derived from the video control signal.

FIG. 14 shows a registration example (registration means 1400). The video control signal FSS is the Ct of the source signal.
The 20th signal value of the rl signal portion, and the video control signal notFSS is a signal whose value is the logical negation operation result of the control signal.

Then, in step 1003 (structure information extracting step) of FIG. 10, a signal flow structure list is extracted as the structure information from the signal flow diagram input in step 1001. The structure information extraction step 1003 and the flow input step 1001 constitute a function input step.

FIG. 15 shows an example of the extracted signal flow structure list. The signal flow structure list is data in which the description of each processing block or input / output port is described in the following format.

ID: Function description Input processing block designation The first and second lines describe the input port PORT0, and the first line description "PORT0" indicates the ID of the processing block. "INPUT" indicates the function.

Description "signal [0]" in the second line
(“Y [0]” in the present embodiment) indicates that data corresponding to the current pixel to be processed by the source signal is input.

The description on the 3rd-4th lines is applied to the input port P.
This is a description of ORT1, “PORT1” indicates the ID of the processing block, “INPUT” indicates its function, and “signal [−748 * 516]” indicates 516 * for the current pixel to be processed by the source signal. 748 = 385
This indicates that data of 968 pixels before is input. here,
516 is the number of lines in one field, 748 is the number of pixels in one line, data before 385968 pixels is data corresponding to one field before the current pixel to be processed, and these data are stored in these. Input from a frame memory (not shown).

The fifth to seventh lines are the description of the processing block HF.
0, the description “HF0” on the fifth line indicates the ID of the processing block, and “5TAP” indicates that the function is a 5-tap symmetric filter. The description on the 6th line indicates the coefficient of the filter, and the description "PORT" on the 7th line
"0" indicates that the output of PORT0 is used as the input of this processing block. The following description format is similar.

Then, in step 1004 (signal processing unit control information generating step) of FIG. 10, the video processing unit control information is generated using the signal flow structure list and the video control signal information registered in step 1002. To generate.

FIG. 16 shows a flowchart of the image processing section control information generation processing in step 1004. Less than,
The details of this flowchart will be described.

That is, in step 1601, allocation of each processing block to the signal processing module 105 is determined.
In this example, for example, the 12 MHz LPF processing block 120
3 is assigned to VPE1 and VPE2, and the inter-field interpolation processing block 1205 is assigned to VPE3. Here, VPE1, VPE2
VPE3 is an identifier of each signal processing module 105.

In step 1602 (generation step and connection information generation step) of FIG. 16, an assembler program which is control information of each video processing module 105 and a connection list which is connection information between each video processing module 105 are generated.

17 (a), (b), (c), (d)
Shows an example of an assembler program and connection list.

FIG. 17A shows an assembler program of the video processing module VPE1.

"PROG_HF_1:" in the first line is an identifier indicating a program name.

“While (1)” on the second line indicates that the video processing module repeatedly executes the part surrounded by “{” on the second line to “}” on the ninth line. .

"If (CLK)" on the third line executes the part surrounded by "}" on the third line "{" to the eighth line on the rising edge of the control clock CLK signal. It means to do.

The fourth line "ld 0, ALU" indicates that 0 is loaded into the arithmetic unit ALU, that is, initialization is performed.

The fifth line "mul -0.232 * DF
[0] ”indicates that the content of DF [0], which is the internal register 0, is multiplied by −0.232 and the result is added to the content of the arithmetic unit ALU.

Line 6 "mul + 0.125 * DF
[1] ”indicates that the content of DF [1] which is the internal register 1 is multiplied by 0.125 and the result is added to the content of the arithmetic unit ALU. 7th line “mul + 0.982 *
DF [2] ”indicates that the content of DF [2], which is the internal register 2, is multiplied by 0.982 and the result is added to the content of the arithmetic unit ALU.

Similarly, FIG. 17B is an assembler program of the signal processing module VPE2.

In some cases, an assembler program including the description of the video control signal is generated. FIG. 17
An example is shown in (c).

FIG. 17C shows an assembler program of the video processing module VPE3, which includes a description of the name FSS of the video control signal. In this case, this assembler program is not a complete program and is converted into a complete assembler program by the control signal replacement process described later.

Hereinafter, FIG. 17C will be described.

The second line "while (1)" means that the signal processing module has the second line "{" to the ninth line "}".
Indicates that the part surrounded by is repeatedly executed.

"If (CLK)" on the third line executes the part surrounded by "}" on the third line "{" to the fifth line on the rising edge of the control clock CLK signal. It means to do.

The 4th line "ld DF [$ FSS], AL
U ”is supplied to the arithmetic unit ALU, and the video control signal F
Indicates that the contents of the internal register DF [$ FSS] corresponding to the value of SS is loaded. That is, when the control signal FSS is 0, the content of DF [0] is loaded, and when FSS is 1, the content of DF [1] is loaded.

In the sixth line, "if (CLK)", the signal processing module executes the part surrounded by the sixth line "{" to the eighth line "}" when the control clock CLK signal rises. It means to do.

The 7th line "ld DF [1- $ FSS],
"ALU" indicates that the content of the internal register DF [1] is loaded to the arithmetic unit ALU when the control signal FSS is 0, and the content of the internal register DF [0] is loaded when the FSS is 1. .

FIG. 17D shows an example of the connection list.

"NETLIST:" on the first line is an identifier representing a connection list.

The second to seventh lines represent the connection relationships of the signal processing modules, and have the following format.

Input identifier: Output identifier Indicates that the output designated by the output identifier is connected to the input designated by the input identifier.

The second line is the signal processing module VPE1.
It means that the output 0 of the signal processing module VPE0 is connected to the input 0 of.

Hereinafter, the same description is applied from the third line to the seventh line.

With the above description, as shown in FIG. 18 (a), the 12 MHz LPF processing is VPE1, VPE.
2 is assigned and processing is performed.

In steps 1603 to 1606, a video processing unit control program executed on the control unit 103 is generated.

FIG. 19 shows a part of an example of the generated video processing unit control program.

The control information is a program executed on the control unit 103, and includes (1) a portion for reading a video control signal from a source signal or a portion for deriving a newly defined video control signal, and (2) a video processing unit. The control information (assembler program) replacement part of the video control signal result, (3) the download part of the connection list to the video processing part, and (4) the download part of the control information (assembler program) to the video processing part. Consists of.

In step 1603 (reading unit generation step) of FIG. 16, a video control signal included in the source signal is read based on the information of the video control signal registered in step 1002 of FIG. 10, and a new video control is performed. Generate control information that performs the derivation of the signal.

An example of the control information thus generated is shown in the first and second lines of FIG. The control information of FIG. 19 indicates a program for controlling the signal input unit for MUSE decoding / video processing module, and is executed for each field of the video signal. The first row of FIG. 19 shows that the video control signal FSS is obtained as the 20th pixel value of the Ctrl signal portion in the source signal. "G
“etCtrlData” is a process of controlling the signal input unit 101 to input a corresponding signal from the Ctrl signal portion of the source signal, and constitutes the input unit 1901.
This is a subroutine executed by the control unit 103. Also,
The second line shows that the video control signal notFSS is obtained as the logical negation value of the video control signal FSS. [! ] Is a symbol indicating logical negation.

Subsequently, in step 1604 (replacement portion generation step) of FIG. 16, if the assembler and connection list generated in step 1602 include a video control signal, of the assembler and connection list,
The portion described using the video control signal is replaced with the actual value of the video control signal to complete the generation of the control information.

The third line in FIG. 19 shows an example of the generated control information.

[Translate (PROG_SEL
_T, PROG_SEL) ”replaces the description part of the video control signal included in the assembler program PROG_SEL_T with the actual video control signal value, and the resulting assembler program is PROG_SE).
A process of returning as L, and configuring the replacement unit 1902,
This is a subroutine executed by the control unit 103.

The replacement results are shown in FIGS. 20 (a) and 20 (b).

FIG. 20A shows the video control signal F.
17 shows the replacement result of the assembler program PROG_SEL_T shown in FIG. 17C when SS is 0.
The value 0 of the control signal FSS is reflected in the description including the video control signals in the 4th and 7th lines of 7 (c).

Similarly, FIG. 20B shows the replacement result when the video control signal FSS is 1.

As shown in FIGS. 18B and 18C, the field interpolation processing is assigned to the signal processing module VPE3 and the processing is performed.

In step 1605 of FIG. 16, if the connection list generated in step 1602 or the connection list includes a video control signal description, step 16
The connection list obtained as a result of replacement with 04 is the video processing unit 10
The control information to be downloaded to the second bus switch 106 is generated.

The fourth line of FIG. 19 shows an example of the generated control information.

[DownLoad (BUSSW, NET
17) to the connection bus switch BUSSW.
This means that the connection list NETLIST shown in (d) is downloaded. “DownLoad” is an instruction to download specified information to a specified portion of the video processing unit 102, and is a subroutine executed on the control unit 103.

In step 1606 of FIG. 16, the assembler program generated in step 1602 or the resulting assembler program replaced in step 1604 if the assembler program includes a video control signal description, is stored in each of the video processing units 102. Generate control information to be downloaded to the signal processing module.

An example of the generated control information is shown in the fifth, sixth and seventh lines of FIG.

The fifth line, "DownLoad (VPE
1, PROG_HF_1) ”is the signal processing module V
To PE1, the assembler program P shown in FIG.
This means that ROG_HF_1 is downloaded and constitutes the output unit 1903.

The sixth line, "DownLoad (VPE
2, PROG_HF_2) ”is the signal processing module V
To PE2, the assembler program P shown in FIG.
This means that ROG_HF_2 is downloaded and constitutes the output unit 1903.

The seventh line, "DownLoad (VPE
3, PROG_SEL) ”is the signal processing module VP
It represents that the assembler program PROG_SEL shown in FIGS. 20A and 20B is downloaded to E3.
The output unit 1903 is configured.

The signal processing modules VPE1,
VPE2 and VPE2 each represent a predetermined one signal processing module among the plurality of signal processing modules 105 shown in FIG.

As described above, the generated control information and the above-mentioned GetCtrlData, Translat
If you use a subroutine such as e or DownLoad,
The video processing unit 102 can be controlled to perform video processing.

GetCtrlData, Transla
A description of the processing contents of te and DownLoad will be omitted.

Although not shown, the generation step and connection information generation step 1602, the reading section generation step 1603, and the replacement section generation step 1604 of FIG. 16 are performed.
The generation means, the connection information generation means, the reading portion generation means, and the replacement portion generation means, which have the same functions as the above, are provided inside the video processing portion control information generation means 412 of the central processing unit 403 in FIG.

Therefore, in this embodiment, the control unit 103
Has an assembler program (control information) including the name FSS of the video control signal in advance, as shown in FIG. Then, the video signal is input to the signal input unit 10
When input to 1, the video control signal FSS included in the video signal is read by the control unit 103, and the actual value (content) of the video control signal FSS is loaded. After that, the video control signal FSS included in the control information of FIG. 17C is replaced with the actual value of the video control signal FSS, and the replaced control information is shown in FIGS. 20A and 20B. You can get as follows. Therefore, when the replaced control information is downloaded to the signal processing modules VPE1, VPE2, VPE3, the signal processing modules VPE1, VPE2, VPE are downloaded.
3 processes the video signal according to the contents of the video control signal included in the downloaded control information.

In this embodiment, the video processing hardware having the DSP for executing the processing by the assembler program in the video processing unit is targeted, but the video processing hardware having the video processing circuit controlled by the control signal is used. May be targeted.

As described above, according to the present embodiment, by describing the function of the signal flow diagram and the function of the processing block in the signal flow diagram by using the video control signal, the video processing by the video control signal is performed. It is possible to easily generate the video processing control information for controlling.

(Third Embodiment) FIG. 21 shows a flowchart of an example of a video application development support system. This flowchart is added to the first embodiment or the second embodiment, and in step 2101 (flow input step), the designer uses the function diagram editor to develop the signal flow diagram. The function at the processing algorithm level of the target video application is input as shown in FIG.

Next, in step 2102 (structure information extracting step), signal flow structure data is extracted from the signal flow diagram input in step 2101. FIG. 15 shows an example of the extracted signal flow structure data.

Subsequently, in step 2103 (calculation step), the input output signal rate of each video processing module 105 is obtained from the function of the video processing module 105 and the input signal rate.

For example, input ports PORT0, PORT
Since 1 is a block that performs a process of inputting one line from the Y signal portion of the source signal, its output signal rate is equal to the input signal rate and is 748 (pixel / line).

Further, the video processing blocks HF0, HF1
Is a 5-tap symmetric filter, so its output signal rate is equal to the input signal rate, each 748 (pixels / line).

Further, since the video processing block SEL0 is a 2-input interpolation selector, its output signal rate is twice the input signal rate, which is 1496 (pixels / line).
Is.

In addition, the video processing block HF2 has 32 bits.
Since the frequency is converted from MHz to 24 MHz, the output signal rate is 24/32 times the input signal rate, which is 1122 (pixel / line).

Then, at step 2104 (display step), the output signal rate obtained at step 2103 is displayed on the 1104 functional diagram editor.

FIG. 22 shows an example of displaying the output signal rate. On the right shoulder of each processing block, the output signal rate of that processing block is shown.

Although not shown, a calculation means and a display means having the same functions as the calculation step 2103 and the display step 2104 of FIG. 21 are provided in the central processing unit 403 of FIG.

As described above, according to the present embodiment, by obtaining and displaying the signal rate of the video processing block, the designer does not always be aware of the signal rate and the signal input unit 101 and the video processing unit. It becomes possible to develop the control information of the module 105.

The present embodiment has been described as being added to the first or second embodiment, but in addition to this, as being added to the fourth embodiment described below. Good.

(Fourth Embodiment) FIG. 23 shows a flowchart of an embodiment of the video processing application development support system of the present embodiment.

In step 2301 (flow input step) of FIG. 23, the designer uses the function diagram editor to show the function at the processing algorithm level of the video application to be developed by the signal flow diagram as shown in FIG. input.

FIG. 24 shows an example of a signal flow diagram.
In this signal flow diagram, a plurality of signal paths (signal paths) are formed between two predetermined image processing units.

In the figure, 2401, 402, 24
03, 2404, 2405, 2406, and 2407 are the same as those shown in FIG.

Further, in the figure, 2408, 2409
Is a frequency conversion processing block similar to 2406.

Further, 2410, like 2405, is an inter-field interpolation block.

Note that, as indicated by symbol 1106 in FIG.
Specify the function when inputting the signal flow diagram.

In FIG. 24, the black rhombus with the symbol 2411 is the 12 MHz low-pass filter 2403.
And a plurality of signal paths between the output port 2407 and another 12 MHz low-pass filter 240
4 and the output port 2407 represent an exclusive selection of a plurality of signal paths, where any one of the plurality of paths is
This indicates selection in a path designation step 2302 described later.

In step 2302 (routing step) of FIG. 23, the designer selects any one of the plurality of signal paths.
Specify one. In this embodiment, the mouse 11 of FIG.
At 03, the pointer cursor is moved onto each processing block on the functional diagram editor 1104 of the output device 1104, and the mouse button is clicked there.

FIG. 25 (a) shows an example of a signal flow diagram after the path is designated. Here, the selected path is displayed with a solid line, and the unselected path is displayed with a broken line.

In the example of FIG. 25 (a), paths connecting HF0, HF1 to SEL0 and SEL0 to HF2 are selected, and HF0 to HF3, HF1 to HF4, HF are selected.
3, the path from HF4 to SEL1 is not selected.

Then, in FIG. 23, step 230 is performed.
In 3 (structure information extraction step), the signal flow structure list is extracted from the signal flow diagram. At this time, if there are multiple paths, the signal flow structure list is extracted only for the specified path.

FIG. 26 (a) shows an example of the signal flow structure list extracted from the signal flow diagram shown in FIG. 25 (a). This is similar to FIG. 15 described above.

Further, FIG. 25 (b) shows another example of the signal flow diagram. This is an example when the other path is selected in step 2302 in the signal flow diagram of FIG. Further, FIG. 26B shows the signal flow structure list extracted from FIG. 25B.

In FIG. 23, step 230 is continued.
In 4 (signal processing unit control information generation step), the image processing unit control information is generated using the signal flow structure list. This is the same processing as step 1004 of the above-described second embodiment.

As described above, according to the present embodiment, the designer describes a plurality of video processing algorithms as a plurality of signal flow paths at the time of studying a video processing algorithm and generates control information. By designating and generating one of them, the history of the algorithm examination remains and the development work can be easily maintained.

(Fifth Embodiment) FIG. 27 shows a functional block diagram of a video processing system development supporting apparatus according to an embodiment of the present invention.

In FIG. 27, reference numeral 2701 is a signal format input means for the designer to graphically input the format of the source signal. The designer inputs the format of the video signal to be developed as shown in FIG.

The signal format input by the designer is the format of the signal format data shown in FIG.
2702 is stored in the signal format information storage means.

Reference numeral 2705 denotes a signal flow diagram input means, through which the designer inputs the signal flow diagram representing the algorithm of the video processing application and the function of each block.

An example of the signal flow diagram is shown in FIG.

[0225] An example of function designation of blocks in the signal flow diagram is shown in Figs. 13 (a) and 13 (b). The information of the signal flow diagram is stored in the signal flow diagram data information storage unit 2706.

FIG. 28 shows an example of the data. Figure 2
The signal flow diagram data information shown in 8 has information of the following format for one block.

Identifier: (arrangement of graphic information) (arrangement of functional information) (arrangement of connection information) Information from the first line to the fourth line in FIG. 28 is the information of the video processing block 1201 and is the first Line "PORT0"
Represents the identifier name of the video processing block.

The second line "(OVAL, 0,30,1
5, 35) ”represents that the shape on the signal flow diagram of the video processing block is an ellipse having a coordinate of (0, 30) as an upper left apex and a width of 35 and a height of 15. .

The third line "(INPUT, Y, 0)"
Is a function of the video processing block is an input port,
This indicates that the data corresponding to the current line of the current field to be processed of the signal Y is input.

The fourth line "(SOURCE_SIGNA
L) ”is an identifier name of a video processing block that is an input of the video processing block, and the video processing block PO
It indicates that RT0 receives the source signal.

Further, the information from the fifth line to the eighth line in FIG. 28 is information of the video processing block 1203, and "HF0" on the fifth line represents the identifier name of the video processing block. 6th line "(BOX, 50,30,15,3
5) ”indicates that the shape on the signal flow diagram of the video processing block has coordinates (50, 30) as the upper left apex and a width of 3
It shows that it is a quadrangle of size 5 and size 15.

The seventh line, "(HF, 5TAP, 0.98
2, 0.125, -0.232) "is a symmetric 5-tap horizontal filter in which the function of the video processing block is 0.982, 0.125, -0.23, and filter coefficients are 0.982, 0.125, and -0.23, respectively.
It represents 2.

The "(PORT0)" in the eighth line indicates that the video processing block HF0, which is the identifier name of the video processing block that is the input of the video processing block, receives the output of the processing block PORT0. ing.

The same applies to the ninth and subsequent lines.

Further, in the signal flow diagram, when there are a plurality of signal flows for realizing an algorithm or when there are a plurality of algorithm candidates, a plurality of algorithms are expressed as a plurality of signal flow paths and the plurality of signal flow paths are input. It is also possible to do so. Figure 2
An example is shown in FIG.

Reference numeral 2707 denotes a signal path designating means,
The designer selects one from multiple signal flow paths.

Reference numeral 2708 denotes a signal flow structure list extraction means, which extracts the signal flow structure list from the signal flow diagram input by the designer in 2705. At this time, if there are multiple signal flow path selections,
Only the information of the selected signal flow path is obtained from the signal path designating unit 2707.

An example of the signal flow structure list is shown in FIGS. 15, 26 (a) and 26 (b).

FIG. 15 corresponds to the signal flow diagram of FIG.

26 (a) and 26 (b) are shown in FIG. 25 (a),
Each corresponds to the signal flow diagram in (b).

Reference numeral 2710 is a control signal registration means for registering the name and the derivation method of the video control signal used by the designer to specify the signal flow diagram and the function. The video control signal is a control signal included in the source signal or a signal newly derived from the control signal.

The registered control signal information is stored in the control signal information storage means 2711 in the format shown in FIG.

Reference numeral 2703 denotes a signal area extraction means, which reads the signal format information from the signal format information storage means 2702, reads the signal name to be input from the signal flow structure list extraction means 2708, and extracts the area of the designated signal. To do.

In this embodiment, the input port 120
Since 1 is a port for inputting the source signal Y signal portion, it is necessary to control the input portion for inputting the Y signal. Therefore, the signal area extracting means 2703 reads Y as a signal name to be input. Be done.

Reference numeral 2704 denotes a signal input section control information generating means, which outputs the area information of the input target signal from the signal area extracting means 2703 to the image processing section of the input target signal from the signal flow structure list extracting means 2708. The input port information of is read and the signal input part control information is generated.

In the present embodiment, the information of the first line in FIG. 7 is read as the area information of the input target signal, and PORT0 is read as the input port information.

FIG. 8 shows a processing flowchart of the signal input section control information generating means.

The generated signal input section control information is shown in FIGS. 9 (a) and 9 (b).

Reference numeral 2709 denotes image processing unit control information generating means, which is the signal flow structure list extracting means 270.
8 to read the signal flow structure list and the video control signal information from the control signal information storage means to generate the video processing unit control information.

FIG. 16 shows a processing flowchart of the video processing section control information generation.

The generated video processing unit control information is shown in FIGS. 19 and 17 (a) to (d).

When there are a plurality of signals to be input, the signal area extracting means 2703 and the signal input section control information generating means 2704 perform the processing a plurality of times.

The signal area extracting means 2703 is
Instead of the signal format information storage means 2702, the signal format information may be directly read from the signal format input means.

[0254] Also, the signal path designating means 2707
Alternatively, the signal flow structure list extraction means 2708
Is the signal flow diagram data information storage means 2706.
Instead of reading the signal flow diagram data from, the signal flow diagram data may be read from the signal flow diagram input means.

Further, the video processing section control information generating means 2
709 is the control signal information storage means 2711
The video control signal may be read from the control signal registration means 2710 instead of reading the video control signal information from the. Also, the image processing unit control information generating means 2709 is used by the control signal information storing means 2711 and the control signal registering means 2710.
May be incorporated.

As described above, according to the present embodiment, the designer can input the signal format diagrammatically, so that the designer does not need to have knowledge of the control of the signal input section and the signal input section control information can be obtained. Can be generated.

Further, by describing the function of the signal flow diagram and the function of the processing block in the signal flow diagram by using the video control signal, the video processing control information for performing the video processing control by the video control signal is easily generated. It becomes possible.

Further, by obtaining and displaying the signal rate of the video processing block, the designer can carry out the development without having to always be aware of the signal rate.

When a video processing algorithm is examined, a plurality of video processing algorithms are described as a plurality of signal flow paths, and when generating control information, one of them is designated and generated. The history of the examination remains, and it becomes possible to easily maintain the development work.

[0260]

As described above, according to the inventions of claims 1 to 3 and claims 11 to 13, the format of the signal to be processed is graphically input, and
Since the designer can simply specify the signal included in the processing target signal, the area information of the specified signal in the format of the processing target signal can be automatically extracted and the control information of the signal input unit can be generated. The designer can easily generate the control information of the signal input unit without the need to store all the detailed knowledge and information regarding the control of the signal input unit or to search repeatedly.

According to the inventions of claims 4 to 6 and 8 and claims 14 to 16 and 18, the designer sets the function description information of the signal processing unit to the name of the control signal. In addition to inputting in the form of registering the method of deriving the content of the control signal, when the processing target signal including the control signal is input, the name of the control signal in the function description information The portion can be easily replaced with the content of the control signal included in the input signal to be processed, and the control information of the signal processing unit can be easily generated.

Further, according to the invention described in claim 7, it is possible to obtain the combined effect of the effects of the invention of claim 1 and the invention of claim 4.

In addition, according to the ninth and the nineteenth aspects of the invention, the designer inputs a signal flow diagram in a form having a plurality of signal paths between two predetermined signal processing units, and the flow diagram thereof is shown. It is possible to repeat selecting and designating an arbitrary one of the plurality of signal paths of, and repeatedly generating control information and the like of the signal processing unit based on the structural information of the formed signal flow diagram. Since the configuration is made possible, it is possible to leave a history of the algorithm of the signal processing application, and it is possible to easily study the algorithm and appropriately develop appropriate control information after the study.

In addition, according to the tenth and twentieth aspects of the present invention, since the signal rate of each signal processing unit is displayed, the designer repeatedly investigates the signal rate of each signal processing unit. The control information and the like of each signal processing unit can be easily generated without searching.

According to the signal processing device and the processing method of the invention described in claims 21 to 32, when the processing target signal including the control signal is input, the control signal name in the control information is changed to the control signal name. After replacing with the content of the input control signal, the control information including the content of this control signal is output to the signal processing unit, so the signal processing for the signal to be processed is changed according to the content of the input control signal. it can.

In particular, according to the invention described in claims 24 and 30, when the video signal is input, the broadcast system of the video signal is detected, and the control information corresponding to the broadcast system is sent to the signal processing unit. Since it is output, it is not necessary to provide a signal processing unit for each video signal of different broadcasting systems even if there are a plurality of broadcasting systems, and the signal processing unit can be shared.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a hardware configuration of a video processing system according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of a signal processing module.

FIG. 3 is an explanatory diagram of a video signal format according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a hardware configuration of a video processing system development support system according to the first embodiment of this invention.

FIG. 5 is a diagram showing a flowchart of a main routine of the signal input unit development support system according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a hardware configuration of a signal input unit development support system according to the first embodiment of this invention.

FIG. 7 is an explanatory diagram showing an example of signal format information in the hardware configuration of the signal input unit development support system according to the first embodiment of this invention.

FIG. 8 is a flowchart showing details of the process of step 504 in FIG.

FIG. 9 is a diagram showing an example of generated signal input unit control information.

FIG. 10 is a diagram showing a flowchart of a main routine of a video processing system development support system according to the second embodiment of the present invention.

FIG. 11 is an explanatory diagram of a hardware configuration of a video processing system development support system according to the second embodiment of this invention.

FIG. 12 is a diagram showing an example of a signal flow diagram in the video processing system development support system according to the second embodiment of the present invention.

FIG. 13 is a diagram showing an example of a function designation description of a processing block and an example of the case where the description includes a video control signal.

FIG. 14 is a diagram showing an example of video control signal information.

FIG. 15 is a diagram showing an example of a signal flow structure list.

16 is a flowchart showing details of the process of step 1004 of FIG.

FIG. 17 is a diagram showing an example of a generated assembler program, an example including a video control signal in the program, an example of a generated assembler, and an example of a generated connection list.

FIG. 18 is a diagram illustrating an operation of the signal processing module by the generated assembler.

FIG. 19 is a diagram showing an example of a generated video processing unit control program.

FIG. 20 is a diagram showing an example of an assembler program as a result of replacing the value of a video control signal.

FIG. 21 is a diagram showing a flowchart of a main routine of the video processing system development support system according to the third embodiment of the present invention.

FIG. 22 is a diagram showing an example of a signal flow diagram showing a signal rate.

FIG. 23 is a diagram showing a flowchart of a main routine of the video processing system development support system according to the fourth embodiment of the present invention.

FIG. 24 is a diagram showing an example of a signal flow diagram including a plurality of signal paths.

FIG. 25 is a diagram showing an example of a signal flow diagram in which one path is selected from a plurality of signal paths.

FIG. 26 is a diagram showing an example of a signal flow structure list in which one path is selected from a plurality of signal paths.

FIG. 27 is a diagram showing functional blocks of a video processing system development support device according to a fifth embodiment of the present invention.

FIG. 28 is a diagram showing an example of signal flow diagram information.

29 is an explanatory diagram showing a schematic operation of a hardware configuration of the program development support system for the video processing system of FIG. 4. FIG.

[Fig. 30] Fig. 30 is a flowchart showing detection of a broadcasting system in a television receiver and switching of signal processing according to the detection result.

[Explanation of symbols]

101 signal input unit 102 video processing unit 103 control unit 104 signal input port 105 signal processing module (signal processing unit) 201 signal processing module (signal processing unit) 202 internal register 203 internal register 204 internal register 205 internal register 206 arithmetic unit 212 program Storage unit 301 Method detection unit 400 Signal designation unit (designation unit) 401 Input device 402 Output device 403 Central processing unit 404 Storage device 1904 Registration unit 1901 Input unit 1902 Replacement unit 1903 Output unit 2701 Signal format input unit 2702 Signal format information storage unit 2703 Signal Area Extraction Means 2704 Signal Input Control Information Generation Means 2705 Signal Flow Diagram Input Means 2706 Signal Flow Diagram Data Information Storage Means 2707 Signals Scan designation unit 2708 signal flow structure list extraction means 2709 video processor control information generating unit 2710 controls the signal registering means 2711 control signal information storage unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location G06F 17/50 H04N 5/46 7/015 H04N 7/00 A (72) Inventor Tamotsu Nishiyama Osaka 1006 Kadoma, Kadoma-shi, Matsushita Electric Industrial Co., Ltd.

Claims (32)

[Claims] 1. A method for supporting development of a signal processing system for developing the control information in a signal processing system for performing a predetermined signal processing according to control information, wherein a format of a signal to be processed composed of a plurality of signals is input. A signal format input step, a designation step of designating a part or all of the signals included in the processing target signal, and the signal designated in the designating step is the format of the processing target signal input in the signal format input step. A signal area extracting step of extracting information of an area to be taken in, and a signal input section of generating control information for a signal input section of the signal processing system based on the information of the signal area extracted in the signal area extracting step. A method for supporting the development of a signal processing system, comprising: a control information generating step. 2. The signal according to claim 1, wherein the step of designating the signal also designates an input port to which the designated signal is to be input, out of a plurality of input ports on the signal processing system. Processing system development support method. 3. When a plurality of signals are designated in the designation step, the designation step, the signal area extraction step, and the signal input unit control information generation step are executed for each designation signal. The method for supporting development of a signal processing system according to claim 1 or 2. 4. A method for supporting development of a signal processing system for developing the control information in a signal processing system for performing predetermined signal processing according to control information, comprising a functional description of a signal processing unit provided in the signal processing system, A function input step of inputting function description information described using the name of a control signal included in the target signal, a registration step of registering derivation information of the content of the control signal, and a function description input in the function input step. A method for supporting development of a signal processing system, comprising: a signal processing unit control information generation step of generating control information of the signal processing unit from information and derivation information of the content of the control signal registered in the registration step. 5. A signal processing unit control information generating step, a generation step of generating control information of the signal processing unit described by using the name of a control signal, from the function description information input in the function input step, and a registration step. The reading unit generating step of generating a reading unit for reading the contents of the control signal from the derivation information of the contents of the control signal registered in the step, and the control information name of the control information of the signal processing unit generated in the generating step, 5. The method for supporting development of a signal processing system according to claim 4, further comprising: a replacement unit generation step for generating a replacement unit for replacing the portion described by using the content of the control signal read in the reading step. . 6. The function input step inputs functional description information of a plurality of signal processing units, and further, based on the functional description information of the plurality of signal processing units input in the function input step, a plurality of these functional description information The development support method for a signal processing system according to claim 4 or 5, further comprising a connection information generating step of generating connection information for connecting the signal processing unit. 7. A signal format input step of inputting a format of a processing target signal composed of a plurality of signals, a designation step of designating a part or all signals included in the processing target signal, and the designation. The signal specified in step, based on the signal area extracted in the signal area extraction step, the signal area extraction step of extracting the area taken in the format of the signal to be processed input in the signal format input step, And a signal input unit control information generating step of generating control information for a signal input unit of the signal processing system. 8. The function input step comprises: a flow input step of inputting a signal processing algorithm and a function of a signal processing unit used for the signal processing by a signal flow diagram focusing on a flow of a signal to be processed; And a structure information extraction step of extracting the structure information from the signal flow diagram input in step (4). The signal processing unit control information generation step includes the structure information extracted in the structure information extraction step and the control signal registered in the registration step. The method for supporting development of a signal processing system according to claim 4 or 7, wherein the control information of the signal processing unit is generated from the derivation information of the content. 9. A method for developing a signal processing system for developing the control information in a signal processing system that performs predetermined signal processing according to control information, comprising: a signal processing algorithm; and a plurality of signal processing units used for the signal processing. A flow input step of inputting a function by a signal flow diagram focusing on the flow of a signal to be processed and configured by a plurality of signal paths between two predetermined signal processing units, and among the signal flow diagrams, A routing step of selecting one signal path among a plurality of signal paths taken between two predetermined signal processing units; and a signal path not designated in the routing step in the signal flow diagram input in the flow input step. The structure information extracting step for extracting the structure information of the part except the Development process of a signal processing system characterized by the structure information and a signal processing unit control information generating step of generating control information for the signal processing unit. 10. A flow input step of inputting a signal processing algorithm and functions of a plurality of signal processing units used for the signal processing by a signal flow diagram focusing on the flow of a signal to be processed, and a structure from the signal flow diagram. A structural information extraction step of extracting information, a calculation step of calculating a signal rate of each signal processing unit from the structural information extracted in the structural information extraction step, and a display step of displaying the signal rate calculated in the calculation step. The development support method for a signal processing system according to claim 1, claim 4, or claim 9, wherein the method includes: 11. A signal processing system development support device for developing the control information in a signal processing system for performing predetermined signal processing according to control information, wherein a format of a signal to be processed composed of a plurality of signals is input. Signal format input means, designating means for designating a part or all of the signals included in the processing target signal, and the signal designated by the designating means is the format of the processing target signal input by the signal format input means. And a signal input section for generating control information for the signal input section of the signal processing system based on the information of the signal area extracted by the signal area extraction section. A development support device for a signal processing system, comprising: a control information generating means. 12. The signal according to claim 11, wherein the designating means for designating a signal also designates an input port to which the designated signal is to be input among a plurality of input ports on the signal processing system. Processing system development support device. 13. A processing object stored by the format storage means when the format storage means stores the format of the signal to be processed input by the signal format input means, and when a plurality of signals are specified by the specification means. The signal format is read out, and for each designated signal, the designation of the signal by the designation means, the extraction of the area by the signal area extraction means, and the control information for the signal input section by the signal input section control information generation means are sequentially performed. 13. The development support device for a signal processing system according to claim 11 or 12, which executes generation. 14. A development support device for a signal processing system for developing the control information in a signal processing system that performs predetermined signal processing according to control information, comprising: a functional description of a signal processing unit included in the signal processing system, Function input means for inputting function description information described using a control signal included in the target signal, registration means for registering derivation information of the control signal, function description information input by the function input means, and A development support device for a signal processing system, comprising a signal processing unit control information generation unit for generating control information of the signal processing unit from derivation information of a control signal registered by the registration unit. 15. The signal processing unit control information generating unit includes a generating unit that generates the control information of the signal processing unit described by using a control signal from the function description information input by the function input unit, and a registration unit. A reading unit generating unit that generates a reading unit that reads the contents of the control signal from the registered derivation information of the control signal, and a portion of the control information of the signal processing unit generated by the generating unit that is described using the control signal. 15. The development support device for a signal processing system according to claim 14, further comprising: a replacement unit generation unit that generates a replacement unit that replaces the contents of the control signal read by the reading unit. 16. The function input means inputs the function description information of a plurality of signal processing units, and further, based on the function description information of the plurality of signal processing units input by the function input means, a plurality of these function processing units. The development support device for a signal processing system according to claim 14 or 15, further comprising connection information generation means for generating connection information for connecting the signal processing unit. 17. A signal format input means for inputting a format of a processing target signal composed of a plurality of signals, a designating means for designating a part or all of the signals included in the processing target signal, and the designation. Based on the signal area extracted by the signal area extraction means, the signal area specified by the signal area extraction means for extracting an area to be taken in the format of the signal to be processed input by the signal format input means. 15. The signal processing system development support apparatus according to claim 14, further comprising: a signal input unit control information generating unit that generates control information for the signal input unit of the signal processing system. 18. A flow input means for inputting an algorithm of a signal processing and a function of a signal processing section used for the signal processing by a signal flow diagram focusing on a flow of a signal to be processed, and the flow input means. And the structure information extracting means for extracting the structure information from the signal flow diagram input in step (1), wherein the signal processing unit control information generating means includes the structure information extracted by the structure information extracting means and the control signal registered by the registering means. 18. The development support device for a signal processing system according to claim 14, wherein control information for the signal processing unit is generated from the derived information. 19. A signal processing system development device for developing the control information in a signal processing system for performing predetermined signal processing according to control information, comprising: a signal processing algorithm and a plurality of signal processing units used for the signal processing. A flow input means for inputting a function by a signal flow diagram focusing on a flow of a signal to be processed, the flow diagram being configured in a plurality of signal paths between two predetermined signal processing units; A routing means for selecting one signal path among a plurality of signal paths taken between two predetermined signal processing parts; and a signal path not designated by the routing means in the signal flow diagram input by the flow input means. The structure information extracting means for extracting the structure information of the portion excluding Development aid device signal processing system characterized by a signal processing unit control information generating means for generating control information No. processor. 20. Flow input means for inputting a signal processing algorithm and functions of a plurality of signal processing units used for the signal processing by a signal flow diagram focusing on the flow of a signal to be processed, and a structure from the signal flow diagram. Structure information extraction means for extracting information, calculation means for calculating the signal rate of each signal processing unit from the structure information extracted by the structure information extraction means, and display means for displaying the signal rate calculated by the calculation means The development support device for a signal processing system according to claim 11, 14, or 19, characterized by comprising. 21. A signal input section for inputting a processing target signal including a control signal, a signal processing section for processing a processing target signal input to the signal input section according to input control information, and the signal input. The control information generated in advance using the name of the control signal included in the processing target signal input to the unit is stored, and the processing target signal input to the signal input unit is input, and the input processing target signal is input. And a control unit for replacing the control signal name included in the control information with the content of the control signal included in the control signal and outputting the control information including the content of the control signal to the signal processing unit. apparatus. 22. The control unit is pre-registered with a storage unit for storing control information generated by using the name of the control signal, and a method for deriving the content of the control signal included in the control information from the signal to be processed. Registration means, based on the derivation method registered in the registration means, from the input processing target signal, an input unit for extracting the content of the control signal corresponding to the control signal name included in the control information, A replacement unit that replaces the control signal name included in the control information with the content of the control signal extracted by the input unit, and an output that outputs the control information containing the content of the control signal replaced by the replacement unit to the signal processing unit. 22. The signal processing device according to claim 21, further comprising: 23. The signal processing apparatus according to claim 21, wherein the input processing target signal is a video signal. 24. The signal input unit receives any one of a plurality of types of video signals corresponding to a plurality of broadcasting systems, and the signal processing unit is commonly used for processing a plurality of video signals of different broadcasting systems. The control unit stores a plurality of pieces of control information corresponding to a plurality of broadcasting systems in advance, and includes a system detecting unit for detecting a broadcasting system of the video signal input to the signal input unit. 24. The control information corresponding to a broadcasting system is output to the signal processing unit.
The signal processing device described. 25. The signal processing device according to claim 23, wherein the control signal included in the video signal is a sampling phase signal. 26. The signal processing device according to claim 24, wherein the plurality of types of broadcasting systems respectively corresponding to the plurality of types of video signals include an NTSC system and a MUSE system. 27. The control information is generated in advance by using the name of the control signal included in the processing target signal to be input, and then the processing target signal including the control signal is input, and then the input The control signal name included in the control information is replaced with the content of the control signal included in the processed signal, and then the input processing target signal is processed using the control information including the content of the control signal. Signal processing method. 28. When replacing the control signal name included in the control information with the content of the control signal included in the input processing target signal, the content of the control signal corresponding to the control signal name included in the control information is processed. 28. The signal processing method according to claim 27, wherein derivation information for deriving from a signal is used. 29. The signal processing method according to claim 27, wherein the input processing target signal is a video signal. 30. A video signal of any one of a plurality of types of video signals respectively corresponding to a plurality of types of broadcasting systems is input, then a broadcasting system of the input video signal is detected, and then the plurality of types The control information corresponding to the detected broadcast system is output from the plurality of control information stored in advance corresponding to each of the broadcast systems, and then shared by the processing of a plurality of video signals of different broadcast systems. 30. The signal processing method according to claim 29, wherein the input video signal is processed based on the output control information by using a signal processing unit for performing the processing. 31. The signal processing method according to claim 29, wherein the control signal included in the video signal is a sampling phase signal. 32. The signal processing method according to claim 30, wherein the plurality of types of broadcasting systems respectively corresponding to the plurality of types of video signals include an NTSC system and a MUSE system.