JPH08163120A - Ciphering circuit - Google Patents

Abstract

PURPOSE: To provide a ciphering circuit of a comparatively small scale which can secure the secrecy of data and also can be applied to the high-speed transmission of data. CONSTITUTION: The register files 10 and 20 are selectively switched for the writing/reading purposes for every ciphering frame (e) based on the control signals (b), (c), (g) and (h). The input data (a) are written in the prescribed addresses of both files 10 and 20 selected by the signals (b) and (c) in the order of input. A pulse generator 30 generates the read addresses (i) based on a ciphering key (f) and reads the data out of the addresses designated by each address (i) of both files 10 and 20 selected by the signals (g) and (h) in the order different from the input order. Then the generator 30 transmits these read data as the ciphering data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encryption circuit, and more particularly to an encryption circuit which is used in a digital data communication device and sequentially encrypts data to be transmitted based on a predetermined encryption key.

[0002]

2. Description of the Related Art Generally, in digital data communication, an encryption circuit is provided in a digital data communication device for the purpose of maintaining confidentiality of information on a transmission line, and data to be transmitted is encrypted based on a predetermined encryption key. After that, it is sent to the transmission line. Conventionally, this type of encryption circuit has a hardware configuration of a complicated random number generation algorithm or generator polynomial (for example, Japanese Patent Laid-Open No. 63-98090).

This is encrypted by inputting the encryption data and the encryption key, generating the encrypted data with this encryption key, and taking the exclusive OR with the input data (plaintext). The data (encrypted text) is generated. In particular, as a random number generation algorithm when creating encrypted data, DE that is a block synthesis cipher is used.
S (Data Encryption Standard) is used, the encryption data is divided into blocks of 64 bits, and the 64-bit key is used to repeat the process of enlarging transposition, reduction transposition, and simple transposition to obtain 64-bit encrypted data. Was to be generated.

As an encryption method for high-speed transmission, there has been proposed a method in which data to be encrypted (plain text) is serially / parallel-converted to be divided in parallel and processed (for example, Japanese Patent Laid-Open No. 3-273725). Issue Bulletin). This is for serializing data (plaintext) to be encrypted.
It is divided into two by parallel conversion, and each divided data is provided with a circuit for encryption consisting of a complicated algorithm or a generator polynomial, and the encrypted data generated by the circuit and the divided into two. The exclusive OR with the data is taken, and the output is subjected to parallel / serial conversion to generate encrypted data.

[0005]

Therefore, according to the former, such a conventional encryption circuit uses a complicated algorithm such as DES and realizes it by hardware. There was a problem that the scale would be huge. According to the latter, when the data to be transmitted is divided into a large number according to the transmission speed, it is necessary to provide a circuit for encryption for each divided data, and the circuit scale is enormous as in the former case. There was a problem that The present invention is intended to solve such a problem, and an object of the present invention is to provide an encryption circuit which is relatively small in scale, has data confidentiality, and can be used for high-speed transmission.

[0006]

In order to achieve such an object, the encryption circuit according to the present invention includes first and second storages for temporarily storing a plurality of input data constituting an encrypted frame. Means and a control means for selecting one of the first and second storage means as a write storage means and the other as a read storage means, and alternately switching and selecting each encrypted frame. By this control means, each input data forming the encrypted frame is written in a predetermined address of the write storage means in the input order, and the data stored in the read storage means is input in the input order based on the encryption key. Is read in a different order. Further, the control means reads out the data stored in the reading storage means in a different order for each encrypted frame, based on the encryption key indicating a different order for each encrypted frame.

[0007]

Therefore, the control means writes each input data forming the encrypted frame in a predetermined address of the writing storage means in the order of input, and the data stored in the reading storage means is the encryption key. The reading order is different from the input order. Further, by the control means, based on the encryption key indicating a different order for each encrypted frame,
The data stored in the read storage means is read in a different order for each encrypted frame.

[0008]

Next, the present invention will be described with reference to the drawings. 1 is a block diagram of an encryption circuit according to an embodiment of the present invention. In FIG. 1, 10 and 20 are N bits for temporarily storing input data a having an N bit parallel configuration.
A register file (first and second storage means) 30 having an M word structure reads input data from the register files 10 and 20 in a predetermined order based on the encrypted frame e and the encrypted key f, and the encrypted data j. Is a pulse generator (control means) for outputting as.

B, c, d, g, h, and i are generated in the pulse generator 30 based on the encrypted frame e and the encrypted key f, and are output to the register files 10 and 20. It is a signal. b and c are control signals for individually controlling the write operation for each register file 10 and 20, and g and h are control signals for individually controlling the read operation for each register file 10, 20. Also,
d is a write address commonly output to each register file 10 and 20, and i is a read address commonly output to each register 10 and 20.

Next, referring to FIG. 2, the write operation of the operation of the present invention will be described. FIG. 2 is a timing chart showing the write operation to the register files 10 and 20. The encrypted frame e is a signal indicating a frame which is a unit of encryption. Within this one frame,
Input data a of 4 (M = 4) words is stored.
Each input data a is sequentially supplied commonly to the register files 10 and 20 as N-bit parallel data.
Further, the encryption key f is input to the pulse generator 30 corresponding to each input data a.

The pulse generator 30 generates a write address d for writing each input data a based on the encrypted frame e, and sequentially outputs the write address d to the register files 10 and 20. In this case, since one frame has a 4-word structure, the write address d is a 2-bit (L = 2) binary signal that advances in increments of each input data a. Further, the pulse generator 30 outputs control signals b and c for selecting the write register file in which the input data a is written based on the encrypted frame e. The control signals b and c are signals that are inverted for each frame, and the register files 10 and 20 written for each frame are switched by this.

At time T1, the control signal b becomes the "L" level and the control signal c becomes the "H" level, and the register file 10 is selected for writing. As a result, each input data a is written in the order of being input to the addresses 0, 1, 2, 3 designated by the write address d in the register file 10. Then, at time T2,
The control signals b and c are inverted, the register file 20 is selected for writing, and each input data a is input to the addresses 0, 1, 2, 3 designated by the write address d in the register file 20. The register files 10 and 20 are written for each frame thereafter.
Are switched and the input data a are written alternately.

Next, the read operation of the operations of the present invention will be described with reference to FIG. FIG. 3 is a timing chart showing a read operation for the register files 10 and 20. In parallel with the above-mentioned write operation, the data stored in the register files 10 and 20 are read out in a predetermined order based on the encryption key f and output as encrypted data.

First, times T1 and T2 in FIG. 3 indicate the same times as the times in FIG. 2, and at time T1, the control signal g is at "H" level and the control signal h is at "L".
The level becomes the level, and the register file 20 is selected as the read register file. In particular, the control signals g and h are
Since the phase is opposite to that of the control signals b and c, when one of the file registers 10 and 20 is in the writing operation in each frame, the other file register 20 and
10 is a read operation.

As a result, in the frame starting from time T1, the input data a is written in the register file 10 and the stored data is read from the register file 20. Here, the pulse generator 30
Generates a read address i based on the encryption key f. In this case, the encryption key f is repeatedly input in the order of 3,2,1,0 in synchronization with each input data a, and the read address i is 3,2,1,0 different from the write order. Output in order.

Therefore, the input data a is sent in the encrypted frame with the order changed based on the encryption key f, and the input data can be encrypted with a relatively simple circuit configuration. It will be possible. In the above description, the control signals b, c, g, and h have been described as independent signals, but the control signals b and h, and c and g have the same phase, so they are regarded as the same signal. Good.

Next, as another embodiment of the read operation of the present invention, a case where the encryption key is changed for each frame will be described with reference to FIG. In FIG. 4, the same parts as those described above (FIG. 3) are designated by the same reference numerals. In this case, the encryption key f changes for each frame and is input to the pulse generator 30 in synchronization with each input data a. At time T1, the control signal g becomes “H” level, the control signal h becomes “L” level,
The register file 20 is selected as the read register file.

In this case, since the control signals g and h have opposite phases to the control signals b and c, when one of the file registers 10 and 20 is in the writing operation in each frame, The file registers 20 and 10 are read. As a result, in the frame starting from time T1, the input data a is written in the register file 10 and the stored data is read from the register file 20.

The pulse generator 30 generates the write address i based on the encryption key f. In this case, the encryption key f
Is input in synchronization with each input data a, so that the encryption key f input in synchronization with the input data a can be read in the next frame based on the encryption key f after the writing is completed. Hold. That is, in the frame starting from time T1, the encryption key f is input to the pulse generator 30 in the order of 0, 1, 3, 2 and held as the encryption key f ′.

At time T2, the control signals g and h are inverted, the input data a is written into the register file 20, and the stored data is read from the register file 10. At this time, the pulse generator 30
Outputs the read address i based on the stored encryption key f ′ and reads the stored data from the register file 10 in the order of addresses 0, 1, 3, 2.

At the same time, the pulse generator 30 holds a new encryption key f input in synchronization with the input data a. Therefore, the input data a is sent in the encrypted frame with the order changed based on the encryption key f which is different for each frame. Especially, when the number of words M constituting one frame is M = 4, The replacement order is 4! (= 24), and if M = 32, 32! (= 2.6 × 10 ³⁵ ), and it becomes possible to generate encrypted data with a high degree of confidentiality by inputting the encryption key that changes for each frame.

[0022]

As described above, according to the present invention, first and second storage means for temporarily storing a plurality of input data forming an encrypted frame, and the first and second storage means are provided.
Control means for selecting one of them as a writing storage means and the other as a reading storage means, and switching and selecting alternately for each encrypted frame. Each of the input data constituting the above is written in a predetermined address of the writing storage means in the input order, and the data stored in the reading storage means is read out in an order different from the input order based on the encryption key. Therefore, the output order is different from the input order of the input data, it is possible to generate encrypted data with confidentiality without using a complicated algorithm in a relatively small circuit, The operating time is shortened and it can be used for high speed transmission. In addition, the control unit reads the data stored in the read storage unit in a different order for each encrypted frame based on the encryption key indicating a different order for each encrypted frame. The order of reading increases with an increase in the number of data forming the frame, and encrypted data having higher confidentiality can be generated.

[Brief description of drawings]

FIG. 1 is a block diagram of an encryption circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing a write operation of the present invention.

FIG. 3 is a timing chart showing a read operation of the present invention.

FIG. 4 is a timing chart showing another read operation of the present invention.

[Explanation of symbols]

10 ... Register file (first storage means), 20 ... Register file (second storage means), 30 ... Pulse generator (control means), a ... Input signal, b, c, g, h ... Control signal, d ... write address, i ... read address, e ...
Encryption frame, f ... Encryption key.

Claims (2)

[Claims] 1. An encryption circuit for encrypting input data based on a predetermined encryption key and outputting the encrypted data, wherein first and second storage means for temporarily storing a plurality of input data forming an encrypted frame. And a control means for selecting one of the first and second storage means as a writing storage means and the other as a reading storage means for alternately switching and selecting for each encrypted frame, By this control means, each input data forming the encrypted frame is written in a predetermined address of the write storage means in the order of input, and the data stored in the read storage means is input based on the encryption key. An encryption circuit characterized in that reading is performed in an order different from the order. 2. The encryption circuit according to claim 1, wherein the control unit controls the data stored in the read storage unit for each encrypted frame based on an encryption key indicating a different order for each encrypted frame. An encryption circuit characterized in that the reading is performed in different order.