JPH08163066A - Tdma processing circuit - Google Patents

Abstract

PURPOSE: To discriminate the certainty of a reception signal without the use of a synchronization detection circuit for substantial signal reception processing by providing one system of synchronization detection circuit to discriminate the certainty of the reception signal. CONSTITUTION: A 2nd synchronization detection circuit 15 independently of a 1st synchronization detection circuit 13 for substantial signal reception processing is connected in parallel with the 1st synchronization detection circuit 13. Through the constitution above, a synthesizer section 12 gives a prescribed signal to a reception section 11 through a setting from a CPU circuit 14 and the reception section 11 is controlled based on the signal. In the case of fine-tuning the synthesizer section 12, a synchronization word included regularly in a reception demodulation signal outputted from the reception section 11 is detected, but the 1st synchronization detection circuit 13 connecting to a signal reception processing circuit is not in use by the independent 2nd synchronization detection circuit 15 is validated and the synchronization detection pulse outputted from the 2nd synchronization detection circuit 15 is counted by a counter circuit 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplex communication system (hereinafter referred to as TDMA) used in a digital mobile phone terminal or the like.
That is) processing circuit.

[0002]

2. Description of the Related Art Conventionally, TDMA has been widely used in digital mobile phone terminals and the like. FIG. 3 shows a configuration block diagram of such a conventional TDMA processing circuit.

In FIG. 3, a receiving section 1 receives a radio wave from a base station (not shown) and demodulates it. And
The synchronization detection circuit 3 detects the synchronization word in this demodulated signal and establishes synchronization. The synthesizer unit 2 is the same as the receiving unit 1 described above.
Adjust the frequency of. Further, the CPU circuit 4 inputs the signal from the synchronization detection circuit 3 and controls the synthesizer unit 2.

First, the CPU circuit 4 includes the synthesizer section 2
Is controlled to set a predetermined frequency so that the receiving unit 1 receives a desired radio wave. That is, the synthesizer unit 2
Outputs a predetermined signal to the receiving unit 1 based on an instruction from the CPU circuit 4. As a result, the receiver 1 receives the desired radio wave from the mobile phone base station.

By the way, when the reference frequency inside the synthesizer section 2 is different from the reference frequency of the base station, C
The frequency of the synthesizer unit 2 is finely adjusted and set under the control of the PU circuit 4. At this time, in order to determine whether or not the adjustment is performed in the correct direction, a method of detecting a synchronization word regularly included in the reception demodulated signal output from the receiving unit 1 is also used. The synchronization word is detected by using the synchronization detection circuit 3 used for the original TDMA processing.

Since the synchronization detecting circuit 3 is used for the original TDMA processing, not only the detection of the synchronization word but also the signal receiving processing is activated. As a result, control in the CPU circuit 4 becomes unnecessarily complicated. Here, the signal receiving process means a process of decoding a received signal linked with a sync word detecting operation. That is, in the conventional hardware configuration, the synchronization detection circuit 3 and the reception signal decoding circuit connected thereto are
Since there is only a system, an unnecessary received signal decoding circuit is activated although it is originally necessary to detect only the presence or absence of the detection of the synchronization word. Furthermore, there is a risk of synchronizing with the wrong sync word due to an error on the signal transmission path.

[0007]

Since the conventional TDMA processing circuit is configured as described above, the synchronization detection circuit 3 must be used to determine only the presence or absence of a synchronization word, and the original signal is required. It could not be processed separately from the receiving operation.

This is because if the received signal is correct, signal reception (decoding) processing is carried out after detection of the sync word. However, sync word detection is used as auxiliary information in the step of adjusting the reference frequency of the synthesizer. This is because, when used, it is desirable to perform processing separately from the original signal reception processing (though it may be the same as a result). Functionally similar processing is possible with conventional hardware, but unnecessary processing is also started, which complicates processing and also increases current consumption.

Further, there is a problem that there is a danger that the wrong sync word is out of sync.

The present invention has been made in view of the above problems, and an object thereof is to obtain a circuit capable of determining the certainty of a received signal without using a synchronization detection circuit used in the original signal reception processing. is there.

[0011]

In order to solve the above problems, the present invention provides a second synchronization detection circuit separate from the original synchronization detection circuit for signal reception. The original synchronization detection circuit is referred to as a first synchronization detection circuit here. Then, the signals from the receiver are connected in parallel in both the first and second synchronization detection circuits, and the output signal of the second synchronization detection circuit is supplied to the counter circuit. The counter value of this counter circuit can be read from the CPU circuit.

That is, in order to solve the above-mentioned problems, the first aspect of the present invention receives a radio wave signal from a base station and demodulates it, a synthesizer section for controlling the reception section, and the reception section. A first synchronization detection circuit that receives a demodulation signal that is output from a receiver and that detects a synchronization word; a second synchronization detection circuit that receives the demodulation signal that is output from the receiver and that detects a synchronization word; A counter circuit connected to the second synchronization circuit; and a CPU circuit that receives information from the counter circuit and performs control to correct the deviation between the base station transmission frequency and the reception frequency, the first synchronization detection circuit The TDMA processing circuit is characterized in that only the output signal of is used for the original signal reception processing.

In order to solve the above-mentioned problems, a second aspect of the present invention includes a receiving section for receiving and demodulating a radio wave signal from a base station, a synthesizer section for controlling the receiving section, and the receiving section. A first synchronization detection circuit that inputs a demodulation signal that is output and detects a synchronization word, a second synchronization detection circuit that inputs a demodulation signal that is output from the reception unit and detects a synchronization word, and the second synchronization A synchronization word detection pulse output from the detection circuit is input, and a CPU circuit that performs control to correct the deviation between the base station transmission frequency and the reception frequency is provided, and only the output signal of the first synchronization detection circuit is originally provided. It is a TDMA processing circuit characterized by being used for the signal reception processing of.

In order to solve the above-mentioned problems, a third aspect of the present invention includes a receiving section for receiving and demodulating a radio wave signal from a base station, a synthesizer section for controlling the receiving section, and the receiving section. A first synchronization detection circuit that inputs a demodulation signal that is output and detects a synchronization word, a second synchronization detection circuit that inputs a demodulation signal that is output from the reception unit and detects a synchronization word, and the second synchronization A first synchronization detection circuit, comprising: a counter circuit connected to the circuit; and a CPU circuit for inputting information from the counter circuit and performing control for monitoring information of neighboring peripheral base stations during communication. The TDMA processing circuit is characterized in that only the output signal of is used for the original signal reception processing.

[0015]

The second synchronization detection circuit of the first invention is
It operates independently of the first synchronization detection circuit for signal reception, detects the synchronization word in the signal, and outputs a detection pulse. In addition, by counting this pulse with the counter circuit, the number of times the synchronization word is detected per unit time is CP.
It can be easily known from the U circuit.

The CPU circuit in the second aspect of the present invention can directly observe the detection pulse which is the output signal of the second synchronization detection circuit and directly know the number of detections of the synchronization word, without using the counter circuit. .

The CPU circuit according to the third aspect of the present invention uses the second synchronization detection circuit to easily detect the number of synchronization words per unit time even when monitoring the information of the neighboring base stations during communication. It is possible to know.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

Example 1. FIG. 1 shows the TDM of the first embodiment.
A block diagram of the A circuit is shown. Conventional TDM
Similar to the circuit A, the synthesizer unit 12 first outputs a predetermined signal to the receiving unit 11 according to the setting from the CPU circuit 14. The receiving unit 11 is controlled based on a predetermined signal from the synthesizer unit 12.

When finely adjusting the synthesizer section 12, the sync word regularly included in the received demodulated signal output from the receiving section 11 is detected, but the first sync detecting circuit 13 connected to the signal receiving processing circuit is The independent second synchronization detection circuit 15 is enabled without being used, and the synchronization detection pulse output from the second synchronization detection circuit 15 is counted by the counter circuit 16
To count.

As described above, the characteristic feature of the first embodiment is that the second synchronization detection circuit 15 independent of the first synchronization detection circuit 13 used for the original signal reception processing is
That is, it is connected in parallel with the first synchronization detection circuit 13. That is, similarly to the first synchronization detection circuit 13, the reception demodulation signal from the reception unit 11 is also supplied to the second synchronization detection circuit 15. With this configuration, according to the first embodiment, the second synchronization detection circuit 15 is operated independently of the first synchronization detection circuit 13, so that the synchronization word is activated without activating the original signal processing. Can be detected.

In other words, the first synchronization detection circuit 13 in the first embodiment is a correlator to which a conventional reception signal decoding circuit is connected. Then, after the timing management circuit detects the sync word, it starts using the sync word as a reference. On the other hand, the second synchronization detection circuit 15 is a correlator that operates independently of the timing management circuit. These two sync detection circuits perform the same operation in terms of "detecting a sync word", but differ in whether or not there is a circuit attached to the circuit.

Further, in the first embodiment, as shown in FIG. 1, a counter circuit 16 for counting the output signal of the second synchronization detection circuit 15 is provided. By reading the count value of the counter circuit 16 by the CPU circuit 14, it is possible to easily know the number of synchronization word detections per unit time. Then, when the number of times is equal to or larger than the predetermined specified value, it is determined that the correct signal is received.

If the first synchronization detection circuit 13 synchronizes with an erroneous synchronization word, the timing management circuit also malfunctions at that timing. That is, both the conventional circuit and the circuit of this embodiment. Is also the same. However, in the circuit of this embodiment, the second synchronization detection circuit 15 is provided, and first, with the operation of the first synchronization detection circuit 13 prohibited, only the presence or absence of a synchronization word per unit time is detected by the second synchronization detection circuit 15. And the counter circuit 16 for detection. Then, by operating the first synchronization detection circuit 13 after the reference frequency of the synthesizer unit 12 is correctly adjusted, it is possible to reduce the risk of malfunctioning with respect to a strange received wave.

With the above configuration, it is possible to judge the certainty of the received signal without affecting the operation of the first synchronization detection circuit 13. In other words, it is possible to reduce the current consumption by preparing two systems of the synchronization detection circuit, activating one of the systems at the initial check of the terminal to simplify the processing, and stopping the operation of the unnecessary portion.

Example 2. In the first embodiment, the number of times the sync word is detected is counted by using the counter circuit 16. In other words, it was counting by hardware. However, this counting may be done by software. For example, it is also preferable that the synchronization detection pulse which is the output signal of the synchronization detection circuit 15 is directly input to the CPU circuit 14 and the CPU circuit 14 counts the pulse by software.

FIG. 2 is a block diagram showing the configuration when the counter circuit 16 in the first embodiment is omitted as described above. As shown in FIG. 2, the counter circuit 16 is omitted and the sync detection pulse is the second sync detection circuit 1.
5 is directly supplied to the CPU circuit 14.

If such a configuration is adopted when the CPU circuit 14 has sufficient capacity, the amount of hardware can be reduced.

Example 3. In the above embodiment,
The case where the present invention is used for the frequency correction method for correcting the deviation between the base station transmission frequency and the terminal reception frequency is shown, but the reception signal determination for determining the probability of the frequency of a peripheral base station other than the own station during communication is shown. The same effect as in the above embodiment can be obtained.

[0030]

As described above, according to the present invention, a synchronization detection circuit for determining the certainty of a received signal is provided.
Since the system is provided as an extra system, there is an effect that it is possible to make a highly accurate determination without affecting the signal receiving circuit.

Further, if the CPU circuit directly counts the sync word detection pulses without using the counter circuit, there is an effect that a TDMA circuit with a reduced amount of hardware can be obtained.

Further, even when the frequencies of the peripheral base stations other than the own station are monitored during communication, even when the above-mentioned configuration of the present invention is adopted, similarly, the signal receiving circuit is not affected and the accuracy is improved. It has the effect of making a high judgment.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a TDMA processing circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration block diagram of a TDMA processing circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration block diagram of a conventional TDMA processing circuit.

[Explanation of symbols]

11 receiver section, 12 synthesizer section, 13 1st synchronization detection circuit, 14 CPU circuit, 15 2nd synchronization detection circuit, 16 counter circuit.

Claims (3)

[Claims] 1. A receiving unit for receiving and demodulating a radio wave signal from a base station, a synthesizer unit for controlling the receiving unit, and a demodulated signal output from the receiving unit as input and detecting a synchronization word. A first synchronization detection circuit, a second synchronization detection circuit that receives a demodulated signal output from the reception unit, and detects a synchronization word; a counter circuit connected to the second synchronization circuit; Of the base station, which controls the correction of the deviation between the base station transmission frequency and the reception frequency.
A TDMA processing circuit, comprising: a circuit, wherein only the output signal of the first synchronization detection circuit is used for original signal reception processing. 2. A receiving section for receiving and demodulating a radio wave signal from a base station, a synthesizer section for controlling the receiving section, and a demodulated signal output from the receiving section as input and detecting a sync word. A first synchronization detection circuit, a demodulation signal output from the receiving unit, a second synchronization detection circuit that detects a synchronization word, and a synchronization word detection pulse output from the second synchronization detection circuit. And a CPU circuit for controlling the deviation between the base station transmission frequency and the reception frequency, wherein only the output signal of the first synchronization detection circuit is used for the original signal reception processing. Processing circuit. 3. A receiving section for receiving and demodulating a radio wave signal from a base station, a synthesizer section for controlling the receiving section, and a demodulated signal output from the receiving section as input and detecting a sync word. A first synchronization detection circuit, a second synchronization detection circuit that receives a demodulated signal output from the reception unit, and detects a synchronization word; a counter circuit connected to the second synchronization circuit; CP for inputting the information of the above and monitoring the information of the adjacent base stations during communication.
And a U circuit, wherein only the output signal of the first synchronization detection circuit is used for the original signal reception processing.