JPH08162931A - Switching device - Google Patents

Abstract

PURPOSE: To prevent the flash-on phenomenon of a transistor at the time of supplying power by simple constitution and to shorten off delay time as well. CONSTITUTION: This device is provided with an output circuit 1 provided with a FET 145 for switching whose drain and source are serially connected to a current path from a power source VD to an output detection part (lead) L, a resistor 147 connected between the gate and the source and a photo voltaic coupler 49 for supplying a driving voltage between the gate and the source of the FET 145 corresponding to the output of an internal circuit 151. A differentiation circuit composed of a capacitor 7 and the resistors 5 and 9 is provided between the drain and the source of the FET 145 and the transistor 3 whose collector and emitter are connected between the gate and the source of the FET 145 is driven by the charging current of the capacitor 7. As a result, when the rise of a voltage occurs between the drain and the source of the FET 145, the transistor 3 is turned on and the FET 145 is forcedly turned off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching device which switches a current path from a power source to a load by a transistor to switch between energization and de-energization of the load.

[0002]

2. Description of the Related Art Conventionally, this type of switching device has been used as an output circuit for outputting a control signal to a controlled device side in a programmable controller, for example, and a switching device as shown in FIG. 5 is known. ing.
Each output circuit illustrated in FIG. 5 is a case where an FET is used as an output transistor.

First, the output circuit 101 shown in FIG.
Is a so-called source output type, which is connected to the controlled device 103 including the power supply VD and the output detection unit L as a load connected to the negative side of the power supply VD. The output circuit 101 is connected to the plus side of the power supply VD, the opposite side of the output detection unit L from the power supply VD, and the minus side of the power supply VD via three terminals P, O, and M. And the power supply V
The FET 105 of the P channel, the source of which is connected to the positive side (terminal P) of D and the drain of which is connected to the side (terminal O) opposite to the power source VD of the output detection unit L, and FET1.
A resistor 10 connected between the source and the gate of 05 to pull up the gate of the FET 105 to the positive side of the power supply VD.
7, a photocoupler 109 having a collector connected to the gate of the FET 105 and an emitter connected to the negative side (terminal M) of the power supply VD, and a photocoupler 109 including an LED 109b for driving the phototransistor 109a by light emission; 109 LE
And an internal circuit 111 including a microcomputer or the like for causing the D109b to emit light according to a control result.

The source output type output circuit 10
In No. 1, when the internal circuit 111 causes the LED 109b of the photocoupler 109 to emit light, a current from the power supply VD flows through the phototransistor 109a of the photocoupler 109 via the resistor 107, which causes a potential difference between the gate and the source of the FET 105. Occurs and the FET 105 is turned on. Then, a current flows from the power supply VD to the output detection unit L via the source and drain of the FET 105, and on the controlled device 103 side, it is detected that a current has flowed to the output detection unit L, and the control result of the internal circuit 111 is detected. To detect.

Next, the output circuit 121 shown in FIG.
Is a so-called sink output type that is connected to the controlled device 123 including the power supply VD and the output detection unit L connected to the positive side of the power supply VD. This output circuit 121 also has three terminals P, O, on the positive side of the power supply VD, on the side opposite to the power supply VD of the output detection unit L, and on the negative side of the power supply VD.
Connected via M. An N-channel FET 125 having a source connected to the negative side (terminal M) of the power supply VD and a drain connected to the opposite side (terminal O) to the power supply VD of the output detection unit L, and the gate and source of the FET 125. It is connected between and the gate of FET125 is the power source V
A resistor 127 that pulls down to the minus side of D, a phototransistor 129a and a phototransistor 129a whose collector is connected to the plus side (terminal P) of the power supply VD and whose emitter is connected to the gate of the FET 125.
Is provided with a photocoupler 129 including an LED 129b for driving the LED by light emission, and an internal circuit 131 for causing the LED 129b of the photocoupler 129 to emit light according to a control result.

Then, the output circuit 12 of the sync output type
In No. 1, when the internal circuit 131 causes the LED 129b of the photocoupler 129 to emit light, a current from the power supply VD flows to the resistor 127 via the phototransistor 129a of the photocoupler 129, which causes a potential difference between the gate and the source of the FET 125. Occurs and the FET 125 is turned on. Then, the FET 12 is connected from the power source VD to the output detection unit L.
A current flows through the drain and source of No. 5, and on the controlled device 123 side, it is detected that a current has flowed to the output detection unit L, and the control result of the internal circuit 131 is detected.

That is, the source output type output circuit 101.
Is configured to switch the current path from the power supply VD to the output detection unit L on the plus side (high side) of the output detection unit L, and the sink output type output circuit 121 is connected from the power supply VD to the output detection unit L. The current path to the switch is switched on the negative side (low side) of the output detection unit L.

On the other hand, the output circuit 141 shown in FIG.
Is called an independent output type and can be used in any of the above-mentioned source output type and sink output type output formats. 5C shows the case where the output detection unit L is provided on the minus side of the power supply VD on the controlled device 143 side, that is, the case where the source output type output format is adopted.

The output circuit 141 is connected to the plus side of the power supply VD and the opposite side of the output detection section L from the power supply VD via two terminals P and O. An N-channel FET 145 having a drain connected to the plus side (terminal P) of the power supply VD and a source connected to the opposite side (terminal O) to the power supply VD of the output detection unit L, and a gate and a source of the FET 145. The resistor 147 connected between and the FET1
Photodiode array 149a connected in the forward direction from the gate of 45 to the source and in parallel with resistor 147 and photodiode array 14 by light emission.
9a, a photovoltaic coupler 149 composed of an LED 149b for generating an electromotive force, and an LE of the photovoltaic coupler 149.
Internal circuit 15 for making D149b emit light according to the control result
1 and.

The independent output type output circuit 141
, The internal circuit 151 is connected to the photovol coupler 149.
When the LED 149b of the above is made to emit light, the photovoltaic coupler 1
A voltage is generated in the photodiode array 149a of 49, which causes a potential difference between the gate and the source of the FET 145, and the FET 145 is turned on. Then the power supply V
A current flows from D to the output detection unit L via the drain and source of the FET 145, and on the controlled device 143 side, it is detected that a current has flowed to the output detection unit L, and the internal circuit 151 is detected.
The control result of is detected.

Here, the output circuits 101 and 1 as described above.
21 and 141, when the controlled devices 103, 123, 143 are connected with the power supply VD turned on, or with the controlled devices 103, 123, 143 connected, the power supply V
When D is turned on, the FETs 105, 125, 145 are momentarily turned on and output erroneously, which causes the controlled devices 103, 123, 143 to malfunction.

This is a FET as an output transistor.
When a voltage that sharply rises is applied between the drain and the source of 105, 125, 145, as shown in FIG.
The junction capacitance Cgd between the gate and the drain is connected to the resistor 107,
The current If flows through 127 and 147, and the junction capacitance Cgd
FET105, 125, 145 until is charged
Potential difference occurs between the gate and source of the FETs 105, 1
This is because a so-called flash-on phenomenon occurs in which 25 and 145 turn on.

It should be noted that the photo voltaic coupler 1 used in the independent output type output circuit 141 as shown in FIG.
No. 49 has a very small driving capacity of about several tens of μA,
Resistor 1 provided between the gate and source of the FET 145
The resistance value of 47 must be set to several hundreds kΩ or more. Therefore, especially in this case, the FET1 needs a small current.
Since the voltage is generated between the gate and the source of the gate electrode 45 and the discharge time of the junction capacitance Cgs between the gate and the source is long, the flash-on phenomenon appears remarkably.

Therefore, as a structure capable of preventing such a flash-on phenomenon, there is a conventional structure disclosed in, for example, Japanese Patent Application Laid-Open No. 5-37322. This technique will be described by taking the sink output type shown in FIG. 5B as an example. For example, as shown in FIG. 6, in the output circuit 161 to which this technique is applied, the power supply V
The capacitor 163 is connected between the terminal P connected to the positive side of D and the source of the FET 125, and
A resistor 165 is provided on the path from the connection point between the source of 125 and the capacitor 163 to the terminal M connected to the negative side of the power supply VD, and further, in parallel with the resistor 165, the voltage between the terminals of the capacitor 163 is predetermined. Bypass circuit 167 for bypassing the resistor 165 when the value exceeds the value
Is provided.

Then, the output circuit 1 thus constructed
In 61, immediately after the controlled device 123 is connected or the power supply VD is turned on, the source of the FET 125 becomes the same potential as the plus side of the power supply VD by the uncharged capacitor 163. Then, after that, the capacitor 163 is charged via the resistor 165 with the lapse of time, and the voltage on the source side of the FET 125 gradually decreases. Then, after that, when the voltage between the terminals of the capacitor 163 becomes a predetermined value or more, the bypass circuit 167 is short-circuited, and the resistor 165 is excluded from the path connecting the source of the FET 125 and the negative side of the power supply VD. .

Therefore, when the power supply VD is applied to the output circuit 161, the voltage applied between the drain and source of the FET 125 is not steep but gradually increases, and the FET 125 is momentarily turned on. The flash-on phenomenon is prevented.

[0017]

However, the above-mentioned conventional output circuit 161 requires a bypass circuit 167 for bypassing the resistor 165 provided in the current path, and normally this bypass circuit 167 is a relay or It is composed of transistors.

If the bypass circuit 167 is composed of a relay, the size of the device will be increased by itself.
Further, even when the bypass circuit 167 is composed of a transistor, it is necessary to use, as the transistor, one having an energization capacity equal to or higher than that of the output transistor (FET 125 in the above example). When the resistance value of the portion L is small, the voltage of the power supply VD is large, or the like, and the energization current is large, the device also becomes large.

On the other hand, the above conventional output circuits 101 and 12
1, 141, 161 are FETs 105, 125, 14
There is also a problem that the time from when the switch 5 is turned on to when the switch 5 is turned off, that is, the off delay time is long. Here, the OFF delay time will be described with reference to FIG. 7 by taking the case of the independent output type shown in FIG. 5C as an example.

First, when the FET 145 is turned off from the on state, the internal circuit 151 stops the light emission of the LED 149b and stops the voltage generation in the photodiode array 149a. Then, as indicated by the two arrows in FIG. 7A, first, the gate-source junction capacitance Cgs and the gate-drain junction capacitance Cgd of the FET 145 are discharged via the resistor 147, and the FET 145 has a The gate-source voltage drops to a predetermined off voltage, and FET1
The drain-source voltage of 45 increases (that is, starts changing from the on state to the off state). However, at this time,
As the drain-source voltage rises, as shown by the arrow in FIG. 7B, a current flows through the gate-drain junction capacitance Cgd through the resistor 147, and the gate-source junction capacitance Cgs of Discharge is disturbed.

That is, in the off delay time, the junction capacitance Cgs and the junction capacitance Cgd of the FET 145 are discharged, and the FET 14 is turned off.
The time T1 until the gate-source voltage of 5 decreases to a predetermined off-voltage and the rising change of the drain-source voltage of the FET 145 charges the gate-drain junction capacitance Cgd and discharges the junction capacitance Cgs. Although it becomes the sum of the disturbed time T2, the above-mentioned conventional output circuit cannot shorten the off delay time, and as a result, a higher speed switching operation cannot be realized. Of.

The above problems are not limited to the case where the FET is used as the output transistor, but also the case where the bipolar transistor is used or the case where the IGBT having the characteristics of both the bipolar transistor and the FET is used. Exactly the same.

The present invention has been made in view of these problems, and it is a first object of the present invention to provide a switching device capable of preventing the flash-on phenomenon with a simple structure, and further, an off delay time. It is an object of the present invention to provide a switching device capable of shortening

[0024]

The present invention, which has been made to achieve the above object, provides a current path for supplying a current from a power source to a predetermined load, and a collector and an emitter or a drain. By supplying a current or a voltage to a transistor having two output terminals made of a source connected in series and a drive terminal made of a base or a gate of the transistor to cause the transistor to perform a switching operation, energization to the load and In a switching device including drive control means for controlling non-conduction, voltage application detection means for detecting whether or not a voltage from the power supply is applied between the two output terminals of the transistor via the load. And when the voltage application detecting means detects the application of the voltage, the transistor turns off the voltage of the drive terminal. Is a voltage control means for forcibly held for a predetermined time in pressure level, a switching device, characterized in that it provided with a spirit.

According to a second aspect of the present invention, in the switching device according to the first aspect, the drive control means receives the voltage from the power source and causes the transistor to perform a switching operation. The gist of a switching device is characterized in that the voltage application detection means detects the application of the voltage from the rise of the voltage supplied to the drive control means.

On the other hand, according to a third aspect of the present invention, in the switching device according to the first aspect, the voltage application detecting means changes the voltage from the rising of the voltage between the two output terminals of the transistor. The gist is a switching device characterized by detecting application.

The present invention according to claim 4 provides the switching device according to claim 2 or 3, wherein:
The voltage application detection means is a differentiating circuit formed by connecting a capacitor and a resistor in series, and the voltage control means is
A switching device characterized by being a second transistor that short-circuits a drive terminal of the transistor to an emitter or a source of the two output terminals when a charging current of the capacitor is a predetermined value or more. .

[0028]

In the switching device according to the first aspect of the present invention configured as described above, the collector and the emitter or the drain and the source of the transistor are provided in the current path for supplying the current from the power source to the predetermined load. Are connected in series, and the drive control means supplies a current or voltage to the drive terminal composed of the base or gate of the transistor to cause the transistor to perform a switching operation, thereby energizing the load and Control de-energization.

Then, the voltage application detecting means detects whether or not the voltage from the power source is applied between the two output terminals of the transistor through the load, and the voltage application detecting means detects the application of the voltage. Then, the voltage control means forcibly holds the voltage of the drive terminal of the transistor at the voltage level at which the transistor is turned off for a predetermined time.

That is, in the switching device according to the first aspect, unlike the conventional device illustrated in FIG. 6, the voltage change between the output terminals of the transistor is not moderated, but the drive terminal (base or gate) of the transistor is changed. The voltage itself is forcibly held at the voltage level for turning off so that the transistor does not turn on.

Therefore, according to the switching device of the first aspect, it is possible to prevent the flash-on phenomenon without providing any additional component in the current path connecting the output terminal of the transistor and the power supply and the load. Therefore, it is possible to improve the reliability without increasing the size of the device.

Next, in the switching device according to a second aspect, in the switching device according to the first aspect, the drive control means receives a voltage from a power source that supplies a current to the load and causes the transistor to perform a switching operation. The voltage application detection means detects that a voltage is applied between the two output terminals of the transistor from the rise of the voltage supplied to the drive control means.

That is, the switching device according to the second aspect is premised on the configuration as illustrated in FIGS. 5A and 5B, and detects that the voltage of the power supply itself has risen to detect the transistor. It is configured to detect that a voltage from the power supply is applied between the output terminals via the load.
5A and 5B, the resistor 107 and the photocoupler 109 and the resistor 127 and the photocoupler 129 correspond to the drive control means, respectively.

Even with such a configuration, when the power is turned on and a voltage that sharply rises is applied between the output terminals of the transistor, the voltage control means sets the voltage level at which the drive terminal of the transistor is turned off. Since it is held for a predetermined time, it is possible to prevent the occurrence of the flash-on phenomenon.

According to the switching device of the second aspect, the rising of the power supply is detected by the voltage application detecting means even when high frequency noise is applied to the power supply, and as a result, the voltage control means forces the transistor to operate. Will be turned off. Therefore, it is possible to prevent a problem in which a sharp voltage rise is applied between the output terminals of the transistor due to high-frequency noise on the power supply, which causes a flash-on phenomenon.

On the other hand, in the switching device according to a third aspect, in the switching device according to the first aspect, the voltage application detecting means detects the rising of the voltage between the two output terminals of the transistor from the output terminal of the transistor to the output terminal of the transistor. The voltage applied from the power supply is detected via the load.

According to the switching device of the third aspect, the flash-on phenomenon can be prevented even when a voltage that sharply rises is applied only between the output terminals of the transistor. That is, in the switching device according to the above-mentioned claim 2, since the rising of the power supply voltage is detected, when the rising of the voltage occurs only between the output terminals of the transistor in the state where the voltage of the power supply is stable. May cause the flash-on phenomenon. On the other hand, in the switching device according to the third aspect, the rise of the voltage between the output terminals of the transistor is directly detected. Therefore, when the power is turned on or high-frequency noise is generated, the output terminal of the transistor is output. The voltage control means can be operated with respect to the rise of any voltage applied in the meantime, and as a result, the flash-on phenomenon in all cases can be surely prevented.

Further, according to the switching device of the third aspect, the off delay time of the transistor can be shortened. That is, as described above, when the transistor starts to change from the ON state to the OFF state, the potential difference between the output terminals becomes large and the rising edge of the voltage occurs between the two terminals, which causes the flash ON time. This is due to the occurrence of the same phenomenon as.

Here, according to the switching device of the third aspect, as described above, the voltage control means can be operated for every rise of the voltage applied between the output terminals of the transistor. When the transistor starts changing from the on state to the off state and a rising change of the voltage occurs between the output terminals, this is detected by the voltage application detecting means, and the transistor is forcibly turned off by the operation of the voltage control means. That is, of the off delay times, the time T2 described in the section "Problems to be solved by the invention" is shortened, whereby the transistor can be turned off quickly.

According to the switching device of the third aspect, since the OFF delay time can be shortened in this way, the switching operation can be speeded up.
Moreover, since the time during which the transistor is linearly turned on (T2 described above) can be shortened, the switching loss of the transistor can be reduced.

Next, in the switching device according to the fourth aspect, in the switching device according to the second or third aspect, the voltage application detection means is a differentiation circuit formed by connecting a capacitor and a resistor in series. The voltage control means is constituted by a second transistor that short-circuits the drive terminal of the transistor to the emitter or the source of the two output terminals when the charging current of the capacitor is equal to or higher than a predetermined value.

That is, in the switching device according to claim 4, in the case of the switching device according to claim 2, between both ends of the power source, and in the case of the switching device according to claim 3, between the output terminals of the transistors. , A differentiating circuit consisting of a capacitor and a resistor is connected.

When a voltage rise occurs between both ends of the power source or between the output terminals of the transistor, the capacitor of the differentiating circuit is charged with a predetermined time constant determined between the resistor and the capacitor. In switching devices,
When the charging current of the capacitor is more than a predetermined value, the second
With this transistor, the drive terminal of the output transistor is short-circuited to the emitter or collector, whereby the output transistor is forcibly turned off.

As described above, according to the switching device of the fourth aspect, the rise of the voltage can be detected and the output transistor can be forcibly turned off with a simple structure.

[0045]

Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 is a circuit diagram showing an output circuit 1 of the programmable controller according to the first embodiment.
The output circuit 1 is obtained by applying the present invention to the conventional output circuit 141 of the independent output type shown in FIG. 5C. In FIG. 1, the same members as those in FIG. The same reference numerals are attached. Since the basic configuration and operation of the output circuit 1 are the same as those of the output circuit 141 shown in FIG. 5C, detailed description thereof will be omitted, and the following description will focus on the differences in configuration and operation. To do.

As shown in FIG. 1, the output circuit 1 of the first embodiment is different from the output circuit 141 shown in FIG. 5C in that the collector of the FET 145 is connected to the gate of the FET 145 and the source of the FET 145 is connected. The emitter is connected to the second
NPN-type transistor (hereinafter,
3), a resistor 5 having one end connected to the base of the transistor 3, one end connected to the opposite side of the resistor 5 from the transistor 3 and the other end FE
A capacitor 7 connected to the drain of T145 and a resistor 9 connected between the base and emitter of the transistor 3.
And, are added and equipped.

In the output circuit 1 of the first embodiment, the photovol coupler 149 and the resistor 147 correspond to the drive control means, and the differentiation circuit including the capacitor 7 and the resistors 5 and 9 applies the voltage. It corresponds to the detection means, and the transistor 3 corresponds to the voltage control means.

Then, the output circuit 1 thus constructed
Then, when the controlled device 143 is connected with the power supply VD turned on, or when the power supply VD is turned on with the controlled device 143 connected, a steeply rising voltage is applied between the drain and source of the FET 145. .

Then, as shown in FIG. 5C, a charging current in the gate direction flows from the drain to the junction capacitance Cgd between the gate and the drain. In the output circuit 1 of the present embodiment, however, At the same time, the capacitor 7 and the resistor 5,
The current I1 also flows through the differentiation circuit composed of 9 and this current I1
(That is, the charging current of the capacitor 7) becomes a part of the base current, and the transistor 3 is turned on.

Therefore, at this time, the current flowing through the gate-drain junction capacitance Cgd does not flow into the resistor 147, and the collector-emitter current I2 of the transistor 3 is reached.
As a result, it directly flows to the source side of the FET 145, which prevents a potential difference between the gate and the source of the FET 145.

Then, when the charging of the capacitor 7 progresses and the current I1 decreases below a predetermined value, the transistor 3 is turned off. At this time, the junction capacitance Cgd of the FET 145 has already been sufficiently charged and is no longer present. The current is not flowing. Thus, according to the output circuit 1 of this embodiment, the FET 1 is turned on when the power is turned on as described above.
The phenomenon in which 45 is momentarily turned on, that is, the flash-on phenomenon, can be prevented only by providing the transistor 3, the capacitor 7 and the resistors 5 and 9, and the additionally provided transistor 3 detects the output. It may have a small energizing ability regardless of the magnitude of the energizing current to be passed through the portion L.

Further, according to the output circuit 1 of the present embodiment, even when a steep rise of the voltage is applied between the drain and the source of the FET 145 due to high frequency noise, a similar operation can prevent a malfunction. Next, the operation when the output circuit 1 is normally operated and the FET 145 is turned off from the on state will be described.

First, when the internal circuit 151 stops the light emission of the LED 149b and stops the voltage generation in the photodiode array 149a, the gate-source junction capacitance Cgs and the gate-drain junction capacitance Cgd of the FET 145 are stopped.
And are discharged through the resistor 147 (see FIG. 7). Then, when the gate-source voltage of the FET 145 drops to a predetermined off voltage, the FET 145 starts changing from the on state to the off state, and a rising change of the voltage occurs between the drain and the source.

Then, also in this case, as described above, the charging current in the gate direction flows from the drain to the junction capacitance Cgd between the gate and the drain. However, in the output circuit 1 of the present embodiment, this occurs. At the same time, the current I1 also flows through the differentiation circuit including the capacitor 7 and the resistors 5 and 9, and the transistor 3 is turned on by the current I1.

Therefore, also in this case, the current flowing through the junction capacitance Cgd between the gate and drain does not flow through the resistor 147, but flows as the collector-emitter current I2 of the transistor 3 toward the source side of the FET 145, and FE
The charge stored in the gate-source junction capacitance Cgs of T145 is also rapidly discharged through the transistor 3, and the FET 145 is instantly turned off. Then, when the charging of the capacitor 7 progresses and the current I1 decreases below a predetermined value, the transistor 3 is turned off. At this time, the junction capacitance Cgd of the FET 145 is already sufficiently charged, and the junction capacitance of the FET 145 is already present. Cgs is fully discharged.

That is, according to the output circuit 1 of the first embodiment, the time T2 during which the junction capacitance Cgd between the gate and the drain is charged and the discharge of the junction capacitance Cgs is prevented when the FET 145 is turned off is shortened. As a result, the off delay time of the FET 145 is shortened.

As described above, according to the output circuit 1 of this embodiment, the flash-on phenomenon of the FET 145 can be prevented with a simple structure, and the off-delay time can be shortened. As a result, the switching operation of the FET 145 can be speeded up and
The time during which the 145 is linearly turned on (the above T
Since 2) can be shortened, the switching loss of the FET 145 can be reduced.

Next, FIG. 2 is a circuit diagram showing the output circuit 11 of the programmable controller of the second embodiment.
The output circuit 11 is obtained by applying the present invention to the conventional output circuit 101 of the source output type shown in FIG. 5A. In FIG. 2, the same members as those in FIG. The same reference numerals are attached. Since the basic configuration and operation of the output circuit 11 are the same as those of the output circuit 101 shown in FIG. 5A, detailed description thereof will be omitted.
The difference between the configuration and the operation will be mainly described below.

As shown in FIG. 2, the output circuit 11 of the second embodiment is different from the output circuit 101 shown in FIG.
Further, a PNP-type transistor (hereinafter simply referred to as transistor) 13 as a second transistor having a collector connected to the gate of the FET 105 and an emitter connected to the source of the FET 105, and the transistor 1
Resistor 15 having one end connected to the base of resistor 3 and resistor 1
5, a capacitor 17 having one end connected to the side opposite to the transistor 13 and the other end connected to the drain of the FET 105, and a resistor 19 connected between the base and the emitter of the transistor 13 are additionally provided. ing.

In the output circuit 11 of the second embodiment, the photo coupler 109 and the resistor 107 correspond to the drive control means, and the capacitor 17 and the resistors 15 and 19 are provided.
The differential circuit consisting of corresponds to the voltage application detection means,
The transistor 13 corresponds to the voltage control means.

Then, the output circuit 1 thus constructed
Even in No. 1, when the controlled device 103 is connected with the power supply VD turned on, or when the power supply VD is turned on with the controlled device 103 connected, a voltage that sharply rises is applied between the source and drain of the FET 105. It

Then, as shown in FIG. 5A, a charging current in the direction from the gate to the drain flows in the junction capacitance Cgd between the gate and the drain, which is the same in the output circuit 11 of the present embodiment. At the same time, the current I3 also flows through the differentiation circuit composed of the capacitor 17 and the resistors 15 and 19, and this current I3 (that is, the charging current of the capacitor 17) becomes a part of the base current to turn on the transistor 13.

Therefore, at this time, the current I4 between the emitter and collector of the transistor 13 flows to the junction capacitance Cgd between the gate and drain, not from the resistor 107, and a potential difference occurs between the gate and source of the FET 105. Is prevented. Then, when the charging of the capacitor 17 progresses and the current I3 decreases to a predetermined value or less, the transistor 13 is turned off.
The junction capacitance Cgd of 105 is sufficiently charged and no current flows anymore.

As described above, the output circuit 11 of the second embodiment.
Also, the flash-on phenomenon at the time of power-on can be prevented only by providing the transistor 13, the capacitor 17, and the resistors 15 and 19, and the transistor 13 has a large energizing current to be passed to the output detection unit L. Regardless of size, it may have a small energizing capacity.

Next, the operation when the output circuit 11 is normally operated and the FET 105 is turned off from the on state will be described. First, the internal circuit 111 is the LED 1
When the light emission of 09b is stopped and the driving of the phototransistor 109a is stopped, the gate-source junction capacitance Cgs and the gate-drain junction capacitance Cgd of the FET 105 are discharged via the resistor 107. And FET1
When the gate voltage of 05 rises and the gate-source voltage reaches a predetermined off-voltage, the FET 105 starts changing from the on-state to the off-state, and a rising change of the voltage occurs between the drain-source.

Then, also in this case, the charging current in the direction from the gate to the drain flows through the junction capacitance Cgd between the gate and the drain. In the output circuit 11 of this embodiment, at the same time, the capacitor 17 and Resistors 15,1
The current I3 also flows through the differentiation circuit composed of 9 and the current I3
This turns on the transistor 13.

Therefore, in this case as well, the current I4 between the emitter and collector of the transistor 13 flows to the junction capacitance Cgd between the gate and the drain, not from the resistor 107, and between the gate and the source of the FET 105. The charge stored in the junction capacitance Cgs is also transferred to the transistor 13
Therefore, the FET 145 is instantly turned off. Then, when the charging of the capacitor 17 progresses and the current I3 decreases to a predetermined value or less, the transistor 13 is turned off.
The junction capacitance Cgd of 105 is fully charged and the junction capacitance Cgs is sufficiently discharged. That is, the off delay time of the FET 105 is shortened also by the output circuit 11 of the second embodiment.

As described above, the output circuit 11 of the second embodiment.
Also, the flash-on phenomenon of the FET 105 can be prevented with a simple configuration, the off delay time can be shortened, and the switching operation can be speeded up and the switching loss can be reduced.

Next, FIG. 3 is a circuit diagram showing the output circuit 21 of the programmable controller of the third embodiment.
The output circuit 21 is obtained by applying the present invention to the conventional output circuit 121 of the sink output type shown in FIG. 5B. In FIG. 3, the same members as those in FIG. The same reference numerals are attached. Since the basic configuration and operation of the output circuit 21 are the same as those of the output circuit 121 shown in FIG. 5B, detailed description thereof will be omitted.
The difference between the configuration and the operation will be mainly described below.

As shown in FIG. 3, the output circuit 21 of the third embodiment is different from the output circuit 121 shown in FIG.
Further, an NPN-type transistor (hereinafter simply referred to as transistor) 23 as a second transistor having a collector connected to the gate of the FET 125 and an emitter connected to the source of the FET 125, and the transistor 2
Resistor 25, one end of which is connected to the base of resistor 3, and resistor 2
5, a capacitor 27 having one end connected to the side opposite to the transistor 23 and the other end connected to the drain of the FET 125, and a resistor 29 connected between the base and the emitter of the transistor 23 are additionally provided. ing.

In the output circuit 31 of the third embodiment, the photo coupler 129 and the resistor 127 correspond to the drive control means, and the capacitor 27 and the resistors 25 and 29 are used.
The differential circuit consisting of corresponds to the voltage application detection means,
The transistor 23 corresponds to the voltage control means.

Then, the output circuit 2 configured as described above
The operation of No. 1 is exactly the same as that of the output circuit 1 of the first embodiment except that the internal circuit 131 drives the FET 125 by the photocoupler 129 (and the resistor 127). The output circuit 21 of the third embodiment also has a simple structure in which the transistor 23, the capacitor 27, and the resistors 25 and 29 are provided.
In addition to preventing the flash-on phenomenon of 5,
The off delay time can also be shortened.

Here, the output circuits 1 and 1 of the above embodiments
1, 21 are provided with a differentiating circuit formed by connecting a capacitor and a resistor in series between the drains and sources of the FETs 145, 105, 125, and the transistors 3, 13, 23 are charged with a charging current flowing through the capacitors of the differentiating circuit. By turning on, the flash on phenomenon is prevented and the off delay time is shortened.

On the other hand, the output circuit 11 of the second embodiment.
Or the output circuit 21 of the third embodiment, the controlled device 10
When receiving the voltage from the power source VD provided at 3,123,
If the FETs 105 and 125 are to be switched, as shown in FIGS. 4A and 4B, it is detected that the voltage of the power supply VD has risen, and the transistor 1
You may make it turn on 3,23.

That is, the output circuit 31 shown in FIG.
With respect to the output circuit 11 of the second embodiment, the side of the capacitor 17 opposite to the resistor 15 is connected not to the drain of the FET 105 but to the terminal M side (negative side of the power supply VD). The output circuit 41 shown in FIG.
With respect to the output circuit 21 of the embodiment, the side of the capacitor 27 opposite to the resistor 25 is connected not to the drain of the FET 125 but to the terminal P side (plus side of the power supply VD).

Also in the output circuits 31 and 41 configured as shown in FIGS. 4A and 4B, when the power source VD is turned on, the differentiation circuit including the capacitor 17 and the resistors 15 and 19, and the capacitor 27. Since a current flows through the differentiating circuit including the resistors 25 and 29 for a predetermined time to turn on the transistors 13 and 23, the flash-on phenomenon of the FETs 105 and 125 can be prevented.

The output circuits 1, 11 and 2 of the above embodiments are
1, 31 and 41 are FETs for switching between energization and de-energization of the output detection unit L.
A bipolar transistor or an IGBT may be used instead of ET. In the output circuit of each of the above embodiments,
A differentiating circuit consisting of a capacitor and a resistor was used to detect changes in the rising edge of the voltage, which simplified the device configuration.For example, when there was a rising edge in the voltage, a pulse signal of a predetermined width was generated. The output one-shot circuit may be formed by a logic circuit, and the transistors 3, 13, 23 may be turned on by the pulse signal thereof.

Furthermore, in each of the above embodiments, the FET 10
Although the bipolar transistors 3, 13 and 23 are used to forcibly turn off the transistors 5, 125 and 145, FETs or IGBTs may be used instead of them. On the other hand, in each of the above embodiments, the switching device of the present invention is applied to the output circuit of the programmable controller.
The present invention can be applied to a drive circuit for switching and driving various loads such as a lamp and a solenoid.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an output circuit of a first embodiment.

FIG. 2 is a circuit diagram showing an output circuit of a second embodiment.

FIG. 3 is a circuit diagram showing an output circuit of a third embodiment.

FIG. 4 is a circuit diagram showing an output circuit of another embodiment.

FIG. 5 is an explanatory diagram illustrating a technique and a flash-on phenomenon which are the premise of the present invention.

FIG. 6 is an explanatory diagram illustrating a conventional device.

FIG. 7 is an explanatory diagram illustrating an off delay time of a transistor.

[Explanation of symbols]

1, 11, 21, 31, 41 ... Output circuit 3, 13,
23 ... Transistors 5, 9, 15, 19, 25, 29, 107, 127, 1
47 ... Resistors 7, 17, 27 ... Capacitors 103, 123, 14
3 ... Controlled device 105, 125, 145 ... FET 109, 129 ...
Photocoupler 111, 131, 151 ... Internal circuit 149 ... Photobol coupler L ... Output detection unit VD ... Power supply

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Dennis M Wright, Ohio, USA 44143-2195 Highland Heights Alpha Drive 747 Allen-Bradley Company

Claims (4)

[Claims] 1. A transistor in which two output terminals consisting of a collector and an emitter or a drain and a source are connected in series to a current path for supplying a current from a power source to a predetermined load, and a base or a gate of the transistor. Drive control means for controlling the energization and de-energization of the load by supplying a current or a voltage to the drive terminal to cause the transistor to perform a switching operation, and a switching device comprising: A voltage application detecting means for detecting whether or not a voltage from the power source is applied between the output terminals via the load; and a voltage at the drive terminal when the voltage application detecting means detects the application of the voltage. Voltage control means for forcibly holding the voltage at a voltage level at which the transistor is turned off for a predetermined time. The switching device according to. 2. The switching device according to claim 1, wherein the drive control means receives the voltage from the power supply and causes the transistor to perform a switching operation, and the voltage application detection means includes the drive control means. The application of the voltage is detected from the rise of the voltage supplied to the switching device. 3. The switching device according to claim 1, wherein the voltage application detection unit detects application of the voltage from a rise of a voltage between the two output terminals of the transistor. Switching device. 4. The switching device according to claim 2 or 3, wherein the voltage application detection means is a differentiation circuit formed by connecting a capacitor and a resistor in series, and the voltage control means is the differential circuit. The switching device is a second transistor that short-circuits the drive terminal of the transistor to the emitter or the source of the two output terminals when the charging current of the capacitor is equal to or more than a predetermined value.