JPH0816258A - Ac power controller - Google Patents

Abstract

PURPOSE:To detect both of a main circuit side open phase and a phase control mean side open phase in an AC power controller. CONSTITUTION:A signal coincidence detecting circuit 27 prepares a coincidence signal CS (AND signal) between 1st and 2nd synchronizing signals SRS, SST prepared by a synchronizing circuit 19 based upon the secondary side inter-line voltage of a three-phase transformer 15 connected to a three-phase AC power supply and an open phase judging circuit 28 detects an open phase on the side of a phase control means 21 based upon the duty ratio of the signal CS and outputs an open phase detecting signal to a phase control circuit 20 and a phase control means open phase display device 30. An open phase on the side of a main circuit 14 is detected by a main circuit open phase detecting circuit 25 and an output signal from the circuit 25 is similarly inputted to the circuit 20 and a main circuit open phase display device 31. At the time of inputting either one of the open phase detecting signals, the circuit 20 stops a gate signal to be inputted to TRIACs 4 to 9 to stop the driving of an AC motor 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC power controller for controlling the phase of a semiconductor switching element to control the power supplied to an AC load.

[0002]

2. Description of the Related Art An example of a conventional AC power control device is shown in FIG. The R, S, and T-phase power supply lines 1, 2, and 3 of the three-phase AC power supply forming the main circuit 14 are connected in antiparallel for each phase, and are triacs 4 to 9 as semiconductor switching elements.
Is connected to the AC motor 13 as a load.

A primary side of a three-phase transformer 15 is connected to power source lines 1, 2 and 3 on the power source side of the triacs 4 to 9 via fuses 16 to 18, and the three-phase transformer 1
The secondary side of 5 is connected to the input terminal of the synchronizing circuit 19. The synchronization circuit 19 uses, for example, R as a line voltage of a three-phase AC voltage induced on the secondary side of the three-phase transformer 15.
Two square waves synchronized with the S-phase voltage and the ST-phase voltage are output as synchronization signals. The output terminal of the synchronizing circuit 19 is connected to the input terminal of the phase control circuit 20. The phase control circuit 20 follows the speed designating signal designated by the speed designating means (not shown) to set the zero point of the interphase voltage obtained by the synchronizing signal. The phase of the triacs 4 to 9 is controlled as a reference timing. And three-phase transformer 1
5, the synchronization circuit 19 and the phase control circuit 20 constitute the phase control means 21.

Current detectors 22, 23 and 24 are disposed on the power supply lines 1, 2 and 3 on the load side of the triacs 4 to 9, and the output terminals of these current detectors 22, 23 and 24 are for the main circuit. It is connected to the input terminal of the open phase detection circuit 25. The main circuit open phase detection circuit 25 outputs a main circuit open phase signal when a predetermined imbalance is detected in the current of each phase. The output terminal of the main circuit open phase detection circuit 25 is connected to the input terminal of the phase control circuit 20, and the phase control circuit 20 receives the main circuit open phase signal, and then the gates for the triacs 4 to 9 are supplied. The signal is stopped to stop driving the AC motor 13. The phase control unit 21 and the main circuit open phase detection circuit 25 form a control circuit 26.

[0005]

In the conventional AC power control apparatus configured as described above, the phase loss on the main circuit 14 side can be detected, but only the phase control means 21 has the phase loss. In this case, the output signal of the synchronizing circuit 19 is out of phase with the synchronizing signal in the normal state, or the synchronizing signal is not output at all. Therefore, the phase control circuit 20 that determines the firing phase of the triacs 4 to 9 with the output signal of the synchronization circuit 19 as a reference causes the triacs 4 to 9 to fire at an abnormal phase and supplies the triacs 4 to 9 to the AC motor 13. There is a problem that the power changes and normal control cannot be performed. In this case, since there is no imbalance in the load currents of the respective phases of the main circuit 14, there is a problem that the main circuit open phase detection circuit 25 cannot detect the unbalance. The present invention has been made in consideration of the above circumstances, and an object thereof is to provide an AC power control device capable of detecting a phase loss even when a phase loss occurs in the phase control means.

[0006]

In order to achieve the above object, an AC power control apparatus according to claim 1 of the present invention comprises a semiconductor switching element interposed in a main circuit between an AC power supply and a load, Obtaining a synchronization signal synchronized with the AC power supply voltage, phase control means for controlling the phase of the semiconductor switching element of the main circuit based on the synchronization signal, and a main circuit open phase detection circuit for detecting open phase of the main circuit, And a phase loss detecting circuit for control means for detecting the phase loss of the phase control means.

According to a second aspect of the present invention, there is provided an AC power control apparatus including a semiconductor switching element interposed in a main circuit between a three-phase AC power supply and a load, and a three-phase transformer to which the three-phase AC power supply voltage is supplied. Phase control means for obtaining first and second synchronization signals synchronized with the three-phase AC power supply voltage, and controlling the phase of the semiconductor switching element of the main circuit based on the first and second synchronization signals, A main circuit open phase detection circuit for detecting a phase loss of the circuit, a signal match detection circuit for outputting a match signal when the first and second synchronization signals of the phase control means overlap, and this signal match detection circuit And a phase loss determination circuit for determining the phase loss based on the duty ratio of the coincidence signal.

In this case, the phase loss determination circuit may be configured to determine the phase loss when the duty ratio of the match signal generated by the signal match detection circuit becomes equal to or lower than the lower limit set value. (Claim 3).

Further, the phase loss determination circuit may be configured to determine the phase loss when the duty ratio of the coincidence signal generated by the signal coincidence detection circuit becomes equal to or higher than the upper limit set value ( Claim 4).

Further, in the phase loss judgment circuit, the duty ratio of the coincidence signal generated by the signal coincidence detection circuit is 0%.
It may be so arranged that it is determined that the phase is lost when the above condition occurs (claim 5).

The phase loss determination circuit has a duty ratio of 10 for the coincidence signal generated by the signal coincidence detection circuit.
The phase may be determined to be 0% when it reaches 0% (claim 6).

An AC power control apparatus according to a seventh aspect of the present invention comprises a semiconductor switching element interposed in a main circuit between a three-phase AC power supply and a load, and a three-phase transformer to which the three-phase AC power supply voltage is supplied. Phase control means for obtaining first and second synchronization signals synchronized with the three-phase AC power supply voltage, and controlling the phase of the semiconductor switching element of the main circuit based on the first and second synchronization signals, A main circuit open phase detection circuit for detecting a phase loss of the circuit, a phase difference detection circuit for detecting a phase difference between the first synchronization signal and the second synchronization signal of the phase control means, and this phase difference detection circuit. And a phase loss determination circuit for determining a phase loss based on the phase difference detected by the.

In this case, the phase loss determination circuit may be configured to determine the phase loss when the phase difference detected by the phase difference detection circuit is less than or equal to the lower limit set value (claim 8). . Further, the phase loss determination circuit may be configured to determine the phase loss when the phase difference detected by the phase difference detection circuit becomes equal to or more than an upper limit set value (claim 9).

According to a tenth aspect of the present invention, there is provided an AC power control device, wherein a semiconductor switching element interposed in a main circuit between a three-phase AC power source and a load, and first and second three-phase AC power source voltages are supplied. Of the single-phase transformer, obtains first and second synchronization signals synchronized with the three-phase AC power supply voltage, and controls the phase of the semiconductor switching element of the main circuit based on the first and second synchronization signals. A phase control means, a main circuit open phase detection circuit that detects a phase loss of the main circuit, and a signal coincidence detection circuit that outputs a coincidence signal when the first and second synchronization signals of the phase control means overlap. A phase loss determination circuit for determining a phase loss based on the duty ratio of the match signal of the signal match detection circuit.

In this case, in the open-phase judging circuit, the duty ratio of the coincidence signal generated by the signal coincidence detecting circuit exceeds the second predetermined value at the lower limit value or more exceeding the first predetermined value. You may comprise so that it may determine with a missing phase when it exists in the range below an upper limit (Claim 11).

The phase loss determination circuit determines the phase loss when the duty ratio of the coincidence signal generated by the signal coincidence detection circuit is equal to or less than a constant value less than the first predetermined value. May be configured (claim 12).

Further, the phase loss determination circuit determines the phase loss when the duty ratio of the coincidence signal generated by the signal coincidence detection circuit becomes equal to or more than a constant value exceeding the second predetermined value. It may be configured as described above (claim 13).

The duty ratio of the coincidence signal generated by the signal coincidence detection circuit is 0% in the open-phase determination circuit.
It may be so arranged that it is judged that the phase is out of phase when it becomes (claim 14).

Furthermore, the phase loss determination circuit has a duty ratio of 50 for the coincidence signal generated by the signal coincidence detection circuit.
It may be so arranged that it is determined that the phase is lost when the percentage is reached (claim 15).

The duty ratio of the coincidence signal generated by the signal coincidence detection circuit is 10 in the open-phase determination circuit.
The phase may be determined to be 0% when it reaches 0% (claim 16).

Further, the AC power control device according to any one of claims 1 to 16 may be configured so as to include a display device for separately displaying the open phase of the main circuit and the open phase of the phase control means. Good (Claim 17).

[0022]

According to the AC power control apparatus of the present invention, the open phase on the phase control means side is detected separately from the open phase on the main circuit side. Even if a phase occurs, it can be reliably detected.

According to another aspect of the AC power control apparatus of the present invention, the first and second synchronizing signals synchronized with the three-phase AC power supply voltage induced on the secondary side of the three-phase transformer connected to the three-phase AC power supply. Since the phase loss is determined on the basis of the duty ratio of the coincidence signal created by the above, it is possible to reliably detect the phase loss on the side of the phase control means when the three-phase AC power supply is used.

In this case, when the duty ratio of the coincidence signal becomes equal to or less than the lower limit set value, it is determined that the phase is open, the phase control corresponding to the three-phase AC power supply of R, S and T phases. Even if the first and second synchronization signals are not completely in-phase due to the R-phase or T-phase loss on the means side, the open-phase detection can be reliably performed (claim 3).

Further, when the duty ratio of the coincidence signal exceeds the upper limit set value, it is determined that the phase is out of phase, and the first and second phases are caused by the open phase of the S phase on the phase control means side. Even if the synchronization signals of 1 are not completely in-phase, the open phase detection can be reliably performed (claim 4).

Further, the duty ratio of the coincidence signal is 0%.
When it is configured to judge that the phase is lost when the phase becomes, the open phase detection is performed when the first and second synchronization signals are completely out of phase due to the open phase of the R or T phase on the phase control means side. Can be promptly performed (Claim 5).

The duty ratio of the coincidence signal is 10
If it is configured to judge that there is a missing phase when it reaches 0%,
Due to the open phase of the S phase on the phase control means side, the first and second
The phase loss detection can be promptly performed when the synchronization signals of 1 are completely in phase (claim 6).

Further, according to the alternating-current power control device of the seventh aspect, the phase difference between the first and second synchronization signals is detected, and the open phase is determined based on this phase difference. With this method, it is possible to surely detect the open phase on the phase control means side.

In this case, if the phase difference is less than or equal to the lower limit set value, it is determined that there is an open phase, and the first and second synchronization signals are generated by the open phase of the S phase on the phase control means side. It is possible to surely detect the open phase when the phases are substantially the same (claim 8).

When the phase difference is equal to or more than the upper limit set value, it is determined that the phase is out of phase, and the first and second synchronization signals are caused by the open phase of the R or T phase on the phase control means side. It is possible to surely detect the open phase when the phase becomes almost opposite (claim 9).

Further, according to the alternating-current power control device of the tenth aspect, the three-phase alternating-current power supply voltage is induced on the secondary side of the first and second single-phase transformers connected to the three-phase alternating-current power supply. The open phase is determined based on the duty ratio of the coincidence signal generated from the first and second synchronization signals, and in particular, when the duty ratio exceeds the lower limit value exceeding the first predetermined value, the second phase is determined. When it is in the range of the upper limit value or more exceeding the predetermined value (claim 11),
When the value is equal to or less than a certain value less than the first predetermined value (claim 1
2) Or, when the upper limit value is exceeded (claim 13), it is determined that there is an open phase, so even if two single phase transformers are used instead of the three phase transformer, the open phase detection of the phase control means is detected. Can be done reliably.

In this case, when the duty ratio of the coincidence signal is determined to be 0%, it is determined that the phase is open, and the first and second phases are caused by the open phase of the R or T phase on the phase control means side.
It is possible to promptly detect the phase loss when either one of the sync signals remains low level (claim 14).

The duty ratio of the coincidence signal is 50.
When it is configured to determine the phase loss when%, when either one of the first and second synchronization signals remains at the high level due to the phase loss of the R or T phase on the phase control means side. The open phase can be detected promptly (Claim 15).

Further, the duty ratio of the coincidence signal is 10
When the phase is determined to be the open phase when 0%, the open phase can be promptly detected when the first and second synchronization signals are in phase due to the open phase of the S phase on the phase control means side ( Claim 16).

According to the seventeenth aspect of the present invention, since the display device for individually displaying the open phase on the main circuit side and the open phase on the phase control means side is provided, any one of them can be selected depending on the display state. It becomes clear whether the phase loss occurred on the side of.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG.
As will be described with reference to FIG. 4, in FIG. 1, the same parts as those in FIG. 9 of the conventional example are denoted by the same reference numerals and the description thereof will be omitted. The output terminal of the synchronization circuit 19 is connected to the input terminal of the signal coincidence detection circuit 27, and the output terminal of the signal coincidence detection circuit 27 is connected to the input terminal of the open phase determination circuit 28. In this case, the signal coincidence detection circuit 27 and the open phase determination circuit 28 are
It operates as will be described later, and these constitute the control means open-phase detection circuit 29. The phase loss determination circuit 2
The output terminals of 8 are connected to the input terminals of the phase control circuit 20 and the phase control means phase-break display device 30. The output terminal of the main circuit open phase detection circuit 25 is connected to the input terminal of the main circuit open phase display device 31. The phase control means 21, the main circuit open phase detection circuit 25, and the control means open phase detection circuit 29 form a control circuit 32.

Next, the operation of this embodiment will be described with reference to FIGS. 2 to 4. FIG. 2 shows the phase control means 2
1 shows the signal output state of each part in the normal state where no phase loss occurs. That is, as shown in FIG. 2A, the synchronization circuit 19 detects the RS inter-phase voltage VRS and the ST inter-phase voltage VST, which are line voltages on the secondary side of the three-phase transformer 15, and
As shown in (b) and (c), the first and second synchronization signals SR of high level H corresponding to these positive (+) half waves.
Output S and SST. Then, the phase control circuit 20
Are the first and second synchronization signals SRS and SST
The zero crossing points of the R, S and T phase voltages corresponding to the power supply lines 1, 2 and 3 are detected from the main circuit 14 based on the detected zero crossing points.
The semiconductor switching elements 4 to 9 are subjected to firing angle control (phase control).

The first and second synchronizing signals SRS and SST from the synchronizing circuit 19 are given to the signal coincidence detecting circuit 27, which, as shown in FIG. When the second synchronization signals SRS and SST match (duplicate), a match signal C of high level H
Output S. In this case, the duty ratio of the coincidence signal CS is theoretically (60/180) × 100%.

FIG. 3 shows each signal output corresponding to FIG. 2 when the T phase of the phase control means 21 is missing. Since the RS phase of the three-phase transformer 15 is normal, the voltage RS between the RS phases on the secondary side shown in FIG. 3A is output in the same manner as in FIG. 2A. However, the ST phase of the three-phase transformer 15 loses the excitation from the primary side due to the open phase of the T phase, but since it is magnetically coupled to the RS phase, the ST phase on the secondary side is 180 degrees apart from the RS phase. Voltages out of phase are induced. Therefore, the synchronizing signals SRS and SST from the synchronizing circuit 19 are as shown in FIG.
As shown in (b) and (c), the coincidence signals CS from the signal coincidence detection circuit 27 are out of phase with each other.
As shown in (d), theoretically, there is no signal with a duty ratio of 0%.

FIG. 4 shows a case where the S phase is missing.
The RS and ST phases on the secondary side of the three-phase transformer 15 are generated by the magnetic flux induced by the RT phase voltage on the primary side.
In-phase voltage as shown in (a) appears. Therefore, FIG.
As shown in (b) and (c), the first and second synchronization signals SRS and SST are also in phase. As a result, the duty ratio of the coincidence signal CS of the signal coincidence detection circuit 27 theoretically becomes 100% as shown in FIG. When the R phase is out of phase, it is the same as when the T phase is out of phase.

Therefore, the phase loss determination circuit 28 is configured to output the phase control means phase loss signal for the R and T phases when the match signal CS of the signal match detection circuit 27 becomes 0% in duty ratio. By doing so, the open phase of the R phase or the T phase can be detected. Further, if the phase loss determination circuit 28 is configured to output the phase control means phase loss signal for S phase when the coincidence signal CS of the signal coincidence detection circuit 27 reaches the duty ratio of 100%, the S phase is detected. The open phase of can be detected.

However, in an actual circuit, there are imbalances in the three-phase transformer 15 and variations in circuit constants. Therefore, when the theoretical duty ratio (60/180) × 100% of the coincidence signal CS of the signal coincidence detection circuit 27 observed during the normal operation is set as a predetermined value, a certain value less than the predetermined value is set. If the duty ratio of the coincidence signal CS actually observed is set to the lower limit set value and is less than or equal to the lower limit set value, it is determined that the phase is open, and the phase control means open phase signal for R and T phases is output, Further, a certain value exceeding the predetermined value is set as the upper limit set value, and when the actually observed duty ratio of the coincidence signal CS is equal to or more than the upper limit set value, it is judged as a phase loss and the phase for S phase is used. The phase loss determination circuit 28 is also configured to output the control means phase loss signal.

When the phase loss determination circuit 28 determines the phase loss according to the state of the coincidence signal CS from the signal coincidence detection circuit 27, the phase control means phase loss signal is output to the phase control circuit 20.
And to the phase control means phase-disruptive display device 30. The phase control circuit 20 outputs the main circuit open phase signal output from the main circuit open phase detection circuit 25 or the open phase determination circuit 28.
When any one of the phase control means open-phase signals output by is input, the gate signals to the triacs 4 to 9 are stopped and the driving of the AC motor 15 is stopped. In the open-phase display device 30 for phase control means, the open-phase determination circuit 28 has R, T
When the phase control means open phase signal for phase is output, it is displayed on the phase control means 21 side that an R phase or T phase open phase has occurred, and the open phase determination circuit 28 indicates the phase control means open phase signal for S phase. Is output, it is displayed on the phase control means 21 side that the S-phase open phase has occurred. In addition, the main circuit open phase display device 3
When the main circuit open phase detection circuit 25 outputs a main circuit open phase signal, 1 indicates that the main circuit 14 side has received the open phase in response to the output.

As described above, according to the present embodiment, the RS interphase voltage V on the secondary side of the three-phase transformer 15 of the phase control means 21.
The first and second synchronizing signals SRS and SST are obtained from the RS and ST inter-phase voltage VST by the synchronizing circuit 19, and when the duty ratio of the coincidence signal CS with which they overlap is 0% or 100%, the open phase determination circuit. 28 is a phase control means 21
The phase control means open phase signal is output as the open phase.

Therefore, when the phase control means 21 is out of phase, when the duty ratio of the coincidence signal CS of the first and second synchronization signals SRS and SST becomes 0% or 100%, the phase is lost. The phase determination circuit 28 uses the both sync signals SRS
And that the SST is completely out of phase or in-phase, it is promptly judged that the phase control means 21 is out of phase, and the phase control means open phase signal is output. The phase loss on the side of the phase control means 21 can be reliably detected.

Further, the open-phase determination circuit 28 uses the coincidence signal CS
The duty ratio of the predetermined value ((60/180) × 100
%), The phase control means 21 is judged to be out of phase and the phase control means open phase signal is output even when it becomes equal to or more than the lower limit set value less than%) or more than the upper limit set value exceeding a predetermined value. When a phase loss occurs in the means 21, the duty ratio of the coincidence signal CS is theoretically 0% or 100 due to the imbalance of the three-phase transformer 15 and the variation of the circuit constants.
Even if the percentage does not reach%, it can be surely detected as the open phase, and no detection error occurs.

Then, the open phase display device 30 for the phase control means
When the phase control means open phase signal is given from the open phase determination circuit 28, the open phase display of the R phase or the T phase or the open phase of the S phase is performed. When the main circuit open phase signal is given from the open phase detection circuit 25, the open phase is displayed, so that the operator can easily determine which side of the main circuit 14 and the phase control means 21 the open phase has occurred. Is possible and is extremely effective in work.

5 to 7 show a second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The different parts will be described below. That is, unlike FIG. 1, the output terminal of the synchronization circuit 19 is connected to the input terminal of the phase difference detection circuit 33, and the output terminal of the phase difference detection circuit 33 is connected to the input terminal of the open phase determination circuit 34.
Further, the output terminal of the open phase determination circuit 34 is the phase control circuit 20.
And an input terminal of the phase-failure display device 30 for the phase control means. The phase difference detection circuit 33 and the open phase determination circuit 34
Constitutes a control means open-phase detection circuit 35, and the control means open-phase detection circuit 35 forms a control circuit 36 by the phase control means 21 and the main circuit open-phase detection circuit 25.

In the above structure, the phase difference detection circuit 33 detects the phase difference between the first and second synchronization signals SRS and SST and outputs the phase difference signal PS to the open phase determination circuit 34. The phase loss determination circuit 34 receives the phase difference signal PS and determines the phase loss as described later.

FIG. 6 shows the output state of each signal in the normal state, and FIG. 7 shows the output state of each signal in the T phase open phase. FIG. 6 (a),
(B) and (c) are the voltages between RS phases and ST phases on the secondary side of the three-phase transformer 15 and the corresponding first and second synchronization signals SRS and SST, respectively, as in FIG.
The phase relationship of each signal is also the same as in FIG. Figure 7
(A), (b) and (c) also show output states similar to those in FIG. In the normal state, the phase difference between SRS and SST between the first sync signal and the second sync signal is 120 degrees as shown in FIGS. 6B and 6C, but when the T phase is missing, It becomes 180 degrees as shown in 7 (b) and 7 (c). When the R phase is out of phase, the phase difference between the synchronization signals SRS and SST is 180 degrees, as in the case of the T phase, and when the S phase is out of phase, it is 0 degrees.

Therefore, the phase loss determination circuit 34 controls the phase loss control signal for the S phase or the control for the R and T phases when the phase difference output from the phase difference detection circuit 33 becomes 0 degree or 180 degrees. It is configured to output the means open phase signal. In this case as well, the three-phase transformer 15 is used as in the first embodiment.
, The phase difference is less than 120 degrees, the observed phase difference is less than or equal to the lower limit value, or the phase difference is more than 120 degrees. Is set as an upper limit set value, and when the observed phase difference is equal to or more than the upper limit set value, the S-phase control means open-phase signal or the R, T-phase control means open-phase signal is output. .

FIG. 8 shows a third embodiment of the present invention, and FIG.
The same parts as those in FIG.
The different parts will be described. That is, the difference from FIG. 1 is that the first single-phase transformer 37 and the second single-phase transformer 38 are used instead of the three-phase transformer 15. The primary side of the first single-phase transformer 37 is the fuse 1
The fuses 17 and 1 are connected to the R-phase and S-phase power supply lines 1 and 2 via 6 and 17, and the primary side of the second single-phase transformer 38.
8 are connected to the S-phase and T-phase power supply lines 2 and 3. Further, the secondary sides of the first and second single-phase transformers 37 and 38 are connected to the input terminal of the synchronizing circuit 19 with the terminals corresponding to the S phase being common to both, and thus the phase control means 39.
Is configured. The output terminal of the signal coincidence detection circuit 27 is connected to the input terminal of the open phase determination circuit 40, and the output terminal of the open phase determination circuit 40 is connected to the input terminals of the phase control circuit 20 and the phase control means open phase display device 30. Thus, the control means open-phase detection circuit 41 is configured. The phase control unit 39, the main circuit open phase detection circuit 25, and the control unit open phase detection circuit 40 form a control circuit 42.

In the operation of the above configuration, the difference from FIG. 1 is that when the R phase or the T phase is missing, the first single phase transformer 37 and the second single phase transformer 38 are magnetically coupled. Therefore, the secondary side output of the single-phase transformer of the missing phase becomes 0V, and the corresponding synchronizing signal of the synchronizing circuit 19 remains at the high level H or the low level L (the circuit of the synchronizing circuit 19 at that time). Depending on the condition). Therefore, the coincidence signal CS of the signal coincidence detection circuit 27 becomes the same as the synchronization signal corresponding to the normal two phases when the synchronization circuit 19 outputs the high level H at the input level 0V, and its duty ratio is theoretical. Target is 50%.

Therefore, the coincidence signal CS of the signal coincidence detection circuit
If the open phase determination circuit 40 is configured to determine the open phase when the duty ratio becomes 50%, the open phase of the R phase or the T phase can be detected.

Also in this case, considering the magnetic imbalance of the single-phase transformers 37 and 38 and the variation of the circuit constants as in the first and second embodiments, the open-phase determination circuit 40 has the predetermined phase in the first embodiment. Value is (60/180) x 100%
Is a first predetermined value, a certain value exceeding the first predetermined value is set as a lower limit value, and a duty ratio of 50% is a second predetermined value, and a certain value exceeding the second predetermined value. Is set as the upper limit value, and the coincidence signal CS of the observed signal coincidence detection circuit 27 is
Is also determined to be an open phase when the value is within the range from the lower limit value to the upper limit value.

Further, the coincidence signal CS of the signal coincidence detection circuit 27 remains at the low level L when the synchronization circuit 19 outputs the synchronization signal at the low level L. Therefore, the phase loss determination circuit 40 determines the phase loss when the duty ratio of the coincidence signal CS of the signal coincidence detection circuit 27 is 0% or when the duty ratio is less than a certain constant value less than the first predetermined value. It is also configured to judge.

When the S-phase is missing, the S-phase input terminals on the primary side of the first and second single-phase transformers 37 and 38 are connected to each other, so that the first and second S-phase input terminals are connected. Since the in-phase voltage obtained by dividing the RT-phase voltage at the midpoint appears in the secondary RS-phase and ST-phase outputs of the single-phase transformers 37 and 38, the coincidence signal CS of the signal coincidence detection circuit 27 is high. It remains at level H. Therefore, the open phase determination circuit 4
0 is the duplication of the coincidence signal CS of the signal coincidence detection circuit 27.
If the tee ratio is 100%, or if variations in circuit constants are taken into consideration, the phase may be determined to be a phase loss above the upper limit value. In each of the above embodiments, the first and second
The line voltage of the three-phase AC power supply to obtain the synchronization signal of
Although the phase and the ST phase are used, the combination is not limited to this, and it goes without saying that the ST phase and the RT phase or the RT phase and the RS phase may be used.

[0058]

As is apparent from the above description, according to the AC power control apparatus of the first aspect of the present invention, the phase loss on the phase control means side is detected separately from the phase loss on the main circuit side. Therefore, even if a phase loss occurs only on the phase control means side, this can be detected with certainty, and the load can be prevented from falling into an abnormal drive state.

According to the alternating-current power control device of the second aspect, the first and second synchronization signals synchronized with the three-phase AC power supply voltage induced on the secondary side of the three-phase transformer connected to the three-phase AC power supply. Since the phase loss is determined on the basis of the duty ratio of the coincidence signal created by the above, it is possible to reliably detect the phase loss on the side of the phase control means when the three-phase AC power supply is used.

In this case, when the duty ratio of the coincidence signal becomes equal to or less than the lower limit set value, it is judged that the phase is open, the phase control corresponding to the three-phase AC power supply of R, S and T phases. Even if the first and second synchronization signals are not completely in-phase due to the R-phase or T-phase loss on the means side, the open-phase detection can be reliably performed (claim 3).

Further, when the duty ratio of the coincidence signal exceeds the upper limit set value, it is determined that there is an open phase, and the first and second phases are caused by the open phase of the S phase on the phase control means side. Even if the synchronization signals of 1 are not completely in-phase, the open phase detection can be reliably performed (claim 4).

The duty ratio of the coincidence signal is 0%.
When it is configured to judge that the phase is lost when the phase becomes, the open phase detection is performed when the first and second synchronization signals are completely out of phase due to the open phase of the R or T phase on the phase control means side. Can be promptly performed (Claim 5).

Further, the duty ratio of the coincidence signal is 10
If it is configured to judge that there is a missing phase when it reaches 0%,
Due to the open phase of the S phase on the phase control means side, the first and second
The phase loss detection can be promptly performed when the synchronization signals of 1 are completely in phase (claim 6).

According to the alternating-current power control device of the seventh aspect, the phase difference between the first and second synchronization signals is detected, and the open phase is determined based on the phase difference. With this method, it is possible to surely detect the open phase on the phase control means side.

In this case, when the phase difference is less than or equal to the lower limit set value, it is determined that there is an open phase, and the first and second synchronization signals are generated by the open phase of the S phase on the phase control means side. It is possible to surely detect the open phase when the phases are substantially the same (claim 8).

Further, when the phase difference is determined to be the upper limit set value or more, it is determined that the phase is open, the phase control means side R or T phase open phase causes the first and second synchronization signals. It is possible to surely detect the open phase when the phase becomes almost opposite (claim 9).

Further, according to the alternating-current power control device of the tenth aspect, the three-phase alternating-current power supply is synchronized with the three-phase alternating-current power supply voltage induced on the secondary side of the first and second single-phase transformers. The open phase is determined based on the duty ratio of the coincidence signal generated from the first and second synchronization signals, and in particular, when the duty ratio exceeds the lower limit value exceeding the first predetermined value, the second phase is determined. When it is in the range of the upper limit value or more exceeding the predetermined value (claim 11),
When the value is equal to or less than a certain value less than the first predetermined value (claim 1
2) Or, when the upper limit value is exceeded (claim 13), it is determined that there is an open phase, so even if two single phase transformers are used instead of the three phase transformer, the open phase detection of the phase control means is detected. Can be done reliably.

In this case, when the duty ratio of the coincidence signal is 0%, it is determined that the phase is out of phase, and the first and second phases are caused by the open phase of the R or T phase on the phase control means side.
It is possible to promptly detect the phase loss when either one of the sync signals remains low level (claim 14).

The duty ratio of the coincidence signal is 50.
When it is configured to determine the phase loss when%, when either one of the first and second synchronization signals remains at the high level due to the phase loss of the R or T phase on the phase control means side. The open phase can be detected promptly (Claim 15).

Further, the duty ratio of the coincidence signal is 10
When the phase is determined to be the open phase when 0%, the open phase can be promptly detected when the first and second synchronization signals are in phase due to the open phase of the S phase on the phase control means side ( Claim 16).

Further, according to the alternating-current power control device of the seventeenth aspect, since the display device for individually displaying the open phase on the main circuit side and the open phase on the phase control means side is provided, any one of them can be displayed depending on the display state. It becomes clear whether the phase loss occurred on the side of.

[Brief description of drawings]

FIG. 1 is a block diagram of an electrical configuration showing a first embodiment of the present invention.

[Fig. 2] Operation explanatory diagram in normal state

FIG. 3 is an operation explanatory diagram when the T phase is out of phase.

FIG. 4 is an operation explanatory diagram when the S phase is open.

FIG. 5 is a block diagram of an electrical configuration showing a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of operations in a normal state.

FIG. 7 is an explanatory diagram of an operation when the T phase is out of phase.

FIG. 8 is a block diagram of an electrical configuration showing a third embodiment of the present invention.

FIG. 9 is a block diagram of an electrical configuration showing a conventional example.

[Explanation of symbols]

4 to 9 are triacs (semiconductor switching elements),
10 to 12 are current detectors, 13 is an AC motor (load), 14 is a main circuit, 15 is a three-phase transformer, 19 is a synchronous circuit, 20 is a phase control circuit, 21 is phase control means, 25
Is an open phase detection circuit for the main circuit, 27 is a signal coincidence detection circuit, 2
8 is a phase loss determination circuit, 29 is a phase loss detection circuit for control means, 3
Reference numeral 0 denotes a phase control means open phase display device, 31 a main circuit open phase display device, 32 a control circuit, 33 a phase difference detection circuit, 3
Reference numeral 4 is a phase loss determination circuit, 35 is a phase loss detection circuit for control means, and 3
6 is a control circuit, 37 is a first single-phase transformer, and 38 is a second
1 is a single-phase transformer, 39 is a phase control means, 40 is a phase loss determination circuit, 41 is a phase loss detection circuit for control means, and 42 is a control circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H02M 1/00 C H02P 7/36 302 S

Claims (17)

[Claims] 1. A semiconductor switching element interposed in a main circuit between an AC power supply and a load, and a synchronization signal synchronized with the AC power supply voltage, and phase control of the semiconductor switching element based on the synchronization signal. AC power control device comprising phase control means, main circuit open phase detection circuit for detecting open phase of the main circuit, and control means open phase detection circuit for detecting open phase of the phase control means . 2. A semiconductor switching element interposed in a main circuit between a three-phase AC power supply and a load, and a three-phase transformer to which the three-phase AC power supply voltage is supplied, and synchronized with the three-phase AC power supply voltage. Phase control means for controlling the phase of the semiconductor switching element based on the first and second synchronization signals, and a main circuit for detecting a phase loss of the main circuit A phase loss detection circuit, a signal coincidence detection circuit that outputs a coincidence signal when the first and second synchronization signals of the phase control means overlap, and based on the duty ratio of the coincidence signal of the signal coincidence detection circuit AC power control device comprising a phase loss determination circuit for determining phase loss. 3. The phase loss determination circuit is configured to determine a phase loss when a duty ratio of a match signal generated by the signal match detection circuit is equal to or lower than a lower limit set value. The AC power control device according to claim 2. 4. The phase loss determination circuit is configured to determine the phase loss when the duty ratio of the match signal generated by the signal match detection circuit becomes equal to or higher than an upper limit set value. The AC power control device according to claim 2. 5. The phase loss determination circuit is configured to determine the phase loss when the duty ratio of the match signal generated by the signal match detection circuit becomes 0%. The AC power control device according to claim 2. 6. The duty ratio of the coincidence signal generated by the signal coincidence detection circuit is 100% in the open-phase determination circuit.
The AC power control device according to claim 2, wherein the AC power control device is configured to determine that the phase is lost when the above condition occurs. 7. A semiconductor switching element interposed in a main circuit between a three-phase AC power supply and a load, and a three-phase transformer to which the three-phase AC power supply voltage is supplied, the synchronous circuit being synchronized with the three-phase AC power supply voltage. Phase control means for controlling the phase of the semiconductor switching element based on the first and second synchronization signals, and a main circuit for detecting a phase loss of the main circuit A phase loss detection circuit, a phase difference detection circuit that detects a phase difference between the first synchronization signal and the second synchronization signal of the phase control unit, and a phase loss based on the phase difference detected by the phase difference detection circuit. An AC power control device comprising: 8. The phase loss determination circuit is configured to determine a phase loss when the phase difference detected by the phase difference detection circuit is equal to or less than a lower limit set value. The described AC power control device. 9. The phase loss determination circuit is configured to determine a phase loss when the phase difference detected by the phase difference detection circuit is equal to or greater than an upper limit set value. The described AC power control device. 10. A semiconductor switching device interposed in a main circuit between a three-phase AC power supply and a load, and first and second single-phase transformers to which the three-phase AC power supply voltage is supplied. First synchronized with phase AC power supply voltage
And a second synchronization signal, and phase control means for controlling the phase of the semiconductor switching element based on the first and second synchronization signals, and a main circuit open phase detection for detecting a open phase of the main circuit. A circuit, a signal coincidence detection circuit that outputs a coincidence signal when the first and second synchronization signals of the phase control means overlap, and a phase loss based on the duty ratio of the coincidence signal of the signal coincidence detection circuit. An AC power control device comprising: 11. The upper limit value in which the duty ratio of the coincidence signal generated by the signal coincidence detection circuit is equal to or more than a lower limit value exceeding a first predetermined value and exceeds a second predetermined value in the phase loss determination circuit. 11. The alternating current power control device according to claim 10, wherein the alternating current power control device is configured to determine that the phase is out of the range when in the following range. 12. The phase loss determination circuit determines the phase loss when the duty ratio of the coincidence signal generated by the signal coincidence detection circuit is equal to or less than a constant value less than the first predetermined value. The AC power control device according to claim 10, wherein the AC power control device is configured as described above. 13. The phase loss determination circuit is configured to determine a phase loss when a duty ratio of a match signal generated by the signal match detection circuit exceeds the upper limit value. The AC power control device according to claim 10. 14. The phase loss determination circuit is configured to determine a phase loss when a duty ratio of a match signal generated by the signal match detection circuit becomes 0%. The AC power control device according to claim 10. 15. The duty ratio of the coincidence signal generated by the signal coincidence detection circuit is 50% in the open-phase determination circuit.
11. The AC power control device according to claim 10, wherein the AC power control device is configured to determine that the phase is lost when it becomes. 16. The duty ratio of the coincidence signal generated by the signal coincidence detection circuit is 100 in the open-phase determination circuit.
The alternating-current power control device according to claim 10, wherein the alternating-current power control device is configured to determine that the phase is lost when the percentage is reached. 17. The AC power control device according to claim 1, further comprising a display device for separately displaying the open phase of the main circuit and the open phase of the phase control means.