JPH08161389A - Circuit simulating method and circuit simulator - Google Patents

Abstract

PURPOSE: To more correctly simulate delay time by calculating the delay time by using the ratio of length of wiring to a branched destination node and the total length of a tree to constitute an RC net and the total length of the three. CONSTITUTION: Three pieces of the branched destination nodes N11 to N13 are connected to the output terminal (drive node) N1 of a circuit cell 5. About the drive node N1 of each circuit cell, the total length lT of the three to constitute the RC net and the wiring length l1k to each branched destination N11 to N13 (N1k ) are read out of the data base of prelayout or postlayout. Then, about each branched destination node N1 , Rw is determined from an expression Rw =l1k /lT. Since the ratio Rw of the wiring length l1k to each branched destination N1k and the total length lT of the three calculated by this Rw calculation represents quantitatively the feature of the delay time of the wiring, the delay time is calculated by using this Rw and the total length lT of the three.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an LSI (Large Scale I
CAD (Computer Aided Decoder) for ntegated circuit design
The present invention relates to a circuit simulation method and a circuit simulator in a sign system).

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, some documents were described in the following documents. Reference 1: Japanese Patent Application Laid-Open No. 04-205661 Reference 2: Nishikubo, "Introduction to Circuit Simulator SPICE", Japan Industrial Technology Center, P. 16 Reference 3; Toshiba Review, 49 [11] (1994), Urata, Takayoshi, Yamada “0.4 μm gate array TC200.
G series "P.779-782 Fig. 2 is a flowchart showing a conventional circuit simulation method. The conventional circuit simulation method will be described with reference to Fig. 2. In step S1,
The output terminal of the circuit cell of the netlist and the resistance and capacitance of the net connecting this output terminal and the branch destination node are input from a file. In step S2, a delay time to the branch destination node (hereinafter referred to as tpd) is calculated by an algebraic calculation method applying the Laplace transform. In step S3, the tpd calculated in step 2 is output to a file. The tpd output to this file is used by the timing verification unit. Further, in the above-mentioned document 1, the wiring portion is treated as one cell to improve the accuracy of timing verification. That is, the change in the delay time due to the complicated branch wiring is simply due to the capacitive load. This is because having one delay time in the node of the circuit cell makes it impossible to perform the timing verification with the accuracy required for the current minute LSI.

FIG. 3 is a diagram showing a method of describing the capacity described in the netlist of the circuit simulator described in the above reference 2. In the figure, 13,0 is defined as a node number, and 1 is defined as having a 1 μF capacitor C0001 between the node numbers 13 and 0. In the conventional circuit simulator, the netlists extracted from the layout are designated according to the one capacitance designation method shown in FIG. FIG. 4 is a diagram showing a circuit simulation method using a conventional look-up table. In general,
ICs for specific applications represented by gate arrays (hereinafter referred to as A
In the development environment of (SIC), the load on the internal circuit is treated as a capacitive load and the delay characteristics are evaluated so that the circuit design can be easily performed without necessarily being familiar with the layout of the LSI. Reference 3 shows a circuit simulation method for evaluating delay characteristics using a look-up table. In this circuit simulation method,
In order to correspond to high precision, the size of capacitive load Cn
(N = 0 to 3) and rounded input waveform Sn (n = 0 to 3)
The circuit simulation (delay calculation) was performed by combining and.

[0004]

However, in the conventional circuit simulation method and circuit simulator,
There were the following problems (a) to (f). (A) 10m like clock line in LSI
In the signal wiring that exceeds m, the delay time calculated by the algebraic calculation method is slower than the actual delay time at the near end of the long wiring, and conversely, faster than the actual delay time at the far end. There was an error that it became too much. In addition, the degree of this error depends on the setup of the flip-flop of the submicron generation MOS type logic LSI.
Compared to the hold time value, it is no longer negligible. Also, in a layout that has various branches, it is difficult to improve the accuracy by sufficiently following the deviation of the branch destination node. (B) Even if there is a feature in the distribution of branch destination nodes and it is not necessary to calculate the delay time for all the nodes, deviation of the nodes, quantification of the distribution, and stratification based on this cannot be performed. In addition, the delay time is uniformly calculated for all branch destination nodes. Therefore, useless circuit simulation is performed. (C) As described in Document 1, in order to perform timing verification in combination with a circuit cell, data of both the self-evident logical result “true” and the delay time are provided, that is, the wiring cell is regarded as the circuit cell. It must be treated as an equivalent cell, and in a large-scale LSI, the data amount of this wiring cell becomes large, including a logical expression for expressing an obvious logic or its logical result, in response to a complicated wiring form. Computer data processing was overloaded and was a problem. (D) The delay time of the connected circuit cells generally differs for each input terminal. In this case, the delay time of the wiring portion also differs correspondingly. However, if the timing verification target is divided into two, that is, a circuit cell and a wiring cell, it is necessary to consider an interface for transferring such information, which causes a problem in that the data processing by the computer becomes overloaded.

(E) In the conventional circuit simulator, the capacitance between the wiring and the substrate or the upper and lower wirings and the capacitance including the parasitic effect (fringing effect) generated between the adjacent wirings can be distinguished from the capacitance other than the wiring portion. Therefore, it is difficult to execute a highly accurate circuit simulation that reflects the capacitance value specific to the LSI wiring. In particular, in an LSI design method in which a netlist for circuit simulation is extracted from LSI layout data and the timing is verified by a circuit simulator using this, LSI wiring is performed for the capacity described in the netlist on the circuit simulator side. There is no means to correct the content of the described capacitance in accordance with the type of parasitic effect of. Further, there is no means for reallocating one capacitance of the netlist node of the target wiring corresponding to the adjacent wiring or the upper layer wiring to the node of another netlist corresponding to the type of the parasitic effect. (F) Some of the minute LSIs to be developed cannot perform a sufficient circuit simulation by using only one item of the simple capacitive load Cn as the circuit load, as in Reference 3. . For example, it is hard to say that in an ASIC in which the wiring structure is multi-layered, the parasitic load effect of the resistance value and the capacitance value related to the wiring pattern layout can be sufficiently expressed. Therefore, the timing verification before and after the layout did not always match the delay time of both as expected. If they do not match, it is necessary to redo the wiring pattern layout. In other words, it was not satisfactory in terms of technology, cost and delivery.

[0006]

In order to solve the above-mentioned problems, a first invention is a circuit for calculating a delay time of signal propagation between an output terminal of a circuit cell and a branch destination node connected to the output terminal. In the simulation method, the following processing is executed. That is, the ratio R _W between the output terminal of the circuit cell, the wiring length to each branch destination node connected to the output terminal, and the total length of the tree that constitutes the RC net connected to the output terminal is calculated. and R _W calculation processing for, and a delay time calculation process for calculating the delay time by using the entire length of the R _W and the tree calculated by the R _W calculation processing, so as to execute. The second invention is the first
In the same circuit simulation method as that of the above invention, the following processing is executed. That is, the ratio of the output terminal of the circuit cell of the first invention, the wiring length to each branch destination node connected to the output terminal, and the total length of the tree that constitutes the RC net connected to the output terminal. and R _W calculation processing of calculating the R _W, the statistical method of R _W calculated by the R _W calculation processing as statistics, and clustering process for clustering the connected branch destination node to said output terminal, said clustering The delay time calculation processing for calculating the delay time to the branch destination node representing each class is executed.

According to a third aspect of the invention, in the circuit simulation method similar to that of the first aspect, the following processing is executed. R _W calculating the ratio R _W of the total length of the tree constituting an RC net connected to the output terminal and the wiring length to each branch destination node connected to the output terminal and the output terminal of the circuit cell (tree) A calculation process; a first delay time calculation process for calculating a delay time corresponding to the total length of the tree when the total length of the tree is smaller than a threshold; and the number of branch destination nodes connected to the output terminal If R _W is a number that cannot be treated as a random variable, a second delay time calculation process for calculating the delay time to each branch destination node, and R
_When the variation of _W is small, a third delay time calculation process for calculating the delay time corresponding to the average of R _W is executed. Then, the a first clustering process for clustering evenly the branch destination node R _W when the distribution of R _W is a discrete, when the distribution of the R _W is a random distribution, the R _W A second clustering process for clustering the branch destination nodes according to the standard deviation;
When the distribution of R _W is neither discrete type nor random, a third clustering process of clustering the branch destination nodes based on the distribution of each mountain of the distribution of R _W , and the first, second, or third And a fourth delay time calculation process for calculating the delay time of the representative of each class clustered by the clustering process of.

According to a fourth aspect of the present invention, in the circuit simulation method similar to that of the first aspect, the following processing is executed. That is, the ratio R _W of the output terminal of the circuit cell, the wiring length to each branch destination node connected to the output terminal, and the total length of the tree that constitutes the RC net connected to the output terminal is calculated. R _W calculation processing, an algebraic calculation processing for calculating the delay time to the branch destination node connected to the output terminal by an algebraic calculation method applying Laplace transform, and a delay time calculated by the algebraic calculation processing for the R _W The delay time correction process for correcting the delay time is executed. A fifth aspect of the present invention is the delay time correction process of the fourth aspect of the invention, wherein the delay time calculated by the algebraic calculation process is used as the explanatory variable element based on the variable amount based on the total wiring length and the R _{W. In} order to reduce the error when _W is small and when _W is large, the correction is performed by dividing by the correction value Y ₁ of the equation (3) or the correction value Y ₂ of the equation (4) calculated by the multiple regression equation. _{Y 1 = a 1 + b 1} l T + c 1 / R W ··· (3) Y 2 = a 2 + b 2 (R W -c 2) l T / R W ··· (4) where, a ₁ , B ₁ , c ₁ , a ₂ , b ₂ , c ₂ are parameters, c ₂ is a value greater than 0 and less than 1, and l _T is the total length of the tree.

According to a sixth aspect of the invention, in the circuit simulation method similar to that of the first aspect, the following processing is executed. That is, the ratio R _W of the wiring length to the branch destination node connected to the output terminal connected to the output terminal of the circuit cell and the total length of the tree forming the RC net connected to the output terminal , Before modification of layout
Wherein R _W respectively mean and modifications before after-between R _W input process of inputting both R _W, unmodified after-the R _W after
And a test process for testing whether or not the hypothesis that the respective variance values are equal to each other is satisfied by a statistical method, and the test result of the test process is that at least one of the mean value and the variance value is different. Only when the result is, the delay time calculation processing for calculating the delay time to the branch destination node is executed for the circuit cell of the corrected layout.

A seventh aspect of the invention is to carry out the verification process of the fifth aspect of the invention.
If R _W is normally distributed after the pre-correction-normal distribution to test the average value of R _W of the corrected front and as follows a normal distribution, chi-square distribution variance values of R _W of the corrected front and and test process, if not R _W is normally distributed after the modified front and, assaying mean a t distribution R _W of the modified front and, the dispersion value of R _W of the corrected front and as a follow F distribution It is composed of non-normal distribution test processing. An eighth invention is a circuit simulation method similar to the first invention, wherein a delay time by a basic gate that outputs only a logical "true" including an output terminal of a circuit cell of the first invention and a wiring to a branch destination node. The delay data of 1 is provided as an array corresponding to the output terminal or the input terminal of the circuit cell. In a ninth aspect of the invention, a plurality of the delay data are provided for each output terminal of the circuit cell of the eighth aspect. The tenth invention is
In the ninth invention, a ratio R of an output terminal of a circuit cell, a wiring length to each branch destination node connected to the output terminal, and a total length of a tree forming an RC net connected to the output terminal By clustering the branch destination nodes based on _W , the plurality of delay data are provided. In an eleventh aspect of the invention, the delay data of the eighth to the tenth aspects of the invention are made to have the dependency of the input terminal of the circuit cell.

In a twelfth aspect of the invention, the delay data of the eighth to eleventh aspects is made to have temperature dependency of the circuit cell. A thirteenth invention has the following configuration in a circuit simulator that performs timing verification based on a netlist extracted by a circuit layout.
That is, the netlist input section for inputting the netlist, the correspondence between the nodes defined in the netlist and the wiring on the layout, the positional relationship between the nodes, the wiring area of the node, and the perimeter of the wiring. A node information input section for inputting, and an allocation method input section for inputting a capacity allocation method for designating which wiring and board or between which wiring, and the node and wiring input by the node information input section. Based on the correspondence of and the positional relationship between nodes,
A wiring capacitance selection unit for inputting a parameter of a flat plate capacitance per unit area and a parameter of a fringing capacitance per unit length of a target wiring specified by the capacitance allocation method from a wiring capacitance parameter file, and is selected by the wiring capacitance selection unit. A wiring capacitance parameter, and a capacitance calculation / allocation unit that calculates the capacitance of the wiring based on the area of the wiring of interest and the length of the circumference of the wiring input by the node information input unit, and allocates the capacitance to the wiring. And a capacitance writing unit that writes the capacitance of the wiring allocated by the capacitance calculating / allocating unit to a corresponding node on the netlist of the wiring.

In a fourteenth aspect of the present invention, the capacity calculation / allocation unit of the thirteenth invention calculates the capacitance value of the wiring of interest, which is input by the allocation method input unit of the twelfth invention, as one ground capacitance. I am trying to do it. The fifteenth invention is the first
The capacity calculating / allocating unit according to the third aspect of the invention divides the capacity value of the wiring of interest, which is input by the allocation method inputting unit according to the twelfth aspect of the invention, into the ground capacity and the adjacent capacity between the adjacent wirings, and calculates the capacity value. I have to. In a sixteenth invention, a capacity calculating / allocating unit according to the thirteenth invention is configured so that a capacity value of a target wiring for carrying out capacity allocation input by the allocation method input unit of the twelfth invention is a capacity between the target wiring and an upper layer wiring. Is calculated as the upper layer capacity. A seventeenth aspect of the present invention is the capacitance calculation / allocation unit according to the sixteenth aspect, wherein the upper layer capacitance is the plate capacitance parameter and fringing based on the positional relationship between the target wiring and the upper layer wiring input by the node information input unit. It is calculated based on the capacity parameter.

The eighteenth invention is a circuit simulation method for obtaining a delay time of signal propagation between an output terminal of a circuit cell in an LSI and a next-stage circuit by referring to information described in a lookup table. Are taking various measures. That is, in the information described in the lookup table, the wiring capacitance element in the capacitive load between the output terminal and the next stage circuit and the gate capacitance element of the next stage circuit are separately described as independent elements, and the above description is made. The delay time of signal propagation between the output terminal and the next stage circuit is calculated based on the determined wiring capacitance element and gate capacitance element. First
According to a ninth aspect of the invention, in the eighteenth aspect of the invention, the wiring capacitance element of the information described in the lookup table is described separately as a resistance component and a capacitance component. In a twentieth aspect of the invention, it is assumed that the resistance component and the capacitance component in the nineteenth aspect of the invention have an inverse proportional relationship, and the relation between the resistance component and the capacitance component is linearly interpolated or regressed to obtain a linear relationship. Is described in the lookup table. A twenty-first aspect of the invention is described by separating the capacitance component in the nineteenth aspect into a fringing effect component and a component other than the fringing effect component, and interpolating or regressing the resistance component and the capacitance component with a curve to form a curve relationship. It is written in the lookup table.

A twenty-second aspect of the invention is a circuit simulator having the following configuration. That is, in the circuit simulator of the twenty-second invention, it is necessary to consider the resistance component in the simulation based on the circuit description input section for inputting the circuit information including the capacitive load between the circuits of the LSI and the input circuit information. It operates when there is no need to consider the resistance component and a load content determination unit that determines whether or not there is,
The delay time of signal propagation between the circuits is calculated with reference to the first lookup table in which the wiring capacitance in the capacitive load between the circuits and the gate capacitance of the next-stage circuit are described separately as independent elements. Which operates when it is necessary to consider the resistance component, the wiring capacitance element in the capacitive load between the circuits and the gate capacitance of the next stage circuit are independent elements, and The wiring capacitance element includes a second circuit delay calculation unit that calculates a delay time of signal propagation between the circuits by referring to a second look-up table that is described by separating the resistance component and the capacitance component. I have it. In a twenty-third aspect of the invention, it is assumed that the second lookup table in the twenty-second aspect of the invention has an inverse proportional relationship between the resistance component and the capacitance component, and the relationship between the resistance component and the capacitance component is expressed as follows. A linear interpolation is used or a linear regression is used to describe the relationship. In a twenty-fourth aspect, the second lookup table in the twenty-second aspect is described by separating the capacitance component into a fringing effect component and a component other than the fringing effect component, and describing the relationship between the resistance component and the capacitance component. Is interpolated or regressed with a curve to have a structure described by a curve relationship.

[0015]

According to the first aspect of the present invention, since the circuit simulation method as described above, R _W calculated by R _W calculation processing, since the characteristics of the delay time of the wiring, such that expressed quantitatively, this The delay time is calculated using R _W and the total wiring length. According to the second invention, the branch destination nodes are clustered by a statistical method using R _W as a statistic.
The delay times to the branch destination nodes belonging to each clustered class are regarded as equal because R _W substantially matches, and the delay times are calculated for the branch destination nodes representing the classes. According to the fourth aspect of the invention, the delay time calculated by the algebraic calculation method to which the Laplace transform is applied has a plus error at the near end portion (the portion where R _W is close to 0) of the wiring,
Since there is a negative error at the far end (the part where R _W is close to 1), this error is corrected based on the total wiring length and R _W. According to the fifth invention, at the time of delay calculated by the algebraic calculation method to which the Laplace transform is applied, the near end portion (R _W
Is close to 0), the positive error (the ratio of the calculated delay time to the true delay time is greater than 1), and the far end (the part where R _W is close to 1) is the negative error (true delay). The ratio of the calculated delay time to the time is smaller than 1), so that the variable amount based on the total wiring length and R _W is used as an explanatory variable element, and the correction amount Y of the equation (3) or (4) is used.
_The delay time calculated by ₁ or Y ₂ is divided to correct the delay time.

According to the sixth aspect of the invention, the average value and the variance value of R _W before and after the modification of the layout are obtained, and whether the hypothesis holds whether the average value and the variance value are the same before and after the modification The standard method is used. And only when it is verified that the mean or variance of R _W is different before and after correction,
Calculate the delay time. According to the seventh invention, before correction
If the latter R _W is a normal distribution, by a statistical method,
Mean normal distribution of unmodified after-R _W, and assayed as follows variance values before after-corrected chi-square distribution, if R _W of the corrected pre-is not a normal distribution, unmodified post- The average value of R _W is tested as t distribution, and the variance before and after correction is tested as F distribution. According to the thirteenth invention, for the wiring of interest designated by the capacitance allocation method, the capacitance between the wiring of interest and the substrate (or lower layer wiring) is calculated as the film thickness or the dielectric constant of the dielectric of the wiring capacitance of the wiring of interest. Input the unit capacitance parameter of the flat plate capacitance and the fringing capacitance parameter determined by the wiring parameter file. Then, the plate capacitance component and the fringing component are obtained from this capacitance parameter. Then, the obtained wiring capacitance is written in the node corresponding to the wiring of interest in the netlist. The circuit simulator performs timing verification according to this netlist.

According to the eighteenth aspect, the wiring capacitance element and the gate capacitance element of the next stage circuit are independent from each other with respect to the capacitive load existing between the output terminal of the circuit cell in the LSI and the next stage circuit. Described in the lookup table.
Therefore, by circuit simulation, for example, the delay time corresponding to the length of the wiring or the number of branch destination nodes is calculated. According to the nineteenth to twenty-first inventions, since the wiring capacitance element in the eighteenth invention is separated into the resistance component and the capacitance component and described in the lookup table, the distribution of the resistance and capacitance components due to the change of the wiring width Circuit simulation can be performed while expressing changes. According to the twenty-second to twenty-fourth aspects, the circuit information is input by the circuit description input unit, and the load content determination unit determines whether it is necessary to consider the resistance component in the simulation. If it is not necessary to consider the resistance component, first
As for the capacitive load between the circuits described in the lookup table of, the wiring capacitance and the gate capacitance of the next stage circuit are used,
The delay time is calculated by the first circuit delay time calculation unit. On the other hand, when it is necessary to consider the resistance component, the second circuit delay time calculation unit calculates the delay time based on the separately described resistance component and capacitance component described in the second lookup table. Is calculated. Therefore, the above problem can be solved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a flow chart showing a circuit simulation method of a first embodiment of the present invention. FIG. 5 is a diagram showing an example of a wiring net for explaining the circuit simulation method of FIG. As shown in this figure, the output terminal (hereinafter referred to as a drive node) N ₁ of the circuit cell 5 has 3
The branch destination nodes N ₁₁ , N ₁₂ , and N ₁₃ are connected.
Active elements (not shown) are connected to the branch destination nodes N ₁₁ , N ₁₂ , and N ₁₃ . Between the drive node N ₁ and the branch destination node N ₁₁ , an RC net having a wiring length l _{1 formed} of a resistor R1, capacitors C1-1, and C1-2, a resistor R2, and a capacitor C2-
1, are connected by an RC net wiring length l ₂ consisting of C2-1. Drive node N ₁ and branch destination node N
_{Between 12} and ₁₂ , there is an RC net having a wiring length l ₁ made up of a resistor R1, capacitors C1-1 and C1-2, and a resistor R3 and capacitors C3-1 and C3-1.
An RC net consisting of C3-1 and having a wiring length l ₃ and a resistor R4
They are connected by an RC net having a wiring length of l ₄ and composed of capacitors C4-1 and C4-2. Between the drive node N ₁ and the branch destination node N ₁₃ , a resistor R1 and capacitors C1-1 and C1 are connected.
Resistance wiring length l ₁ of the RC net consisting -2 R3, capacitor C3-1, resistance RC net wiring length l ₃ consisting of C3-2 R5, capacitor C5-1, wiring length l ₅ consisting of C5-2
It is connected by the RC net.

Here, the RC net refers to a passive wiring portion made of RC having no active element like an inverter, and generally has the following active element at its branch destination node. l ₁ is 1 mm, l ₂ is 1 mm, l ₃ is 7 mm, l ₄ is 1 mm, and l ₅ is 10 mm. The total length I _T of the tree (tree) that constitutes the RC net connected to the drive node N ₁ is 20 mm. The circuit simulation method will be described below with reference to these drawings. In step S11, with respect to the drive node N ₁ of each circuit cell, its l _T and the wiring length l _1k (k = 1, 2, ..., S) from the drive node to each branch destination node N _1k (k = 1, 2, ..., S)
Read 1,2, ..., D) from the pre-layout or post-layout database. In step S12, l _T is compared with the threshold value n. If l _T is n or less, the process proceeds to step S13, and if l _T is larger than n, the process proceeds to step S14. In step S13, for the drive node N ₁ , all branch destination nodes N _1k
One tpd is assigned to This is because l _T is small, and therefore the drive node N ₁ branches to the branch destination node N.
The tpd up to _1k is assumed to be the same. Step S1
4, each branch destination node N _1k of the drive node N ₁
For, the following equation (5), obtaining the R _W (R _W calculation processing).

R _W = l _1k / l _T (5) This R _W is a variable having a value of 0 or more and 1 or less. For example, in the wiring net of FIG. 5, the drive node N ₁
R _W between the branch destination node N ₁₁ and the drive node N ₁
R _W between the branch destination node N ₁₂ and the drive node N ₁
And R _W between the branch destination node N ₁₃ are 0.1,
It becomes 0.45 and 0.9. In step S15, R
Whether treated as random variables _W, to determine the magnitude of the number of nodes s of the node N ₁ of the branch destination node N _1k, when not treat R _W as a random variable with a small the node number s is to step S16 If the number of nodes s is sufficiently large and R _W is treated as a random variable, the process proceeds to step S18. In step S16, the tpd from the drive node N ₁ to the branch destination node N _{1k is} calculated by an algebraic arithmetic method applying the Laplace transform (algebraic arithmetic processing). FIG. 6 is a diagram showing the relationship between the error between R _W and the delay time.

The horizontal axis represents R _W and the vertical axis represents the delay time error err. Here, the error err is the ratio of the calculated tpd and the true pd with no error. That is, when the error err is larger than 1, it represents a positive error, when the error is smaller than 1, it represents a negative error, and when the error err is 1, it represents a true tpd. G ₁ is l _T
The error when = 20, G ₂ is the error err when l _T = 10. As shown in FIG. 6, tpd calculated by the algebraic calculation processing in step S16 is the near end portion (R
_The positive error is large at the left end on the _W axis, and the negative error is large at the far end (right end on the R _W axis). Therefore, step S1
7, the variable amount based on l _T and R _W is used as an explanatory variable element, and the relative error (true tpd) when R _W is small (near end of the wiring net) and large (far end of the wiring net). (The ratio of the calculated tpd to the above) becomes smaller, the tpd calculated in step S16 is divided by the correction value Y ₁ of the equation (3) or the correction value Y ₂ of the equation (4) (delay time correction processing). ). G _{3 in} FIG. 5 is G
₁ is corrected and G ₄ is corrected G ₂ .

As shown in FIG. 6, by the correction by the delay time correction processing, the error of the corrected tpd approaches 1, and
Approaching true tpd. In step S18, seeking R _W of variance V (R _W), the dispersion V (R _w) decide whether it can be regarded as 0 smaller than a predetermined value. Then, R _W is averaged, and there is no variation and dispersion V
If the (R _W) is regarded as 0, the process proceeds to step 19,
If the variance of R _W is large, it is assumed that one R _W cannot represent the tpd of all branch destination nodes, and step S21
Proceed to. In step S19, all tdp branch target node N _1k assumes the same value, the expected value of R _W E (R
The corresponding tdp to _W) is calculated by algebraic calculation method applying the Laplace transform (algebraic calculation process). Step S2
At 0, as in step S17, E (R _W)
From this, tdp is corrected by the equation (2) or (3) (delay time correction processing). In step S21, R _W
It is determined whether or not the distribution is considered to be a discrete type. If it is considered to be a discrete type, the process proceeds to step S22 to perform R _W clustering, and if not, to a step S25. In step S22, R _W is equally clustered (same R _W intervals for clustering). In step S23, the tpd is calculated from the representative R _{W of} each clustered class by an algebraic arithmetic method applying the Laplace transform (algebraic arithmetic processing). In step S24, with respect to the tpd of each class, the tpd is corrected by the representative R _W of each class by the equation (2) or (3) in the same manner as in step S17 (delay time correction process).

In step S25, the branch destination node N
_It is determined whether the _1k distribution is regarded as random. If it is regarded as random, the process proceeds to step S26. If not, the process proceeds to step S29. In step S26, the distribution of R _W is regarded as a normal distribution, and R
_Using the standard deviation σ of _W , clustering is performed so that a large distribution frequency portion has a short R _W interval of the clustering class and a small distribution frequency portion has a long R _W interval. In step S27, the R _W representative of each class that is clustered, obtain the tpd by algebra method applying the Laplace transform (algebraic calculation process). In step S28, for each tpd,
The tpd is corrected according to the equation (3) or (4) using the representative R _W of each class (delay time correction processing). Figure 7
FIG. 6 is a diagram showing a distribution of R _W (the number of branch destination nodes is 41) when it is not regarded as a random distribution. The horizontal axis in the figure is R
_W , the vertical axis represents the number of branch destination nodes. In step S29, assuming that the distribution cannot be regarded as a normal distribution as shown in FIG. 7, clustering is performed for each mountain corresponding to the mountain in the distribution. In step S30, the tpd of R _w representing each clustered class is obtained by an algebraic arithmetic method applying Laplace transform (algebraic arithmetic processing). In step S31, for each tpd, the tpd is corrected by the representative R _W of each class according to the equation (3) or (4) (delay time correction processing). The above processing is performed for the output terminals of all the circuit cells.

As described above, the first embodiment has the following advantages (a) to (j). (A) In timing verification for wiring in an LSI having complicated and diversified branching forms such as in the case of automatic placement and routing of LSI CAD, the position of all nodes in the net is quantitatively determined by R _W. Can be expressed as
The accuracy of calculating d is improved. (B) V, which does not cause a problem of tpd skew between nodes due to wiring resistance (the difference in tpd is small between nodes), like a Steiner tree net for high-accuracy timing control
The (R _W) smaller net, tpd calculation to all the nodes becomes unnecessary, thereby enabling a representative one of tpd corresponding to the load of the net. (C) Since R _W can be regarded as a random variable, statistical evaluation can be performed, and the number of times of tpd calculation can be reduced by quantitative stratification of node groups in the net and tpd calculation for each class. . Then, only when R _W cannot be treated as a random variable, the tpd can be calculated for all the nodes of the net, so that the time for the timing verification can be shortened. (D) By considering clustering evenly with respect to variations in a small number of nodes that do not form a statistical distribution of nets, clustering is evenly performed for each class, and the number of tpd calculations can be reduced. . (E) The number of times tpd is calculated by clustering a net whose distribution of R _W is not random, such as a net controlled by timing by the function of the LSI placement and routing tool. be able to.

(F) With respect to the wiring, the distribution of the wirings to the branch destination node is controlled to be random with respect to the timing.
Clustering based on the standard deviation σ of _W can be performed, and only tpd for each class is calculated, and unnecessary tpd calculation can be omitted. (G) When there is a clear deviation under the control of the placement and routing tool in the distribution of nodes on the net, such as in timing driven placement and routing, for the branch destination node group of the net controlled in timing, Representative tpd
The calculated tpd is allotted, and it becomes possible to omit the tpd calculation for all the branch destination nodes of the unnecessary group. (H) In the circuit simulation by the algebraic calculation method applying the Laplace transform, the calculated tpd is the actual t
to coincide with the pd it is (in one line branch point 0 the central portion) R _W 0.5 Near node group is, it is possible to improve the accuracy of tpd calculated values for other nodes groups . For example, as shown in G3 and G4 of FIG. 6, 70%
Error is improved within 10%. (I) The objective accuracy evaluation of the circuit simulation method is performed by RMS (mean square error), but in the circuit simulation by algebraic calculation processing, the relative error (the calculated delay time with respect to the true tpd) at a small R _W. Ratio)
Is large, and the degree of improvement in the tpd correction of this portion is remarkable in the evaluation by RMS. In the circuit simulation by (j) algebraic calculation processing, the relative error at large at the R _W is smaller than the relative error in R _W is small at the difference between the absolute error (delay time calculated true tpd ) Is a factor of timing verification omission at a submicron class operating frequency (10 MHz or more), and accuracy in LSI timing verification is improved.

Second Embodiment FIG. 8 is a flow chart showing the circuit simulation method of the second embodiment. This circuit simulation method has a function of avoiding recalculation of tpd by statistical evaluation of R _W when the layout of the LSI is modified. The circuit simulation method of the second embodiment will be described below with reference to FIG.

[0027] In R _W input processing step S51, for each drive node from the database, a set of R _W before and after correction of the connected branch destination node to the drive node respectively input (R _W input process). In step S52, to determine whether or not to treat the distribution of R _W as a normal distribution, when dealing with R _W as a normal distribution, the process proceeds to step S53, R
_{If W} is not treated as a normal distribution, step S55
Proceed to. In test process step S53, the average value E (R _W) of R _W, respectively obtained for those before and after correcting the variance V (R _W). In step S54, the average value E before and after correction
(R _W ) follows a normal distribution, and the variance value V (R _W ) follows a χ ² (chi-square) distribution.
(R _W ), V (R _W ) before and after correction can be regarded as different, a null hypothesis is set up, and a population test is performed.
If any one is significant, tpd after layout correction
To calculate step S57, and if neither is significant, the process advances to step S58 to avoid retiming verification. In step S55, R
_W of the average value E (R _W), respectively obtained for those before and after correcting the variance V (R _W) ·. In step S56, the average value E (R _W) of the corrected pre-dispersion values V (R _W) of the t-distribution, also before correction after-as subject to the F distribution, the pre-correction-later E (R _W ), V (with R _W) make a different one and null hypothesis sample test if there was significant even one either, the flow advances to step S57 to calculate the tpd after layout correction, either Is not significant, the process proceeds to step S58 to avoid retiming verification.

In the delay time calculation processing step S57, the corrected tpd is calculated. As described above, the second embodiment has the following advantages (a) to (d). (A) Since the quantitative evaluation variable R _W is introduced for the state of both wirings before and after the LSI layout is corrected, the t after the correction is corrected.
It is possible to determine whether the pd calculation is omitted, and the processing efficiency can be improved. (B) Since it is selected whether or not the distribution of the branch destination nodes of the wiring to be treated is regarded as a population, the determination accuracy in determining the degree of change of the wiring after the layout correction is improved. (C) When considering the distribution of the branch destination nodes of the wiring to be treated as a population, t
It becomes possible to statistically determine whether or not all pd recalculations can be omitted. (D) Even when the distribution of the branch destination nodes of the wiring to be handled cannot be regarded as a population, it is possible to statistically determine whether or not the tpd recalculation to the wiring branch destination nodes after the layout correction can be all omitted.

Third Embodiment FIG. 9 is a diagram showing a circuit simulation method according to a third embodiment of the present invention. In FIG. 9, reference numeral 10 represents a circuit cell which is a basic unit when forming a logic circuit. In the circuit cell 10, 10-A and 10-B are input terminals, and 11 is an output terminal. Reference numeral 12 is an array of delay data for providing a plurality of delay data provided for each output terminal 11. In the array 12, t ₁ , t ₂ , ..., T _n are tpd. Here, the array 12 of delay data is the input terminals 10-A, 10
This is a case where the change in the delay data due to the difference in −B is not considered, and is a one-dimensional array. The size of this array is the sum n of the branch destination nodes to which the output terminal 11 is input, and the contents thereof each have a delay time of t ₁ to t _n . This is a method of providing a plurality of delay data when the number n of pattern blocks forming the layout of an LSI does not increase or when a control system signal for connecting blocks is not output. As described above, since the delay time corresponding to the wiring portion required to improve the accuracy of the timing verification is represented by the terminal of the circuit cell, the wiring is represented as a cell and the logic is “true”. There is an advantage that a wiring cell having data is unnecessary and the load as a circuit simulator does not become heavy even if the accuracy is increased. Further, since a plurality of delay data can be set to the output terminal of the circuit cell, the delay time corresponding to each terminal of the wiring can be provided, and the accuracy of the circuit simulation can be improved.

Fourth Embodiment FIG. 10 is a diagram showing a circuit simulation method according to a fourth embodiment of the present invention, in which elements common to those in FIG. 9 are designated by the same reference numerals. Reference numeral 13 in the figure denotes the arrangement of tpd of the circuit cells 10 in the case where the number n of branch destination nodes having the output terminal 11 as an input in the third embodiment becomes large (for example, when a control system signal is output). Is. In order to accurately represent the signal of the control system driven by the output terminal 11, n
When clustering of R _W is required, the delay data that the array 13 of delay data enters is the delay data t _RW1 , t of each representative of R _W1 , R _W2 , ..., R _Wn of n classes.
It becomes a one-dimensional array having _RW2 ..., _TRWn . As described above, by clustering by R _W ,
Even when it is necessary to handle a large number of terminals and their corresponding delay times such as control signals, the delay data can be compressed.

Fifth Embodiment FIG. 11 is a diagram showing a circuit simulation method according to a fifth embodiment of the present invention. Elements common to those in FIG. 9 are designated by the same reference numerals. Reference numerals 14 and 15 in the drawing are delay data arrays in the case where it is necessary to give the input terminal dependence to the delay data group of the output terminal 11 in the third and fourth embodiments, respectively. A circuit cell 10 including sub-micron class LSIs and the like using input terminals 10-A and 10-B.
There is a case where it is necessary to express the difference in self-delay and the difference in self-delay time depending on how the input signals input to the input terminals 10-A and 10-B are rounded. Both 14 and 15 are a two-dimensional array of the number of delay data of the number of input terminals × the number of output terminals. The data of 14 are the input terminals 10-A, 10- in FIG.
Non-stratified delay data t _{1A to} t respectively corresponding to B
_nA X, t _{1B to} t _nB , and the data of 15 is input terminal 10
-A, 10-B delay data is clustered in the corresponding R _W respectively t _RW1A ~t _RWnA, a t _RW1B ~t _RWnB. As described above, according to the fifth embodiment,
Since the delay data has the dependency on the input terminals 10-A and 10-B, there is an advantage that a more accurate circuit simulation can be performed.

Sixth Embodiment FIG. 12 is a diagram showing a circuit simulation method according to a sixth embodiment of the present invention, in which elements common to those in FIG. 9 are designated by the same reference numerals. Reference numerals 16 and 17 in the figure are delay data arrays in the case where the delay data group of the output terminal 11 needs to have temperature dependence in the fifth embodiment. This newly added dimension contains the delay data of the required temperature levels T _{1 to} T _m , respectively, 16,
17 is a three-dimensional array of the number of temperature levels × the number of input terminals × the number of delay data of output terminals. As described above, according to the sixth embodiment, since the delay data has the temperature dependence, there is an advantage that a more accurate circuit simulation can be performed. Seventh Embodiment FIG. 13 is a diagram showing a circuit simulation method of a seventh embodiment of the present invention. In the seventh embodiment, an array of delay data is provided on the input terminal side. In the figure, 18-A is the number of terminals n connected to the input terminal 10-A.
_{It has A} delay data and 18-B is input terminal 10-B.
It is a one-dimensional array having delay data of the number n _{B of} terminals connected to. Here, there are a plurality of n _A and n _{B in} the case of wired OR, for example. As described above, according to the seventh embodiment, even if the delay data array is provided on the input terminals 10-A and 10-B side, the same advantages as the fourth embodiment are obtained.

Eighth Embodiment FIG. 14 is a block diagram of a circuit simulator showing an eighth embodiment of the present invention. This circuit simulator has a netlist input unit 21, an allocation method input unit 23, and a node information input unit 25. Netlist input unit 21,
A capacity allocation node selection unit 29 is connected to the output sides of the allocation method input unit 23 and the node information input unit 25.
A wiring capacitance parameter selection unit 30 and a PERI division unit 32 are connected to the output side of the capacitance allocation node selection unit 29. Wiring capacity parameter selection unit 30 and PERI division unit 3
The capacity calculation / allocation unit 33 is connected to the output side of 2, and the capacity writing unit 34 is connected to the output side. The circuit simulator execution unit 35 is connected to the output side of the capacitance writing unit 34. Reference numeral 21 is a file that stores a netlist extracted from the layout of the LSI, and is input by the netlist input unit 21. 24
Is a file that stores information in which the user has designated which wiring and the board should be allocated wiring capacity or which wiring capacity should be allocated. The allocation method input unit 23
Is entered by

Reference numeral 26 is a file for storing information indicating the correspondence between the nodes described in the netlist 22 and the wiring. Reference numeral 27 indicates a positional relationship between nodes (for example, when a capacitance is formed between wirings, when a wiring corresponding to a node is a layer on a layout, or when wirings of the same layer form adjacent capacitances). , A node corresponding to the adjacent wiring). Reference numeral 28 is a file that stores the area AREA (cm ² ) of the node and the wiring corresponding to this node, the length (cm) of each side around the node, and the like. 26, 27, 2
8 is input by the node information input unit 25. In order to obtain the wiring capacitance (since the wiring capacitance differs depending on the dielectric constant, the film thickness, etc. of the wiring and the substrate or the interlayer insulating film between the wirings), the capacitance per unit area (F / cm ² ) and a fringing capacitance per unit length (F / cm) are wiring capacitance parameter files. 31 is input by the wiring capacitance parameter selection unit 30.

Next, the operation of the circuit simulator of the eighth embodiment will be described with reference to FIG. The netlist input unit 21 reads the netlist 22 extracted from the LSI layout pattern. Allocation method input unit 23
Then, the capacity allocation method 24 is read, and the wiring to be allocated by the user is input as the wiring of interest. In the node information input unit 25, the correspondence 26 between the node and the wiring,
Information regarding the nodes such as the positional relationship 27 between the nodes and the correspondence relationship 28 between the nodes and the area AREA and the perimeter PERI is read. The capacity allocation node selection unit 29 refers to the correspondence 26 between the node and the wiring, and selects the node corresponding to the wiring of interest from the input netlist 22.
The wiring capacitance parameter selection unit 30 refers to the node-to-wiring correspondence 26 and the positional relationship 27 between the nodes, respectively, to obtain a wiring structure of interest, and to form a wiring capacitance of the wiring of interest from this wiring structure of interest. Cp ^* (F / cm ² )
And the fringing capacitance Cf ^* (F / cm) are selected from the wiring capacitance parameter file 21. FIG. 15 (a),
(B) is a plan view of the layout of the wiring for which wiring capacity is to be allocated. As shown in the figure, the wiring area AR
The EA and its perimeter PERI are stored in 28 in FIG. 14 and are input by the node information input unit 25. The horizontal direction in FIG. 15 represents the width direction of the wiring, and the vertical direction represents the wiring direction. In the PERI dividing unit 32, as shown in FIG. 15B, the peripheral length PERI is referred to by referring to the correspondence relation 28 between the node corresponding to the target wiring and the peripheral length PERI of the target wiring input by the node information input unit 25. Is divided into two components, that is, the length PR1 in the width direction of the wiring and the length PR2 in the wiring direction.

FIG. 16 is a diagram showing a wiring capacity model of the eighth embodiment. As shown in FIG. 16, in this capacity model, capacitance of the wiring 40 by the electric lines of force from the capacitance value Cf ^* flat capacitance C40-1 and the capacitance value Cf ^* wiring length direction of the side surface of the by the bottom of the wiring 40 Fringing capacity C
It is assumed that the ground capacity is constituted by 40-2 and C40-3. In the capacity calculation / allocation unit 33, FIG.
According to the wiring capacitance model shown in 6, the area AREA corresponding to the allocation node, the length PR1 in the wiring direction, and the plate capacitance value C
With reference to p ^* and the fringing capacitance value Cf ^* , the allocated capacity C is calculated from the following equation (6), and the allocated capacity C is used as the ground capacity to allocate the capacity to the wiring of interest. C = AREA * Cp ^* + 2PR2 * Cf ^* = Cp + 2Cf (6) Here, Cp is the plate capacitance value of AREA * Cp ^* , and Cf is the fringing capacitance value of PR2 * Cf ^* .

FIG. 17 is a diagram showing the wiring capacitance of the eighth embodiment. In the figure, reference numeral 41 indicates the wiring of interest, and C41 indicates the allocated capacity. In the capacity writing unit 34, the capacity defined in the node of the netlist corresponding to the wiring to which the capacity is allocated is updated with the allocated capacity C. The circuit simulation execution unit 35 inputs the netlist that reflects the wiring state of the LSI updated by the capacitance writing unit 34, and executes the circuit simulation. As described above, in the eighth embodiment, the allocation method input unit 23
Since the parasitic capacitance allocating method 24 can be selected according to the LSI wiring layout, the capacitance calculating / allocating unit 23 according to this method, the netlist input unit 21, the node information input unit 25, Utilizing various information relating to the LSI layout pattern which cannot be dealt with by the conventional circuit simulator fetched by the wiring parameter selecting unit 30 and the peripheral components PR1 and PR2 of the wiring length divided by the PERI dividing unit 32, The allocated capacity C can be calculated by the equation (6), and all the capacities can be put together as the ground capacity and the capacity can be allocated between the nodes. Therefore, one kind of data, such as the correspondence data 26 between nodes and wirings, the positional relationship 27 between nodes, and the relational data 28 between nodes and AREAs and PERIs, which are possessed for the nodes of the net list of the circuit simulation of the LSI wiring group, can be obtained. Because they are input separately without being collected in the capacity,
It is a circuit simulator that can sufficiently reflect the parasitic capacitance peculiar to LSI wiring. Therefore, it is an effective circuit simulator in the LSI design method of performing timing verification on layout data.

In the netlist 22 extracted from the conventional LSI layout pattern, the extraction range is limited, and in order to easily extract the netlist 22, the elongated wiring is divided into several wirings and the wirings are cut out. The fringing capacitance due to the lines of electric force generated from the two line segments in the wiring width direction on the cut surfaces at both ends of this wiring was estimated. However, since this fringing capacity is not possible originally,
Although there is a problem that the amount of wiring is overestimated by this amount, such a problem is solved by designating the capacitance allocation method with the wiring divided according to the eighth embodiment as one wiring according to the layout, There is an advantage that a highly accurate circuit simulation result can be obtained.

Ninth Embodiment FIG. 18 is a wiring capacitance diagram showing the function of the circuit simulator of the ninth embodiment of the present invention. The ninth embodiment is the eighth
14 is different from the embodiment described above in that the capacity calculation / allocation unit 3 in FIG.
3 is the addition of the function of obtaining the capacitance between adjacent wirings in the same layer. In the figure, 42, 43 and 44 indicate wirings, and C42, C43 and C44 indicate wirings 42, 43 and 4
4, C45 is an adjacent capacitance between the wirings 42 and 43, and C46 is an adjacent capacitance between the wirings 43 and 44.
The operation of the circuit simulator according to the ninth embodiment will be described below. In the capacity calculation / allocation unit 33, the capacity allocation method 24
According to the capacitance between the wiring of interest and the board and the capacitance between the wiring of interest and the adjacent wiring which are designated by the allocation method input unit 23, the ground capacitance C ₁ between the wiring of interest and the board and the adjacent wiring The adjacent capacitance C _{2 of the above} is calculated according to equations (7) and (8), respectively. ^{_{C 1 = Cp * × AREA +}} PR2 × Cf * ··· (7) C 2 = PR2 × Cf * ··· (8) wherein, Cp ^* is a flat plate capacitance between the target wiring and the substrate parameters, AREA is the target wiring , PR2 is the length of the wiring 9 of the target wiring, and Cf ^* is a fringing capacitance parameter. As described above, in the ninth embodiment, as shown in FIG.
As shown in FIG. 7, since the wiring capacitance between the nodes can be allocated in a format in which the ground capacitance is Cp + Cf and the adjacent capacitance is Cf, it is possible to estimate the capacitance between the adjacent wirings, and the adjacent effect becomes remarkable. In the circuit simulation of the coming submicron device, a highly accurate simulation result considering the influence of the parasitic capacitance due to the adjacent wiring can be obtained.

Tenth Embodiment FIG. 19 is a wiring capacitance diagram showing the function of the circuit simulator of the tenth embodiment of the present invention. In the figure, 45 is wiring,
46 is an upper layer wiring of the wiring 45, C46 is a ground capacitance of the wiring 45, and C47 is a wiring capacitance between the wiring 45 and the upper layer wiring 46. The tenth embodiment is different from the eighth embodiment in that the capacity calculating / allocating unit 33 in FIG. 14 is provided with a function for obtaining the wiring capacity between the upper layer and the upper layer. The operation of the circuit simulator of the tenth embodiment will be described below.
In the capacity calculation / allocation unit 33 in FIG. 14, the capacity allocation method 2
4 and the capacitance between the wiring of interest 45 and the substrate and the capacitance between the wiring of interest 45 and the upper layer wiring 46 designated by the allocation method input unit 23, the ground capacitance between the wiring of interest and the substrate and the upper layer wiring are specified. The wiring capacitance between and is calculated by the equation (6). Here, the ground capacitance of the target wiring 45 and the wiring capacitance between the target wiring 45 and the upper layer wiring 46 are assumed to be equal. As described above, in the tenth embodiment, it is possible to estimate the capacitance with the upper layer wiring in addition to the ground capacitance, and the number of wiring layers is increased as the integration degree of the LSI is improved. In the circuit simulator for the multi-layer wiring structure, the upper layer is compared to the case where the capacitance is extracted and assigned by the layout data extracting device or the total capacitance is collectively set to the ground capacitance as in the seventh embodiment. There is an advantage that the potential of the wiring can be reflected and a more accurate simulation result can be obtained.

Eleventh Embodiment FIG. 20 is a wiring capacitance diagram showing the function of the circuit simulator according to the eleventh embodiment of the present invention. Elements common to those in FIG. 19 are designated by the same reference numerals. It is attached. C in FIG.
48 is the ground capacitance of the target wiring 45, and C49 is the target wiring 45.
And the wiring capacitance between the upper layer wiring 46 and the upper layer wiring 46. The eleventh embodiment is different from the tenth embodiment in that the capacitance calculating / allocating unit 33 in FIG. 14 has different wiring capacitances C49 between the ground capacitance C48 of the target wiring 45 and the upper wiring 46. That is, the calculation is performed using a capacity parameter. Less than,
The operation of the circuit simulator of the 11th embodiment will be described. In the capacity calculation / allocation unit 33 in FIG. 14, the capacity between the target wiring 45 designated by the capacity allocation method 24 and input by the allocation method input unit 23 and the board, and the target wiring 45.
According to the designation between the capacitance between the upper wiring and the upper wiring 46, the ground capacitance between the wiring of interest and the substrate and the wiring capacitance between the upper wiring (6)
Are calculated separately by. In FIG. 20, Cpb is the plate capacitance component of the ground capacitance C48, Cfr is the fringing component of C48, Cpt is the plate capacitance component of the capacitance C49 between the upper wirings, and Cfr is the fringing component of C49. As described above, in the eleventh embodiment, the upper layer wiring of the target wiring and the lower layer wiring of the target wiring or the electrodes of the substrate capable of forming a capacitance equivalent to the wiring are positioned symmetrically with respect to the target wiring. Assuming that the ground capacitances are equal to each other, the wiring capacitance between the target wiring and the upper layer wiring and the target wiring and the lower layer wiring are also set according to the eleventh embodiment even when these positions are not symmetrical. It is possible to allocate the capacitance of the wiring of interest to all combinations among the multi-layer wirings by separately obtaining the wiring capacitances such as.

Twelfth Embodiment FIG. 21 is a diagram for explaining the concept of the circuit simulation method of the twelfth embodiment of the present invention. In this embodiment, the LS
It is a circuit simulation method for calculating a delay time between circuits by using a look-up table when performing a circuit simulation in I. In the conventional document 3, the delay time is simply obtained by combining the capacitance value on the capacitance axis C _ax shown in FIG. 4 and the input waveform rounding Sn.
It is assumed that the capacitance value used in the simulation is proportional to the wiring length l _T as shown by the straight line 50 in FIG. That is, the capacitance value used for the simulation is selected regardless of the input gate capacitance of the leaf cell group. However, actually, the capacitive load Cc connected to the circuit cell has a wiring capacitance and a gate capacitance of the next-stage circuit. In the twelfth embodiment, the wiring capacitance value C (l _T ) corresponding to the target wiring length l _T and the fan-out capacitance connected to the wiring, that is, the gate capacitance of the leaf cell group.
F / O is described in the plane lookup table as an independent element. The capacitive load Cc is uniquely determined by the combination of the wiring capacitance value C (l _T ) and the gate capacitance F / O. as a result,
The capacitive load Cc used for circuit simulation is
This corresponds to the non-linearity indicated by the curve 51 in FIG.

For example, 2-input N of the basic gate of ASIC
When calculating the circuit delay time tpd for an average load such as AND (the fanout number is 2 and the wiring length is 2 mm),
The value on the curve 51 is extracted from the lookup table based on the corresponding gate capacitance F / O and the wiring capacitance value C (l _T ). In this case, the value of the area 52 in FIG. 21 is extracted. Also, the wiring length is 10 mm at the output terminal of the circuit cell.
When a circuit delay time tpd is calculated when a long control system wiring such as ˜20 mm is connected and the control system wiring has a fanout of 40 to 60, the area indicated by 53 in FIG. 21 is extracted. Here, in the conventional technique that does not consider the relationship between the wiring capacitance and the gate capacitance, the point on the straight line 50 is extracted, so the difference from the region 53 is ΔF / O. The capacitive load Cc is obtained based on the extracted value, and finally the delay time tpd is expressed by the following equation (9). tpd = f (C (l _T ), F / O, Sn) (9) As described above, in the twelfth embodiment, in the circuit simulation method using the lookup table,
The description for the look-up table is described separately for the gate capacitance F / O and the wiring capacitance value C (l _T ), and the delay time is calculated by the equation (9). On the other hand, in the conventional method shown in Document 3, the delay time tpd is calculated by the following equation (10). tpd = f (Cn, Sn) (10) That is, it becomes possible to express the load of the LSI along more specific items than in the past, and the calculation accuracy of the delay time is improved.

13th Embodiment FIG. 22 is a functional block diagram of a circuit simulator showing a 13th embodiment of the present invention. This circuit simulator includes a circuit description input unit 60 for inputting circuit information including a capacitive load between LSI circuits, and a load content for determining whether or not a resistance component needs to be taken into consideration in the simulation based on the circuit information. And a determination unit 61. First and second circuit delay calculation units 62 and 63 are connected to the output side of the load content determination unit 61. Circuit delay calculation unit 62
Operates when there is no need to consider the resistance component, and the wiring capacitance in the capacitive load between the circuits and the gate capacitance of the next-stage circuit are described as separate elements and described in the twelfth embodiment. Referring to the lookup table 64 of 1,
It has a function of calculating the delay time between each circuit. The circuit delay calculation unit 63 operates when it is necessary to consider the resistance component, and has a function of calculating the delay time between the circuits by referring to the second lookup table 65 different from the lookup table 64. Have The output sides of the circuit delay time calculation units 62 and 63 are connected to the circuit delay output unit 67. The circuit delay output section 67 is configured to output the final delay time.

FIG. 23 is a diagram for explaining the description of the lookup table 65 in FIG. The lookup table 65 includes wiring capacitance elements C in the capacitive load.
(L _T ) and the gate capacitance F / O of the next-stage circuit are independent elements, and the wiring capacitance element C (l _T ) has a resistance component R
It is described separately for * and capacitance component C *. For example,
Three points indicating positions on the total wiring length l _{T are} defined as l _T1 , l _T2 , and l _T3 . The resistance component R * and the capacitance component C * at each position l _T1 , l _T2 , l _T3 correspond to the wiring width, and the resistance component R *
Since the relationship between * and the capacitance component C * is inversely proportional,
The straight lines l _P1 , l _P2 and l _P3 in FIG. 23 are determined corresponding to the respective positions l _T1 , l _T2 and l _T3 . These straight lines l _P1 , l _P2 , l _P3
The points of combination of the resistance component R * and the capacitance component C * corresponding to the wiring width for each of the positions l _T1 , l _T2 , and l _T3 are determined as n _P1 , n _P2 , and n _P3 , respectively. 3 points n _P1 , n _P2 , n
_The line obtained by interpolating or regressing _P3 is the wiring capacitance element C
Used as (l _T ) _P. FIG. 24 is a diagram showing an example of actual wiring. It is assumed that the actual wiring 68 has three types of wiring widths as shown in FIG. If this sheet resistance is R _s and the capacitance per unit area is C _u , then three points l _T1 , l _T2 ,
The resistance component at l _T3 becomes R _s , 2R _s , 4R _s , and the capacitance component becomes 16C _u , 8C _u , 4C _u . These combinations correspond to the points n _P1 , n _P2 , and n _P3 in FIG. 23, respectively. Wiring capacitance element axis C on which points n _P1 , n _P2 , and n _P3 ride
(L _T ) _P is the wiring capacitance axis C in the twelfth embodiment.
It corresponds to (l _T ).

Next, the circuit information including the capacitive load between the circuits of the LSI is input through the circuit description input unit 60 for explaining the operation of the circuit simulator of FIG. The load content determination unit 61 determines, based on the input circuit information, whether or not it is necessary to consider the resistance component in the simulation. As a basis for this determination, it is determined that the resistance component needs to be taken into consideration for a capacitive load having a wiring width that varies depending on the current density, such as a wiring that propagates a control system clock. When it is determined in the circuit simulation that the consideration of the resistance component is unnecessary, the circuit delay calculation unit 62 operates and calculates the delay time tpd between the circuits by referring to the lookup table 64. Equation (9) in the twelfth embodiment is used for this calculation. When it is determined in the circuit simulation that the resistance component needs to be considered, the circuit delay calculation unit 63 operates, the lookup table 65 is referenced based on the wiring width, and the delay time tpd between the circuits is calculated. The following equation (11) is used for this calculation. tpd = f (R *, C *, F / O, Sn) (11) The delay time tpd calculated by the circuit delay calculation units 62 and 63 is output via the circuit delay output unit 67. . As described above, in the thirteenth embodiment, the circuit simulation is performed with reference to the look-up table 65 in which the wiring capacitance element is described by separating the resistance component R * and the capacitance component C *. It is possible to consider the resistance component in the simulation when the wiring width changes according to the current density, such as the wiring that propagates the clock signal of the control system, etc., and the accuracy of the simulation of the propagation delay time improves. . Further, a load content determination unit 61 for determining whether or not the resistance component needs to be considered is provided, and the circuit content delay calculation unit 62 or 6 is determined by the load content determination unit 61.
Since 3 calculates the delay time, it is possible to calculate the delay time when it is not necessary to consider the resistance component R *.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the ninth embodiment, the adjacent capacitance between the wiring of interest and the adjacent wiring is calculated as being equal to the fringing capacitance of the ground capacitance of the wiring of interest, but the sum of the fringing capacitance of the adjacent capacitance and ground capacitance is calculated. May be distributed so that is equal to 2Cf in the equation (6). (2) It is also possible to calculate the capacitance by combining the circuit simulators of the eighth to tenth embodiments. As a result, it is possible to select the total wiring capacity of the wiring of interest as a ground capacitance in the lower layer, or to divide it into adjacent wiring and upper layer wiring for reconfiguration, which causes problems in dynamic operation simulation. The circuit simulator can be easily realized when simulation of noise and increase in wiring delay due to mirror capacitance between wirings is required for simulator accuracy. (3) In the thirteenth embodiment, the relationship between the resistance component R * and the capacitance component C * is assumed to be linear, and the straight line l _P1 , l _P2 , l
_Although represented by _P3 , in the wiring area of a fine LSI, the capacitive component due to the fringing effect cannot be ignored due to the influence of the edges of the wiring pattern. In this case, it is unreasonable to express the relationship between the resistance component R * and the capacitance component C * by a straight line of l _P1 , l _P2 , l _P3 . 25 is a diagram for explaining the fringing effect of the actual wiring of FIG. 24, and FIG. 26 is a diagram for explaining the correction of FIG. Assuming that the capacitance component of the fringing effect per unit length is C _f , as shown in FIG. 25, each capacitance component C * in FIG. 24 has 4C _f corresponding to the positions l _T1 , l _T2 , and l _T3. Each is added. In order to express this result, as shown in FIG. 26, the straight lines l _P1 , l _P2 ,
It is sufficient to replace l _P3 with the curves l _f1 , l _f2 , and l _f3 , respectively. A curve C (l _T ) _f connecting points n _f1 , n _f2 and n _f3 on the curve corresponding to the positions l _T1 , l _T2 and l _T3 on the actual wiring 68 is
This corresponds to the wiring capacitance element axis C (l _T ) _P in FIG.

[0048]

As described above in detail, the first, fourth,
According to the fifth aspect of the invention, since the delay time is calculated using R _W , the delay time can be simulated more accurately. According to the second and third inventions, the branch destination nodes are clustered by R _{W and the} delay time is calculated only for the class representative, so that the processing speed of the circuit simulation is increased. According to the sixth and seventh inventions,
Since the statistical method is used to test the average and variance values of R _W before and after the layout is modified, it is possible to avoid calculating the delay time after modification, which is not always necessary. Is improved. According to the eighth to twelfth inventions, since only the delay data is provided as an array at the output terminal or the input terminal of the cell, it is possible to realize an accurate circuit simulation without increasing the data amount. According to the thirteenth to seventeenth inventions, the capacitance of the wiring of interest is allocated according to the capacitance allocation method, the allocated capacitance is written to the node corresponding to the wiring of interest in the netlist, and the timing verification is performed according to the written capacitance. Therefore, an accurate circuit simulation can be realized.

According to the eighteenth invention, in the circuit simulation method using the lookup table, the description of the lookup table of the capacitive load connected to the circuit cell is separated into the gate capacitance element and the wiring capacitance element. It is described and the delay time is calculated. Therefore, the load on the LSI can be expressed according to more specific items than in the past, and the calculation accuracy of the delay time is improved. Further, it becomes possible to incorporate the load components of the circuits handled at the respective design stages of the layout design and the logic design into one circuit simulation, and in particular, the parasitic load expression considering the wiring parasitic capacitance in the layout of the large chip LSI. Can be improved. According to the nineteenth invention, since the wiring capacitance element of the capacitive load of the circuit cell is further divided into the resistance component and the capacitance component and described in the look-up table, the wiring width like the control system wiring of the LSI can be obtained. Change and there is a bias in the distribution of resistance values on the pattern layout, the parasitic load expression of the wiring portion is improved and L
The expression of the parasitic load of the circuit during SI can be improved.

According to the twentieth invention, it is assumed that the resistance component and the capacitance component in the nineteenth invention have an inverse proportional relation, and the relation between the resistance component and the capacitance component is described in a lookup table in a linear relation. are doing. Therefore, the resistance value can be uniquely associated with the capacitance value determined by the position on the wiring without adding a new look-up table. That is, it is possible to improve the expression of the parasitic load of the circuit wiring portion without increasing the table order. According to the twenty-first aspect, the capacitive component in the nineteenth aspect is described by being divided into a fringing effect component and a component other than the fringing effect component, and the resistance component and the capacitive component are interpolated or regressed by a curve to look for a curve relationship. Since it is described in the up table, the parasitic wiring capacitance based on the fringing effect corresponding to the physical structure (thickness) of the wiring can be incorporated into the parasitic load of the circuit wiring portion in the nineteenth invention, and the expression is further improved. Can be expected. That is, the process structure of the wiring can be reflected in the calculation of the delay time of the circuit including the fine wiring.

According to the twenty-second to twenty-fourth inventions, a load content judgment unit for judging whether or not the resistance element needs to be taken into consideration in the simulation based on the circuit information, and a case where the resistance element does not have to be taken into consideration. First circuit delay calculation that operates and calculates the delay time of signal propagation between circuits by referring to the first lookup table in which the wiring capacitance and the gate capacitance of the next stage are separated and described as independent elements Section and the resistance element are operated, it is described that the wiring capacitance element and the gate capacitance of the next stage circuit are independent elements, and the wiring capacitance element is separated into a resistance component and a capacitance component. Second
The second circuit delay calculating section for calculating the delay time of signal propagation between the respective circuits with reference to the lookup table of (1), the same effects as those of the nineteenth to twenty-first aspects can be expected. In the circuit simulation for the purpose of back annotation after the pattern layout of the LSI circuit, the wiring inside the LSI circuit block and the signal line or the signal line group connected to the logical hierarchical level across the circuit blocks It is possible to perform a simulation without distinguishing between. That is, the simulation procedure can be simplified.

[Brief description of drawings]

FIG. 1 is a flowchart showing a circuit simulation method according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a conventional circuit simulation method.

FIG. 3 is a diagram showing a method of inputting and specifying a capacity of a netlist.

FIG. 4 is a diagram showing a circuit simulation method using a conventional look-up table.

5 is a diagram showing an example of a wiring net for explaining the circuit simulation method of FIG.

FIG. 6 is a diagram showing a relationship between R _W and a delay time error.

FIG. 7 is a diagram showing a distribution of R _W (the number of branch destination nodes is 41) when the distribution is not considered to be random.

FIG. 8 is a flowchart showing a circuit simulation method according to a second embodiment of the present invention.

FIG. 9 is a diagram showing a circuit simulation method according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a circuit simulation method according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a circuit simulation method according to a fifth embodiment of the present invention.

FIG. 12 is a diagram showing a circuit simulation method according to a sixth embodiment of the present invention.

FIG. 13 is a diagram showing a circuit simulation method according to a seventh embodiment of the present invention.

FIG. 14 is a configuration diagram of a circuit simulator according to an eighth embodiment of the present invention.

FIG. 15 is a plan view of a layout of wirings to which wiring capacity is to be allocated.

FIG. 16 is a diagram showing a wiring capacitance model according to an eighth embodiment of the present invention.

FIG. 17 is a diagram showing a wiring capacitance according to an eighth embodiment of the present invention.

FIG. 18 is a wiring capacitance diagram showing the function of the circuit simulator of the ninth embodiment of the present invention.

FIG. 19 is a wiring capacitance diagram showing the function of the circuit simulator of the tenth embodiment of the present invention.

FIG. 20 is a diagram of wiring capacitance showing the function of the circuit simulator of the eleventh embodiment of the present invention.

FIG. 21 is a diagram illustrating a concept of a circuit simulation method according to a twelfth embodiment of the present invention.

FIG. 22 is a functional block diagram of a circuit simulator showing a thirteenth embodiment of the present invention.

23 is a diagram illustrating a description of a lookup table 65 in FIG.

FIG. 24 is a diagram showing an example of actual wiring.

FIG. 25 is a diagram illustrating a fringing effect of the actual wiring of FIG. 24.

FIG. 26 is a diagram illustrating the correction of FIG. 23.

[Explanation of symbols]

10 circuit cell 10-A, 10-B input terminal 11 output terminal 12, 13, 14, 15, 16, 17, 18-A, 18
-B array 21 Netlist input part 22 Netlist 23 Allocation method input part 24 Capacity allocation method 25 Node information input part 26 Correspondence between nodes and wiring 27 Positional relationship between nodes 28 Nodes and AREA, P
Relationship with ERI 29 Capacity allocation selection section 30 Wiring capacity parameter selection section 31 Wiring capacity parameter file 32 PERI division section 33 Capacity calculation / allocation section 34 Capacity writing section 35 Circuit simulation execution section 60 Circuit description input section 61 Load content judgment section 62, 63 1st, 2nd circuit delay calculation part 64, 65 1st, 2nd look-up table 67 circuit delay output part C (lt) wiring capacitance F / O gate capacitance R * resistance component C * capacitance component

Claims (24)

[Claims] 1. A circuit simulation method for calculating an output terminal of a circuit cell and a delay time of signal propagation to a branch destination node connected to the output terminal, wherein the output terminal of the circuit cell is connected to the output terminal. Wiring length to each branch destination node and RC connected to the output terminal
Delay calculating and R _W calculation processing of calculating the ratio R _W of the total length of the tree (tree) constituting the net, the delay time by using the entire length of the R _W and the tree calculated by the R _W calculation processing A circuit simulation method characterized by executing time calculation processing. 2. A circuit simulation method for calculating an output terminal of a circuit cell and a delay time of signal propagation to a branch destination node connected to the output terminal, wherein the output terminal of the circuit cell is connected to the output terminal. The wiring length to each branch destination node and RC connected to the output terminal
And R _W calculation processing of calculating the ratio R _W of the total length of the tree (tree) constituting the net, by statistical techniques the R _W calculated by the R _W calculation processing as statistics, is connected to the output terminal A circuit simulation method, comprising: performing a clustering process for clustering the branch destination nodes, and a delay time calculation process for calculating a delay time to the branch destination node representing each of the clustered classes. 3. A circuit simulation method for calculating a delay time of signal propagation to an output terminal of a circuit cell and a branch destination node connected to the output terminal, wherein the output terminal of the circuit cell is connected to the output terminal. Wiring length to each branch destination node and RC connected to the output terminal
R _W calculation processing for calculating the ratio R _W with the total length of the trees (trees) forming the net, and a first calculation for calculating the delay time corresponding to the total length of the tree when the total length of the tree is smaller than a threshold value. The delay time calculation process and the number of branch destination nodes connected to the output terminal are the R _W
Is a number that cannot be treated as a random variable, the second delay time calculation process for calculating the delay time to each branch destination node, and the average of R _W when the variation of R _W is small A third delay time calculation process for calculating a delay time to be performed, a first clustering process for evenly clustering the branch destination nodes in R _W when the distribution of R _W is a discrete type, and a distribution of R _W R is a random distribution,
_A second clustering process for clustering the branch destination nodes according to the standard deviation of _W ; and if the distribution of R _W is not discrete or random, the branch destination nodes are based on the distribution of each mountain of the distribution of R _W. And a fourth delay time calculation process for calculating the delay time of the representative of each class clustered by the first, second, or third clustering process. Characteristic circuit simulation method. 4. A circuit simulation method for calculating a delay time of signal propagation to an output terminal of a circuit cell and a branch destination node connected to the output terminal, wherein the output terminal of the circuit cell is connected to the output terminal. Wiring length to each branch destination node and RC connected to the output terminal
An R _W calculation process for calculating a ratio R _W with respect to the total length of a tree (tree) forming a net, and a delay time to a branch destination node connected to the output terminal are calculated by an algebraic calculation method applying Laplace transform. A circuit simulation method comprising: executing an algebraic calculation process and a delay time correction process for correcting the delay time calculated by the algebraic calculation process based on the R _W. 5. The delay time correction process is performed when the delay time calculated by the algebraic calculation process is a variable amount based on the total length of the tree and the R _W as an explanatory variable element and the R _W is small. 5. The correction is performed by dividing by the correction value Y ₁ of the equation (1) or the correction value Y ₂ of the equation (2) calculated by the multiple regression equation so that the error when large is small. The described circuit simulation method. _{Y 1 = a 1 + b 1} l T + c 1 / R W ··· (1) Y 2 = a 2 + b 2 (R W -c 2) l T / R W ··· (2) where, a ₁ , B ₁ , c ₁ , a ₂ , b ₂ , c ₂ are parameters, c ₂ is a value greater than 0 and less than 1, and l _T is the total length of the tree. 6. A circuit simulation method for calculating a delay time of signal propagation to an output terminal of a circuit cell and a branch destination node connected to the output terminal, wherein the output terminal is connected to the output terminal of the circuit cell. The ratio R _W of the wiring length up to the branch destination node to the total length of the tree that constitutes the RC net connected to the output terminal
Regarding, regarding R _W input processing for inputting both R _W before and after layout correction, and the respective average values of the R _W before and after correction and the respective variance values of the R _W before and after correction. Correct only when the test results of the test process that tests whether or not the hypothesis of equality holds by a statistical method, and the test result of the test process is that at least one of the mean value and the variance value is different. A circuit simulation method characterized in that a delay time calculation process for calculating a delay time to a branch destination node is executed for a circuit cell of a later layout. Wherein said test process, if R _W is normally distributed after the modified front and the average normal distribution of R _W of the modified front and, the dispersion value of R _W of the corrected front and A normal distribution test process that tests as if it follows a chi-square distribution, and if the R _W before and after the correction is not a normal distribution
7. The circuit simulation according to claim 6, further comprising: a non-normal distribution test process for testing the mean value of R _W after R t distribution and the variance value of R _W before and after correction as F distribution. Method. 8. A circuit simulation method for calculating a signal propagation delay time between an output terminal of a circuit cell and a branch destination node connected to the output terminal, wherein wiring between the output terminal of the circuit cell and the branch destination node is provided. A circuit simulation method, characterized in that delay data of a delay time by a basic gate that outputs only a logical "true" is provided as an array corresponding to an output terminal or an input terminal of the circuit cell. 9. The circuit simulation method according to claim 8, wherein a plurality of the delay data are provided for each output terminal of the circuit cell. 10. A ratio R of an output terminal of the circuit cell, a wiring length to each branch destination node connected to the output terminal, and a total length of a tree forming an RC net connected to the output terminal. 9. The circuit simulation method according to claim 8, wherein the plurality of delay data are provided by clustering the branch destination nodes based on _W. 11. The method according to claim 8, wherein the delay data is made to have a dependency on an input terminal of the circuit cell.
9. The circuit simulation method according to 9 or 10. 12. The circuit simulation method according to claim 8, wherein the delay data is made to have temperature dependence of the circuit cell. 13. A circuit simulator for performing timing verification based on a netlist extracted by a circuit layout, a netlist input unit for inputting the netlist, a node defined by the netlist, and the layout Specify the node information input section that inputs the correspondence relationship with the wiring, the positional relationship between the nodes, the area of the wiring of the node, and the perimeter of the wiring, and which wiring is to be allocated between the board and which wiring A unit area of the target wiring specified by the capacity allocation method based on the allocation method input section for inputting the capacity allocation method, and the positional relationship between the nodes and the wiring input by the node information input section and the positional relationship between the nodes. Input the plate capacitance parameter per unit and the fringing capacitance parameter per unit length from the wiring capacitance parameter file. A wiring capacitance selecting unit, a wiring capacitance parameter selected by the wiring capacitance selecting unit, and a wiring capacitance calculated based on the area of the wiring of interest and the circumference of the wiring input by the node information input unit. A capacity calculating / allocating section for allocating the capacity to the wiring and a capacity writing section for writing the capacity of the wiring allocated by the capacity calculating / allocating section to a corresponding node on the netlist of the wiring. Circuit simulator characterized by. 14. The capacitance calculation / allocation unit is configured to calculate the capacitance value of the wiring of interest, which is input by the allocation method input unit, for performing the capacitance allocation as one ground capacitance. Circuit simulator described. 15. The capacitance calculating / allocating unit divides the capacitance value of the wiring of interest, which is input by the allocation method input unit, for performing the capacitance allocation into a ground capacitance and an adjacent capacitance between adjacent wirings, and calculates the capacitance value. 14. The circuit simulator according to claim 13, wherein: 16. The capacitance calculation / allocation unit is configured to calculate, as an upper layer capacitance, a capacitance between the wiring of interest and an upper layer wiring of the target wiring for performing the capacitance allocation input by the allocation method input unit. Item 13. The circuit simulator according to item 13. 17. The capacitance calculating / allocating unit calculates the upper layer capacitance based on the plate capacitance parameter and the fringing capacitance parameter which are input by the node information input unit and are based on the positional relationship between the target wiring and the upper wiring. The circuit simulator according to claim 16, wherein the circuit simulator is calculated. 18. A circuit simulation method for determining a delay time of signal propagation between an output terminal of a circuit cell in an LSI and a next-stage circuit by referring to information described in a lookup table The information separately describes the wiring capacitance element in the capacitive load between the output terminal and the next stage circuit and the gate capacitance element of the next stage circuit as independent elements, and describes the wiring capacitance element and the gate capacitance element described above. A circuit simulation method, characterized in that a delay time of signal propagation between the output terminal and the next stage circuit is calculated based on the above. 19. The circuit simulation method according to claim 18, wherein, of the information described in the look-up table, the wiring capacitance element is described separately as a resistance component and a capacitance component. 20. It is assumed that the resistance component and the capacitance component have an inverse proportional relationship, and the relationship between the resistance component and the capacitance component is interpolated or regressed by a straight line to obtain the linear relationship in the lookup table. 21. What has been described.
The described circuit simulation method. 21. The fringing effect component and a component other than the fringing effect component are described separately by describing the capacitance component, and the resistance component and the capacitance component are interpolated or regressed with a curve and described in the lookup table in a curve relationship. 20. The circuit simulation method according to claim 19, wherein: 22. A circuit description input section for inputting circuit information including a capacitive load between circuits of an LSI, and based on the inputted circuit information, judges whether or not it is necessary to consider a resistance component in a simulation. A load content determination unit, which operates when there is no need to consider the resistance component, and which is described as the wiring capacitance in the capacitive load between the circuits and the gate capacitance of the next-stage circuit separated as independent elements. A first circuit delay calculation unit for calculating a signal propagation delay time between the circuits by referring to a lookup table; and a capacitive load between the circuits which operates when the resistance component needs to be considered. And the gate capacitance of the next-stage circuit as independent elements, and the wiring capacitance element is referred to as a second look-up table described by separating it into a resistance component and a capacitance component. A circuit simulator comprising: a second circuit delay calculation unit that calculates a delay time of signal propagation between the circuits. 23. The second lookup table is
It is assumed that the resistance component and the capacitance component have an inversely proportional relationship, and the relation between the resistance component and the capacitance component is linearly interpolated or regressed to have a configuration described in a linear relationship. 23. The circuit simulator according to claim 22. 24. The second look-up table is
The capacitance component is described by being divided into a fringing effect component and a component other than the fringing effect component, and the relationship between the resistance component and the capacitance component is interpolated or regressed by a curve to be described as a curve relationship. 23. The circuit simulator according to claim 22.