JPH08161223A - Microcomputer with built-in otp memory for controlling internal combustion engine - Google Patents

Abstract

PURPOSE: To rewrite data (programs) after shipping products and to cope with problems generated after going on the market. CONSTITUTION: An OTP (one time programmable) memory inside this microcomputer is composed of an EPROM 11 and a mask ROM 12 and a data (program) part 11a, a program part 11b and a monitor part 12a are formed in the memory space. The EPROM 11 is provided with bank memories composed of three banks 0, 1 and 2 on the same memory space in the data (program) part 11a. Thus, even after shipping the products, by rewriting the contents of a bank register constituted of one of the cells of the EPROM 11, one of the plural bank memories is successively selected, the rewrite of the contents of the EPROM 11 is made possible and appropriate measures are relatively easily taken even after the products go on the market.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to an OTP for controlling an internal combustion engine.
(One Time Programmable; hereinafter simply referred to as “OTP”) A memory built-in microcomputer, and in particular, an OTP memory built-in microcomputer for internal combustion engine control that enables modification of data (including programs) after product shipment. It is about computers.

[0002]

2. Description of the Related Art In recent years, ECUs for controlling internal combustion engines (Electron
The development period of ic Control Unit: is also becoming very short. That is, it is necessary to complete an internal combustion engine control ECU suitable for the vehicle in accordance with the L / O (Line Off) of the vehicle, and as a harmful effect of this, there is a concern that a defect in the market may occur due to insufficient compliance.

For this reason, recently, a microcomputer with a built-in OTP memory is trying to change the data (including the program) of the ECU at an early stage to cope with a problem in the market. However, the ECU after it was put on the market
In the worst case, the ECU cannot be modified
The whole thing needs to be replaced.

In order to deal with this, a method of storing some kinds of data (programs) in advance and switching the data (programs) by an external switch when a problem occurs in the market can be considered.

As prior art documents related to such an ECU, Japanese Patent Laid-Open Nos. 56-52573 and 58-58 are available.
The one disclosed in Japanese Patent No. 41242 is known. In these cases, the technique of switching data (program) depending on the destination (vehicle type) is shown, and the method of switching a plurality of pre-stored data (program) by an external switch is easy when the above-mentioned trouble occurs. It can be analogized.

[0006]

By the way, it is very difficult to predict in advance the problems that will occur in the market, and it has not been possible to take sufficient measures in advance.

Therefore, the present invention has been made in order to solve such a problem, and it is possible to rewrite the data (program) after the product is shipped and to cope with the problem that occurs after the product is put on the market. It is an object to provide a microcomputer with a built-in OTP memory.

[0008]

A microcomputer with a built-in OTP memory for controlling an internal combustion engine according to the present invention includes a specific register formed by one of the cells of the built-in OTP memory and a part of the memory space of the OTP memory. A plurality of bank memories set in the same memory space, and a logic circuit for sequentially selecting one of the plurality of bank memories based on the contents of the specific register.

[0009]

According to the present invention, a logic circuit is formed on the same memory space which is a part of the memory space of the OTP memory based on the contents of a specific register formed by one of the cells of the OTP memory incorporated in the microcomputer. One of the plurality of bank memories to be set is sequentially selected.

[0010]

EXAMPLES The present invention will be described below based on specific examples.

FIG. 1 is a block diagram showing a memory configuration of an internal combustion engine controlling OTP memory built-in microcomputer according to an embodiment of the present invention.

In FIG. 1, the OTP memory bus-connected to a CPU (not shown) in a microcomputer (hereinafter, simply referred to as "microcomputer") having a built-in OTP memory for controlling an internal combustion engine is an EPROM (Erasable).
Programmable ROM) 11 and mask ROM 12.

In the memory space of the EPROM 11 and the mask ROM 12, a data (program) section 11a as a storage area for storing various data (including programs) using the EPROM 11 and a program section 11b as a storage area for storing a control program. And a monitor section 12a as a storage area for storing the monitor program using the mask ROM 12.

The EPROM 11 has three banks 0, in the same memory space in the data (program) section 11a.
It has a bank memory consisting of 1 and 2. When the program is executed, only one of the banks 0, 1 and 2 exists in the memory space, and it is not necessary to be aware of the bank memory in the program processing.

Next, regarding the selection of the bank memory, FIG.
Will be described with reference to.

As shown in FIG. 2, the bank memory is selected by the bank register 11c formed by one of the cells of the EPROM 11. Bank register 11c
Is valid for the lower 2 bits (bits), and three NAND gates 13 are provided based on the states of bit0 and bit1.
Banks 0, 1, and 2 are selected via the logic circuit 13 including a, 13b, and 13c and one NOT gate 13d.

Here, the initial value of the bank register 11c is 1 for both bit0 and bit1, and the bank 0
Is selected. In addition, bit0 of the bank register 11c
And bit1 are both 1 and only bit0 is 1 → 0
By selecting, bank 1 is selected. Then, from the state of bit0 = 0 and bit1 = 1 of the bank register 11c, bit1 is changed from 1 to 0, that is, bit0 and bit1.
Bank 2 is selected by setting both to 0.

Therefore, when some inconvenience occurs after manufacturing and it is necessary to change (rewrite) the contents of the data (program) portion 11a of the bank 0 which is initially stored, the bits 0 and bi of the bank register 11c are changed.
Data (program) can be written in bank 1 or bank 2 selected by rewriting t1 by overwriting.

The bank register 11c is an EPROM.
Since it is composed of one of 11 cells, each bit (bit) can only be changed from 1 to 0, and the contents of the data (program) unit 11a can be changed (rewritten) up to twice. Writing to the bank register 11c is possible only in the EPROM writing mode.

FIG. 3 is a flow chart showing the processing procedure of EPROM writing in the microcomputer according to the present embodiment.

First, after the write program is loaded in step S101, the process proceeds to step S102, and it is determined whether or not it is the first write. Step S102
The bank 0 is selected in the first write in which the determination condition of is satisfied, the bank register 11c is not accessed, the process proceeds to step S103, the data (program) unit 11a and the program unit 11b are loaded with data, and the EPROM 11 is read. Write to and verify (Veri
In order to confirm whether or not the information stored as fy) is correct, the information is input again by the same means, a comparison check is performed, and then this routine ends.

On the other hand, when the determination condition of step S102 is not satisfied, the process proceeds to step S104 and it is determined whether or not it is the first change. When the determination condition of step S104 is satisfied, the process proceeds to step S105, and bit0 of the bank register 11c is cleared as 1 → 0. Here, when the determination condition of step S104 is not satisfied, the process proceeds to step S106, and it is determined whether or not it is the second change. When the determination condition of step S106 is satisfied, the process proceeds to step S107, and bit1 of the bank register 11c is cleared as 1 → 0. After the processing of step S105 and step S107, the process proceeds to step S108, and the data (program) unit 11a
After the data is loaded into the EPROM 11 and written in the EPROM 11, and verification is performed, this routine is ended. When the determination condition of step S106 is not satisfied, since the change has already been performed twice, rewriting cannot be performed, and thus this routine is ended without doing anything.

This EPROM writing program is loaded into the internal RAM (not shown) of the CPU of the microcomputer by communication from an external tool by the monitor program and executed. The monitor program contains a communication program with an external tool, etc., and is stored in the monitor section 12a of the mask ROM 12 in FIG.

FIG. 4 is a schematic configuration diagram showing an internal combustion engine control ECU constructed by using a microcomputer according to an embodiment of the present invention.

In FIG. 4, 100 is an E for controlling the internal combustion engine.
CU (hereinafter simply referred to as "ECU"), and ECU1
00 mainly comprises a microcomputer 10, a connector 20 for external connection, and a switching circuit 30.

The connector 20 is a communication terminal 2 for communicating with an external tool.
1, a Vpp terminal 22 for supplying the EPROM write voltage Vpp (12 V), and a switching terminal 23 for switching the Vpp terminal voltage of the microcomputer 10. Here, the communication terminal 21 can also be used if the ECU 100 has a communication terminal with a service tool.
The write data is transferred from the external tool to the ECU 100 via. Also, a circuit for generating the EPROM write voltage Vpp can be provided in the ECU 100.
Since it is necessary only when writing to the ROM, it costs less to supply it from the outside through the Vpp terminal 22. Further, by the signal from the switching terminal 23, the microcomputer 1
To the Vpp terminal 10a of 0, 12V is supplied from the switching circuit 30 during EPROM writing, and 5V in other cases.
The switching circuit 30 may be built in the microcomputer 10.

As described above, the microcomputer of this embodiment has a specific register including the bank register 11c formed by one of the cells of the OTP memory including the built-in EPROM 11 and a part of the memory space of the OTP memory. A plurality of bank memories consisting of banks 0, 1 and 2 set in the same memory space consisting of a data (program) section 11a, and one of the plurality of bank memories are sequentially selected based on the contents of the specific register. And a logic circuit 13 that operates.

Therefore, based on the contents of the bank register 11c formed by one of the cells of the EPROM 11 built in the microcomputer 10, the logic circuit 13 comprises the data (program) portion 11a of a part of the memory space of the EPROM 11. One of a plurality of bank memories consisting of banks 0, 1 and 2 set in the same memory space is sequentially selected.

Therefore, even after the product is shipped, the EPROM
By rewriting the contents of the bank register 11c consisting of one of the 11 cells, one of a plurality of bank memories is sequentially selected and the data (program) unit 1 of the EPROM 11 is selected.
The contents of 1a can be rewritten, and even if a problem occurs after the product is put on the market, it can be appropriately dealt with relatively easily.

By the way, the logic circuit 13 of the above embodiment is
It is assumed that the three NAND gates 13a, 13b, 13c and the one NOT gate 13d are used, but the present invention is not limited to this. It suffices if the circuit configuration is such that one can be sequentially selected and can be rewritten to the bank memory.

[0031]

As described above, according to the microcomputer of the present invention, the memory space of the OTP memory is formed by the logic circuit based on the content of the specific register formed by one of the cells of the built-in OTP memory. One of a plurality of bank memories that are set in the same memory space that is a part of the above is sequentially selected. Therefore, even after the product is shipped, by rewriting the contents of the specific register of the OTP memory, one of the plurality of bank memories is sequentially selected.
The contents of the TP memory can be rewritten. This allows
Even if a problem occurs after the product is put on the market, it can be appropriately dealt with relatively easily.

[Brief description of drawings]

FIG. 1 is a block diagram showing a memory configuration in a microcomputer according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing selection of bank memory in a microcomputer according to an embodiment of the present invention.

FIG. 3 is a flowchart showing a processing procedure of a microcomputer according to an embodiment of the present invention.

FIG. 4 is a schematic configuration diagram showing an ECU configured by using a microcomputer according to an embodiment of the present invention.

[Explanation of symbols]

10 Microcomputer (Built-in OTP memory for controlling internal combustion engine) 11 EPROM 11a Data (program) section 11b Program section 11c Bank register 12 Mask ROM 12a Monitor section 13 Logic circuit 100 (for internal combustion engine control) ECU

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location G06F 9/06 540 L 7230-5B

Claims (1)

[Claims] 1. A specific register formed by one of the cells of a built-in OTP memory, a plurality of bank memories set in the same memory space which is a part of the memory space of the OTP memory, and the specific register. And a logic circuit for sequentially selecting one of the plurality of bank memories based on the contents of the above.