JPH081606B2 - Single chip microcomputer - Google Patents

Description

The present invention relates to a single chip microcomputer in which a test mode function and a computer function are integrated on a single semiconductor substrate.

[Conventional technology]

In recent years, due to advances in LSI manufacturing technology, high integration has progressed even in the field of single-chip microcomputers,
The functions integrated on a single semiconductor substrate are becoming more sophisticated. For example, increasing the capacity of the built-in memory and improving the data processing capacity. Along with this, the software that controls single-chip microcomputers has become more sophisticated, and software that brings together the know-how of each company has been built into the chip, but recently there has been the problem of these softwares being stolen. ing. For example,
There were also major social problems such as the program copy of a TV game machine and the creation of pseudo banknotes that abused the control software of a currency exchange machine. Therefore, in order to steal such software, interest and demand for software security have been increasing recently.

Generally, copying of a built-in program of a single-chip microcomputer can be easily performed by using a function of reading a user program and data stored in a built-in memory from an output port (hereinafter, this function is called a test mode function). The above function is originally added to confirm the program and data stored in the built-in memory, and is incorporated in almost all single-chip microcomputers.

FIG. 3 shows a block diagram of a conventional single-chip microcomputer incorporating a test mode function, and the operation will be described below with reference to FIG. In FIG. 3, address bus 1 is a bus for transferring address data. The data bus 2 is a bus for transferring processing data of a central processing unit (hereinafter referred to as CPU). The built-in ROM block 3 is a memory block that stores a program counter, a user program, and data. Generally, ROM has a mask fixed ROM (hereinafter, referred to as mask ROM) and a read-only memory (hereinafter, referred to as PROM) capable of writing data, and the PROM is a UVEPROM that erases data in the memory with ultraviolet rays, In addition, there is an E ² PROM that can electrically write and erase data. The instruction register 4 is a register for storing the instruction code read from the built-in ROM block 3. The CPU control unit 5 is a block that controls the program operation designated by the instruction code stored in the instruction register 4. The accumulator 6 is a register which is the center of data processing. The temporary register 7 is a register for temporarily holding input data to the arithmetic logic operation unit 8. The arithmetic logic operation unit 8 performs a specified arithmetic logic operation on the data stored in the accumulator 6 and the temporary register 7, and outputs the result to the data bus 2. The RAM 9 is a general-purpose register and a readable / writable memory used for storing various processed data, and outputs stored data addressed by the address bus 1 to the data bus 2 or addresses data on the data bus 2. It is stored in the address position of internal RAM 9 specified by bus 1. The port 10 is an output port having a function of outputting the data on the data bus 2 to the outside.

Next, the operation will be described. Built-in in conventional single-chip microcomputer with test mode function
The instruction code at the address designated by the program counter in the ROM block 3 is read from the built-in ROM block 3 and stored in the instruction register 4 via the data bus 2.
The instruction code stored in the instruction register 4 is the CPU control unit 5
Is input to and decoded by hardware such as PLA (Programmable Logic Array) to execute the instruction function. For example, in the case of the binary operation between the accumulator 6 and the general-purpose register, the contents of the general-purpose register are read from the RAM 9 and stored in the temporary register 7. Next, the arithmetic logic operation unit 8 is operated and the operation result is written to the accumulator 8 via the data bus 2 when the destination is the accumulator 8 or to the general purpose register in the RAM 9 when the general purpose register is used. All the above operations are performed in P in the CPU control unit 5.
It is performed by a control signal decoded by hardware such as LA.

Next, the operation of the conventional test mode function will be described with reference to FIG. FIG. 4 shows the built-in structure of FIG.
3 shows a detailed configuration of the ROM block 3. In FIG. 4, the program counter 31 is an address pointer that points to the storage address of the instruction code stored in the built-in ROM (PROM or mask ROM) 32. The built-in ROM 32 is a read-only memory used for storing user programs and data, and the instruction code and data in the memory are output to the data bus 2. When reading data, the program counter 3 does not go through and is directly addressed and read by the address value on the bus 37. The test mode control unit 33 is a block that operates when a signal is output to the test mode request line 36, and controls the operation of the test mode function. The program counter reset line 34 is a signal line for resetting the program counter 31 when the test mode function is executed, and a signal is output from the test mode control unit 33 to the program counter 31. The program counter increment line 35 is a control line for incrementing the program counter 31 when the test mode function is executed, and a signal is output from the test mode control unit 33 to the program counter 31.

When a high voltage is applied to a specific external terminal of a conventional single chip microcomputer, a signal is output to the test mode request line 36 and input to the test mode control unit 33.
The test mode control unit 33 outputs a signal to the program counter reset line 34 immediately after inputting the signal line, and clears the inside of the program counter 31 to Q. Then, the instruction code or data at the address designated by the program counter 31 is read from the built-in ROM 32 and output to the data bus 2, and the data on the data bus 2 is output to the outside via the port 10. After that, the test mode controller
33 outputs a signal to the program counter increment line 35, increments the program counter 31, and outputs the instruction code or data in the internal ROM 32 designated by the program counter 31 to the outside through the port 10. And the following is the same as the program counter increment line
A signal is output to 35, the program counter 31 is sequentially incremented, and the data in the internal memory 32 is sequentially output to the outside via the data bus 2 and the port 10. In this way, the test mode control unit 33 sequentially sends the contents of the built-in ROM 32 in which the user program and data are stored to the data bus 2 and outputs them to the outside via the port 10.

By using the above means, the user applies a high voltage to a specific external terminal of the chip and executes the test mode function to transfer the program and data in the internal ROM 32 to the port 1
It can be read out via 0 and checked.

[Problems to be solved by the invention]

In the above-described single-chip microcomputer having the built-in test mode function, the built-in user program and data can be easily read out by using the test mode function. Even if it is done, a malicious third party can easily read it from the outside, and there is a drawback that the built-in software is not protected at all.

[Means for solving problems]

A single-chip microcomputer according to the present invention comprises, on a single semiconductor substrate, a memory for storing user software, a microprogram memory for storing a microprogram for executing an instruction function, and a process stored in the microprogram memory. An address setting circuit for setting a start address of the routine is provided, and a designating means for storing designation information for designating permission / non-permission of execution of the test mode function is provided and a test mode processing routine is stored in the microprogram memory. And the address setting circuit is configured to set a start address of the test mode processing routine when a test mode is specified, and is stored in the specifying means by execution of the test mode processing routine. The specified information When the designated information specifies execution permission, the test is performed according to the test mode processing routine, and when the designated information specifies execution non-permission, the test execution is prohibited. I am trying.

〔Example〕

Next, one embodiment of a single chip microcomputer according to the present invention will be described with reference to FIGS.

FIG. 1 shows the configuration of a first embodiment of a single-chip microcomputer according to the present invention. First, the components will be described. In Figure 1, the mask
The ROM block 103 and the CPU control unit 105 correspond to the built-in ROM block 3 and the CPU control unit 5 in FIG. Further, the accumulator 6, the temporary register 7, and the arithmetic logic operation unit 8 in FIG. 3 are collectively shown as the execution unit 101 in FIG. In the single-chip microcomputer according to the present invention, the components other than the mask ROM block 103 and the CPU control unit 105 are the same as those of the conventional example shown in FIG.
Only the configuration of the U control unit 105 will be described.

The mask ROM block 103 is the program counter 103-1.
And a program ROM 103-2, and a program counter
Reference numeral 103-1 is an address pointer that points to an instruction code storage address in the mask ROM 103-2. The mask ROM 103-2 is a read-only memory used for storing user programs or data, and the instruction code in the memory is the data bus 2
Is stored in the instruction register 4 via the, and the processing corresponding to each instruction is executed by the CPU control unit 105. When reading data, use the address value on the bus 103-3.
Data in the mask ROM 103-2 is output to the data bus 2 by direct addressing. The CPU control unit 105 is a block that controls instruction execution and test mode function operation, and includes a micro address setting circuit 105-1, a micro program counter 105-2, a micro program ROM 105-3, a decoder 105-4, and a test mode enable. It is composed of a flag 105-5 and a test mode request line 105-6. When the micro address setting circuit 105-1 receives the test mode request signal via the test mode request line 105-6, it sets the test mode processing routine start address in the micro program counter 105-2. Micro program counter 1
Reference numeral 05-2 indicates the address of the microinstruction in the microprogram ROM 105-3 in which the processing corresponding to the instruction is stored by the instruction code fetched in the instruction register 4, and has an increment function. The microprogram ROM 105-3 is a read-only memory that stores control information corresponding to each instruction, and outputs a control signal to each unit via the decoder 105-4. The micro program R-105-3 also includes a test mode processing routine that controls the operation of the test mode function and the permission determination of the test mode function execution. Test mode enable flag 105
-5 is a flag for determining whether the test mode is enabled or disabled. The CPU writes data to and reads data from this flag.
It is performed by the dedicated instruction of. Further, this flag is a semi-fixed flag which is cleared in the initial state and cannot be erased once set.

Next, the operation will be described using the above-mentioned components. Book first
In the single-chip microcomputer of the embodiment, the mask ROM block 103 stores the data of the address designated by the program counter 103-1 in the mask ROM.
It is read from 103-2 and stored in the instruction register 4 via the data bus 2. The instruction code stored in the instruction register 4 is output to the CPU control unit 105, and the test mode request line 10
When the signal is not output to 5-6, it is stored in the micro program counter 105-2 as it is by the micro address setting circuit 105-1 and gives the entry address in the micro program ROM 105-3 for performing the processing corresponding to each instruction. Then, the micro program counter 105-2 is automatically incremented and sequentially points to the addresses in the micro program ROM in which each instruction execution sequence is stored. Next, the signal output from the microprogram ROM 105-3 is decoded by the decoder 105-4, sends a control signal to each unit, and the instruction function is executed.

The above is the instruction execution form of the single-chip microcomputer of the first embodiment. Next, the execution of the test mode function in the first embodiment will be described. When a high voltage is applied to a specific external terminal of this chip, a signal is output to the test mode request line 105-6 and input to the micro address setting circuit 105-1. The micro address setting circuit 105-1 sets the start address of the test mode processing routine in the micro program ROM 105-3 to the micro program counter 105-2, and then the micro program performs permission determination and execution of the test mode function.

Now, in the test mode processing routine in the microprogram ROM 105-3, processing is performed in the following sequence.

: Read the value of the test mode permission flag 105-5.

If the test mode permission flag 105-5 is set at :, it is determined that the test mode function execution is prohibited, and this test mode processing routine enters the infinite loop and does not execute the test mode function.

If the test mode permission flag 105-5 is not set at :, it is determined that the test mode function execution is permitted, and the program counter 103-1 in the mask ROM block 103 is reset.

: The data corresponding to the address designated by the program counter 103-1 is taken out from the mask ROM 103-2 and output to the data bus 2.

: The data on the data bus 2 is output to the execution unit 101, the execution unit 101 performs predetermined data processing such as adding a parity bit and encryption, and outputs the processed data again to the data bus 2.

: Output the data on the data bus 2 to the outside via the port 10.

: Program counter 103-1 value and mask ROM 103-
The final address value of 2 is compared, and if they match, the test mode processing routine enters an infinite loop. If they do not match, move to the next step.

: Increment the program counter 103-1.

: Move to processing step.

The above is the test mode function permission determination and test mode function execution mode using the microprogram.

Although the micro program counter 105-2 addresses the micro program ROM 105-3 in the above embodiment, a method of addressing by the specific field in the micro instruction may be used.

The conventional test mode function is built in by the manufacturer for the purpose of using it during operation inspection during the manufacturing of single-chip microcomputers. Using the above function, the built-in program and data can be read easily, and software protection measures can be taken. Was not done at all. However, in the first embodiment of the present invention, the built-in test mode permission flag 105-5 and the use of the microprogram easily realize the high-level built-in software protection.

As described above, the test mode enable flag 105-5 can be read and written only by the dedicated instruction of the CPU.
It is a semi-fixed flag that cannot be erased once it is set.
Therefore, the manufacturer makes it possible to read the built-in software by the test mode function without setting the above flag during the development and the debug of the software in the mask ROM 103-2. When the product is shipped to the market after the built-in software has been debugged, the test mode enable flag 105
By setting -5 to prohibit the subsequent test mode function execution, the built-in program and data cannot be read. By the above means, it is possible to protect the built-in software with the built-in test mode function.

Further, in the first embodiment, the determination of the test mode permission flag and the execution of the test mode function are realized by the microprogram, so that data processing such as addition of the parity bit and encryption is performed on the built-in program. It is possible to easily improve the certainty and safety of data, and it is very difficult to decipher the above processing sequence, and it is possible to protect the built-in software to a higher degree than execution by a macro program. .

Also, set the test mode enable flag 105-5 to the CPU
Since it is executed by the dedicated instruction, it is absolutely impossible to change the flag value by an external operation, and the above means becomes very safe.

Next, a second embodiment of the single chip microcomputer according to the present invention will be described with reference to FIG. First, the components will be described. PROM block 20 in FIG.
Reference numeral 3 corresponds to the mask ROM block 103 in FIG. 1 showing the configuration of the first embodiment of the single-chip microcomputer according to the present invention, and PROM 203-2 corresponds to the mask ROM 103-2 in FIG. There is. The CPU in Fig. 1
Corresponding to the test mode permission flag 105-5 in the control unit 105, the test mode permission parameter 203-3 is set to P in FIG.
It is assigned to a specific address in ROM203-2,
In the second embodiment, the test mode permission flag 105
-5 does not exist. The components other than the above are the same as those in FIG. Therefore, only the configuration of the PROM block 203 will be described below.

The PROM block 203 includes a program counter 203-1 and a PROM.
It consists of 203-2, the program counter 203-1 is PR
An address pointer that points to the instruction code storage address of the OM203-2. The PROM 203-2 is a programmable read-only memory used for storing user programs or data. The instruction code in the memory is stored in the instruction register 4 via the data bus 2 and the processing corresponding to each instruction is performed by the CPU control unit. Executed by 105. When reading data, the data in the PROM 203-2 is output to the data bus 2 by directly addressing it with the address value on the bus 203-4. The test mode permission parameter 203-3 is a parameter used to determine whether the test mode is permitted or prohibited, and is assigned to the content of a specific address in the PROM 203-2. Data is written to and read from the above parameters using dedicated CPU instructions.

 Next, the operation will be described with reference to FIG.

The operation of the single-chip microcomputer in the second embodiment is similar to that of the first embodiment, and the command function is executed by the microprogram. The test mode function execution form in the above-mentioned components is almost the same as the execution form in the first embodiment. That is, when a high voltage is applied to the specific external terminal of this chip, a signal is output to the test mode request line 105-6 and input to the micro address setting circuit 105-1. The micro address setting circuit 105-1 is the micro program counter 105-2.
The start address of the test mode processing routine in the microprogram ROM 105-3 is set to. After that, permission determination and execution of the test mode function are performed by the microprogram. The contents of the test mode permission parameter 203-3 are checked by the microprogram, and if "Q", the test mode function is executed. However, the test mode permission parameter 203-3 has a value of "Q" in the initial state. When the test mode function is prohibited, data other than "Q" is written to the test mode permission parameter 203-3 by the dedicated instruction of the CPU as in the case of the first embodiment, and thereafter, the program and data in the PROM 203-2 are changed. Prohibit reading.

Further, in the second embodiment, the value of the test mode permission parameter 203-3 can be erased and rewritten. However, when the PROM 203-2 is UVEPROM, the data in the test mode permission parameter 203-3 is changed by ultraviolet rays. There is no problem because other programs and data are also erased by erasing. Further, in the case of E ² PROM, it can be dealt with by prohibiting the writing and writing of data to the test mode permission parameter 203-3 by the built-in program. Therefore, also in the second embodiment, protection of the programs and data in the PROM 203-2 is realized, and the security of the built-in software is enhanced. Also, since the value of the text mode permission parameter 203-3 can be operated only by the instruction of the CPU,
It cannot be changed from the outside, so the above processing sequence is highly secure.

〔The invention's effect〕

As described above, in the single-chip microcomputer according to the present invention, the test mode enable flag (when the built-in program area is the mask ROM) is provided in the CPU control unit in comparison with the conventional single-chip microcomputer having the test mode function. By setting the test mode enable parameter (when the built-in program area is PROM) in the built-in memory or in the built-in memory, these values can be judged by the micro program and the enable / disable of the test mode can be determined. . Therefore, if the test mode function is disabled by setting the test mode enable flag at the time of product shipment or writing data other than "Q" to the test mode enable parameter, the program and data in the internal memory cannot be read out of the chip. It has a great effect on built-in software and data protection.

Further, in the single-chip microcomputer according to the present invention, as described above, the microprogram checks the test mode permission flag or the test mode permission parameter and controls the operation of the test mode function. It's very difficult, for built-in programs and data,
Very high security effect can be obtained.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a first embodiment of a single-chip microcomputer according to the present invention, and FIG. 2 is a second block diagram of a single-chip microcomputer according to the present invention.
FIG. 3 is a block diagram of the embodiment, FIG. 3 is a block diagram of a conventional single-chip microcomputer incorporating a test mode function, and FIG. 4 is a block diagram of the built-in ROM block 3 in FIG. 1 ...... Address bus 2 ...... Data bus 3 ...... Built-in ROM block 4 ...... Instruction register 5 ...... CPU control unit 6 ...... Accumulator 7 ...... Temporary register 8 ...... Arithmetic logic operation unit 9 ...... RAM 10 ...... Port 31 …… Program counter 32 …… Built-in ROM 33 …… Test mode control unit 34 …… Program counter reset line 35 …… Program counter increment line 36 …… Test mode request line 37 …… Bus 101 …… Execution unit 103… ... Mask ROM block 103-1 ... Program counter 103-2 ... Mask ROM 103-3 ... Bus 105 ... CPU control unit 105-1 ... Micro address setting circuit 105-2 ... Micro program counter 105-3 Micro ROM 105-4 Decoder 105-5 Test mode enable flag 105-6 Test mode request line 203 PROM block 203-1 Pro Lamb counter 203-2 ...... PROM 203-3 ...... test mode enable parameter 203-4 ...... bus

 ─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-60-245057 (JP, A) JP-A-59-153240 (JP, A) JP-A-57-182865 (JP, A) JP-A-60- 83157 (JP, A)

Claims (1)

[Claims] 1. A memory for storing user software, a microprogram memory for storing a microprogram for executing an instruction function, and a start address of a processing routine stored in the microprogram memory on a single semiconductor substrate. In a single-chip microcomputer provided with an address setting circuit for setting, a designating means for storing designation information for designating permission / non-permission of test mode function is provided, and a test mode processing routine is provided in the microprogram memory. Further, the address setting circuit is configured to set a start address of the test mode processing routine when a test mode is specified, and the specification information stored in the specifying means by execution of the test mode processing routine. Detected, When the fixed information specifies execution permission, the test is performed according to the test mode processing routine, and when the specified information specifies execution non-permission, the test execution is prohibited. Chip microcomputer.