JPH08154051A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE: To synchronize a phase at all times even when any phase deviation is generated between input data and an internal clock. CONSTITUTION: An internal clock signal 101 is delayed for plural stages by a multistage delay element 1, and one of plural clock signals is selected by a selector 2 based on the count value of an up-down (UD) counter 4 and outputted as a clock signal. A phase detecting part 3 performs control so that the selector 2 can select the clock signal of a phase closest to an external input signal 102 by performing the up counting, down counting and operation stop of the UD counter 4 based on the phase advance and phase delay of this output clock signal and the external input signal 102. At the fall point of a signal 104 in each cycle of the internal clock 101, 1st and 2nd F/F 31 and 32 of the phase detecting part 3 are respectively set and reset and the UD counter 4 is turned to disable state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit for generating a clock signal synchronized with a signal input from the outside.

[0002]

2. Description of the Related Art Generally, a phase locked loop circuit is used to generate an internal clock signal synchronized with an externally input clock signal or a sampling clock synchronized with data for sampling a serial data signal.

FIG. 31 shows an analog PLL (Phase Locked Loop) circuit as a conventional phase locked loop circuit. The voltage controlled oscillator (VCO) 11 generates a clock signal according to the input DC voltage, and the phase comparator 12 causes a data edge which is a change point of a signal input from the outside and an edge of the clock signal generated by the voltage controlled oscillator 11. The signal corresponding to the phase difference of is output. This signal is converted into a DC voltage by the low pass filter 13 and applied to the voltage controlled oscillator 11, and the voltage controlled oscillator 11 generates a clock signal having a frequency such that the input DC voltage becomes "0".

As another conventional digital phase lock circuit, for example, as shown in Japanese Examined Patent Publication (Kokoku) No. 5-88577, a delay circuit for delaying an internal clock in multiple stages and one of a plurality of output signals of this delay circuit are provided. A selector for selecting is provided, the mark signal and the space signal of the NRZ test signal are determined, and N is determined based on the determination result of the NRZ test signal.
A method has been proposed in which after the RZ test signal, the selector fixes and selects one clock signal. Further, another digital system is proposed in, for example, Japanese Patent Publication No. 5-88578.

Further, as another digital system, for example, as shown in Japanese Patent Laid-Open No. 5-91096, a delay circuit for delaying an internal clock in multiple stages and a selector for selecting one of a plurality of output signals of this delay circuit are used. A method of providing a clock signal having the smallest phase difference based on the averaged advance signal or the averaged delayed signal of the phase difference advance signal and the delay signal has been proposed.

[0006]

However, as shown in FIG.
In an analog PLL such as that shown in Fig. 1, the free-running frequency of the voltage controlled oscillator 11 is unstable, and the signal input from the outside is intermittent like a burst signal, and the "signal There is a problem that out of synchronization occurs when "none" or when the same data does not change continuously.

Further, in the circuit as shown in Japanese Patent Publication No. 5-88577, the selector fixedly selects one clock signal based on the determination result of the NRZ test signal after the NRZ test signal. There is a problem that out-of-synchronization occurs when there is a phase shift between the data and the internal clock. Furthermore, JP-A-5-91096
The circuit disclosed in the above publication has a problem that the circuit configuration becomes complicated because an averaged advance signal or an averaged delay signal of the phase difference advance signal and the delay signal is calculated.

In view of the above-mentioned conventional problems, it is an object of the present invention to provide a phase synchronizing circuit capable of always synchronizing the phases even when the phase shift between the input data and the internal clock occurs. It is another object of the present invention to provide a phase locked loop circuit which is inexpensive and can always synchronize the phase regardless of the state of the input signal.

[0009]

In order to achieve the above object, the invention according to claim 1 is a multistage delay element for delaying an internal clock signal in multiple stages and outputting a plurality of clock signals,
A selector for selecting one of a plurality of clock signals delayed by the multistage delay element based on a selection signal, and a phase detecting means for detecting a phase lead and a phase delay of an external input signal with respect to the clock signal selected by the selector. And counting up or down based on the phase lead or phase lag detected by the phase detector, and using the count value as the selection signal so that the selector selects the clock signal of the phase closest to the external input signal. And an up / down counter applied to the selector.

According to a second aspect of the present invention, a multistage delay element that delays an internal clock signal in multiple stages to output a plurality of clock signals, and one of the plurality of clock signals delayed by the multistage delay element is a selection signal. Selector based on the change point, change point detecting means for detecting both rising and falling of the external input signal, and a clock selected by the selector at the change point of the external input signal detected by the changing point detecting means. Phase detection means for detecting the phase lead and phase delay of the external input signal with respect to the signal, and up-counting or down-counting based on the phase lead or phase delay detected by the phase detecting means, and the selector is most effective for the external input signal. The count value is applied to the selector as a selection signal so that a clock signal of a close phase is selected. And having a down-counter.

According to another aspect of the phase detecting means, a first flip-flop for latching the first clock signal selected by the selector at a change point of the external input signal, and a first flip-flop selected by the selector. A delay element that delays the clock signal by one stage, a second flip-flop that latches the second clock signal delayed by the delay element at a change point of the external input signal, and a change point of the external input signal is the first And the change point of the second clock signal, the up / down counter is counted up, and the change point of the external input signal is located between the change points of the first and second clock signals. In this case, the operation of the up / down counter is stopped, and when the change point of the external input signal is delayed from both the change points of the first and second clock signals, And having a means for the-down counter is up-counted.

According to a fourth aspect of the present invention, there is provided a phase detecting means for latching a first clock signal selected by the selector at a change point of an external input signal, and a plurality of delay elements delayed by the multistage delay element. 1 from the clock signal selected by the selector from the clock signal
A second selector for selecting the second clock signal delayed by a stage; a second flip-flop for latching the second clock signal selected by the second selector at a change point of an external input signal; The change point of the input signal is the first
And the change point of the second clock signal, the up / down counter is counted up, and the change point of the external input signal is located between the change points of the first and second clock signals. In this case, the operation of the up / down counter is stopped, and the up / down counter is up-counted when the change point of the external input signal is behind both the change points of the first and second clock signals. It is characterized by

According to a fifth aspect of the present invention, the phase detecting means has a circuit for initializing the first and second flip-flops for each cycle of the internal clock signal.

According to a sixth aspect of the present invention, the change point detecting means removes noise of an external input signal by an RS flip-flop which is set by one level of two input signals and reset by the other level. And

According to a seventh aspect of the present invention, the external input signal is NRZ serial data, and further has a shift register which takes in the NRZ serial data with a clock signal selected by the selector and converts it into parallel data. It is characterized by

According to an eighth aspect of the present invention, a multistage delay element that delays an internal clock signal in multiple stages to output a plurality of clock signals, and one of the plurality of clock signals delayed by the multistage delay element is a selection signal. A selector that selects based on the above, an encoder that generates a plurality of selection signals for the selector to select each clock signal by encoding a plurality of clock signals delayed by the multistage delay element, and a encoder that generates the selection signal Latching means for latching one of the selected selection signals at a change point of the external input signal and applying the latched signal to the selector.

The invention according to claim 9 is characterized by further comprising a delay element for delaying an external input signal and applying it to the latch means for a period longer than an operation delay time of the encoder.

According to a tenth aspect of the present invention, there is further provided a delay element for delaying the clock signal selected by the selector so as to approach the change point of the external input signal.

According to an eleventh aspect of the present invention, a frequency dividing counter for dividing an internal clock signal faster than the external input signal into the same frequency as the external input signal, and a change point interval for detecting an interval between change points of the external input signal. Detecting means, clearing means for clearing the frequency dividing counter when the interval between the changing points detected by the changing point interval detecting means is within a predetermined range, and the interval between the changing points detected by the changing point interval detecting means A sync pull-in state or an out-of-sync state on the basis of whether the value is within or outside a predetermined range, and in the case of the out-of-sync state, there is provided a sync detecting means for prohibiting clearing of the clearing means. .

According to a twelfth aspect of the present invention, there is further provided a shift register for shifting the signal divided by the division counter with an internal clock signal.

The change point interval detecting means according to claim 13 is
It is a counter that counts the interval between the change points of the external input signal with an internal clock signal, and the synchronization detecting means detects whether the synchronization is pulled in or out of synchronization based on the count value of the counter.

[0022]

According to the present invention, the phase lead and the phase lag of the external input signal with respect to the clock signal are detected, and the up-down counter counts up or down based on the phase lead or the phase lag, and the external input Since the clock signal having the phase closest to the signal is selected by the selector, the phase can always be synchronized even when the phase difference between the input data and the internal clock occurs.

According to the fifth aspect of the present invention, the first and second flip-flops are initialized every cycle of the internal clock signal, so that the up / down counter is incremented when the external input signal is disconnected. It is possible to prevent the counting or down-counting operation from being repeated, so that the phase can always be synchronized even when a phase shift occurs between the input data and the internal clock, and the state of the input signal can be reduced with an inexpensive configuration. The phase can always be synchronized regardless of.

According to the sixth aspect of the present invention, the noise of the external input signal is removed and the change point is detected. Therefore, when the NRZ serial data is input as the external input signal, normal sampling can be performed.

According to a seventh aspect of the invention, the shift register uses the clock signal selected by the selector to perform NRZ.
The NRZ serial data can be normally sampled by taking the serial data and converting it into parallel data.

According to the present invention, a plurality of clock signals are encoded to generate a plurality of selection signals for the selector, and the plurality of selection signals are latched at the changing points of the external input signal and applied to the selector. Therefore, the phase can be always synchronized even when the phase shift between the input data and the internal clock occurs, and the phase can always be synchronized regardless of the state of the input signal with an inexpensive configuration. Further, since the delay element takes into consideration the operation delay time of the encoder, it is possible to prevent the loss of synchronization.

According to the eleventh to thirteenth aspects of the present invention, the interval between the changing points of the external input signal is detected, the frequency dividing counter is cleared when the interval between the changing points is within a predetermined range, and the interval between the changing points is determined. If the sync pull-in state or the out-of-sync state is detected based on whether it is within or outside a predetermined range, and the clear means is prohibited from clearing in the out-of-sync state, a phase shift between the input data and the internal clock occurs. Even in the case of doing so, the phase can always be synchronized. Also, when the external input signal is disconnected, the frequency divider counters the free run and maintains the phase before the signal is disconnected, so it is possible to always synchronize the phase regardless of the state of the input signal with an inexpensive configuration. it can.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of the phase locked loop circuit according to the present invention, and FIG. 2 is a block diagram showing in detail an example of the phase locked loop circuit of FIG.

In FIG. 1, the internal clock signal 101 is output from a stable clock generator such as a crystal oscillator (XO), and the multi-stage delay element 1 delays one cycle T into a plurality of stages. One of the plurality of clock signals delayed by each stage by the multi-stage delay element 1 is selected by the selector 2 based on the count value of the up / down (UD) counter 4 and output as a clock signal. The phase detection circuit 3 up-counts, down-counts, and stops the operation of the UD counter 4 based on the phase advance and the phase lag of the output clock signal and the external input signal 102 so that the selector 2 outputs the phase closest to the external input signal 102. Control to select the clock signal.

In FIG. 2, the internal clock signal (= T
0) 101 is delayed by one stage by the multistage delay element (DL) 1 to output signals T1 to T7, for example, 7 stages, and eight signals T0 to T7 are input terminals I0 of the selector 2, respectively.
~ I7 is applied. The internal clock signal 10
When the frequency of 1 is 12.5 MHz, that is, one cycle is 8
In the case of 0 nsec, each delay time of the signals T0 to T7 is 10 nsec.

The selector 2 selects one of the eight signals T0 to T7 as the selection signal of the 3-bit count values QA, QB and QC of the up / down (UD) counter 4, and U
The D counter 4 is octal in this example and operates in binary. The output signal 103 of the selector 2 is used as a clock and is applied to the clock input terminal of the UD counter 4 via the inverter 5, and the D terminal of the first flip-flop (F / F) 31 and the delay element 33 are connected. It is applied to one end. The delay element 33 outputs the signal 103 for 10 ns
The signal 104 delayed by ec is applied to the D terminal of the second F / F 32.

The external input signal 102 is the first and second F /
It is applied to the clock terminals of the F31 and 32, and the Q terminal output Q1 of the first F / F31 and the (/
Q) terminal output (hereinafter "/" is used for inverted signal) is A
The output signal 106 of the AND gate 34 is applied to the ND gate 34, and is applied to the enable terminal (/ E) of the UD counter 4. The (/ Q) terminal output 105 of the first F / F 31 is the up / down terminal U / of the UD counter 4.
Applied to D.

The operation will be described with reference to FIG. First, U
The initial values of the outputs QA, QB, QC of the D counter 4 are "0,
0, 0 ”, and in this case, the selector 2 outputs the signal 103
The signal T0 is selected as. The first F / F 31 latches this signal T0 at the rising edge of the external input signal 102 and outputs Q1 from the Q terminal, and the second F / F 32 outputs the signal 104 obtained by delaying this signal T0 by 10 nsec to the outside. It is latched at the rising edge of the input signal 102 and output from the (/ Q) terminal.

Here, when the signals 103 and 104 are both at the high level at the rising edge P1 of the external input signal 102, that is, when the rising edge P1 is ahead of the rising edges of both the signals 103 and 104, the first F / F3.
Since the (/ Q) terminal output 105 of 1 is "0", the UD counter 4 is set to the up mode. Also, the first F
Q terminal output Q1 of / F31 is "1", second F / F32
(/ Q) terminal output is 0, so UD counter 4
The input signal of the enable terminal (/ E) of is "0",
The UD counter 4 at the falling point N1 of the signal 103
The clock input to the signal rises, the UD counter 4 counts up, and the selector 2 selects the input signal T1 as the next output signal 103.

Therefore, the phase of the output signal 103 approaches that of the external input signal 102, and even then, the next rising P2 of the external input signal 102 is still the signals 103 and 104.
If both of the rising edges of the UD counter 4 are ahead, the UD counter 4 further counts up, and the selector 2 selects the input signal T2 as the next output signal 103.

Next, when the next rising edge P3 of the external input signal 102 is ahead of the signal 103 and behind the signal 104, the enable terminal (/
The input signal of E) becomes "1", the UD counter 4 does not operate, and the selector 2 selects the input signal T2 as the next output signal 103.

Next, when the next rising edge P5 of the external input signal 102 lags behind both the signals 103 and 104, the (/ Q) terminal output 105 of the first F / F 31 becomes "1". Therefore, the UD counter 4 is set to the down mode. Further, the Q terminal output of the first F / F 31 is “0”, and the (/ Q) terminal output of the second F / F 32 is “1”.
Therefore, the input signal of the enable terminal (/ E) of the UD counter 4 becomes "0", the UD counter 4 counts down, and the selector 2 selects the input signal T1 as the next output signal 103.

Therefore, according to this embodiment, the UD counter 4 can be used according to the phase advance of the external input signal 102.
Selects the signal T0-T7 having the closer phase by up-counting or down-counting, so that when the phase shift between the input data and the internal clock occurs, the phase is always kept within the delay time range of the signals T0-T7. Can be synchronized.

FIG. 4 shows a modification of the above embodiment.
In the embodiment shown in FIG. 2, the delay element 33 in the phase detection circuit 3 delays the signal 103 by 10 nsec and outputs the signal 10
4 is generated, but in this modification, the selector 2-2 is used instead of the delay element 33. Delay element 1
a outputs eight signals T1 to T8 (T8 = T0) obtained by delaying one cycle of the internal clock signal (= T0) 101 by 7 stages, and the selector 2-1 is 8 as in the selector 2 shown in FIG.
One of the signals T0 to T7 is selected.

The selector 2-2 uses the same selection signal as the selector 2-1 and the output signal of the selector 2-1 is 10 ns.
It is configured to select one of the eight signals T1 to T8 delayed by ec. With such a configuration, the operation is the same as that of the embodiment shown in FIG. 2, but the selectors 2-1 and 2-2 are used.
Since it can be configured by a digital IC, it can be configured at a much lower cost than when the delay element 33 is used.

In the above two embodiments, the external input signal 102 is intermittent like a burst signal, the serial data signal is "no signal", or the same data does not change continuously. In this case, the UD counter 4 may repeat up-counting or down-counting in that section.

FIG. 5 and FIG. 6 respectively show a phase detector and a timing chart of another modification. First
An F / F 31 and a second F / F 32 each having a set terminal S and a reset terminal R are used, and a rising point detection circuit 8 is added. The rising point detection circuit 8 outputs a signal obtained by delaying the output signal 104 of the delay element 33 by 10 nsec.
And an AND gate 82 that outputs a logical product signal 108 of the output signal of the delay element 81 and the inverted signal of the signal 104,
A set terminal S of the first F / F 31 and the second F / F 32,
The initialization pulse 108 is output to the reset terminal R at the falling point of the signal 104. Other configurations are shown in FIG.
The configuration is the same as that shown in FIG.

Therefore, as shown in FIG. 6, in each cycle of the internal clock 101, the first F / F 31 and the second F / F 32 are set and reset at the falling point of the signal 104, and the output of the AND gate 34. Signal 106
Becomes "1", the UD counter 4 is disabled. The output signal 106 is the external input signal 10
Since the UD counter 4 only counts once for a short time from the rising edge of 2, the UD counter 4 does not operate when the external input signal 102 is cut off or does not change. UD counter 4
Can be prevented from repeating up-counting or down-counting. Therefore, the phases can be almost synchronized regardless of the state of the input signal.

As the clock generator for generating the internal clock signal 101, one having a frequency substantially the same as that of the external input signal 102 is used, and a crystal oscillator (XO) having a small error is desirable. Further, the delay stage of the internal clock signal 101 is not limited to 8 stages, and in the case of 10 stages, the selector 2 has 8 inputs and a decimal BCD counter is used as the UD counter 4. When delaying to 16 stages, the selector 2 uses 16 inputs and the UD counter 4 uses a binary hexadecimal counter. That is, when the internal clock signal 101 is delayed to N stages, the selector 2
Is N input, and the UD counter 4 is N-ary.

By the way, the delay element 33 shown in FIG. 2 determines the range of the phase difference in which the counter 4 does not operate, that is, the range in which it is judged that the counter 4 is pulled in and synchronized, and in the embodiment, it is delayed by one stage. However, if the delay amount is increased, the range of the phase difference in which the counter 4 does not operate increases, and if the delay amount is decreased, the range of the phase difference in which the counter 4 does not operate decreases.

Next, a second embodiment will be described with reference to FIGS. FIG. 7 is a block diagram showing the outline of the second embodiment, and the multistage delay element 1 and the selector 2 are the same as those in the first embodiment. The change point detection circuit 6 detects, for example, a change point of the NRZ signal 102 as an external input signal, and the phase detection circuit 3 detects the phase advance or phase delay of the clock signal selected by the selector 2 at the change point of the external input signal 102. Based on the UD counter 4,
Control is performed so that the clock signal having the phase closest to the external input signal 102 is selected by counting down and stopping the operation. Further, the shift register 7 takes in the NRZ serial data 102 with the clock signal selected by the selector 2 and converts it into parallel data. The operations of the phase detection circuit 3 and the UD counter 4 are slightly different as will be described later.

FIG. 8 is a block diagram showing an example of the circuit of FIG. 7 in detail. The change point detection circuit 6 delays an external input signal 102 such as NRZ data by a delay element 61.
And an EX-O which outputs an exclusive OR signal 107a of the external input signal 102 and the signal delayed by the delay element 61.
This signal 107a is formed by the R gate 62, and the signal 107a shown in FIG.
As shown in, the rising edges K1 and K of the external input signal 102
3 and the rising pulses C1 to C4 at both the falling edges K2 and K4. The signal 107a is applied to the clock input terminal of the UD counter 4 via the inverter 8 and to the clock input terminals of the first and second F / Fs 31 and 32.

Here, unlike the first embodiment, the first F / F 31 is connected to the up / down terminal U / D of the UD counter 4.
Is applied to the enable terminal (/ E), and the (/ Q) terminal output of the first F / F 31 and the Q terminal output Q2 of the second F / F 31 are applied via the AND gate 34. Applied. The external input signal 102 is input to the data terminal D of the shift register 7, and the clock terminal C
The signal 104 delayed by the delay element 33 is input to K. Other configurations are the same as those shown in FIG.

The operation of the second embodiment will be described with reference to FIG. For example, the rising edge K1 of the external input signal 102
At (rising edge of pulse C1), signals 103 and 10
When both 4 are high level, that is, when the rising edge K1 is ahead of the rising edges of both signals 103 and 104, the Q terminal outputs Q1 and Q2 of the first and second F / Fs 31 and 32 are "1, Since it is "1", the UD counter 4 is set to the enable state, and then the UD counter 4 counts down at the falling edge of the pulse C1, so that the selector 2 selects the signal T7 as the next output signal 103.

The shift register 7 operates at the rising edge of the signal 104 (sampling points S1 to S4), takes in the external input signal 102, shifts it, and converts it into parallel data. In this case, the UD counter 4 receives the first and second signals. 2 F / F 3
When the Q terminal outputs Q1 and Q2 of 1 and 32 are "1 and 1", down-counting is performed, when they are "00", up-counting is performed, and when they are "01" and "10", they do not operate.
As shown in FIG. 9, the rising edge K1 of the external input signal 102
And the falling point K2 is the sampling point S1
Although it deviates to 2, at the sampling point S4, it rises K3
Then, the phase is corrected so that the center of fall K4 is reached.

Here, since the change point detection circuit 6 detects the change point of the external input signal 102, when the external input signal 102 has noise or glitch, the output signal 107a thereof is changed as shown in FIG. It will be so disturbed that the data cannot be sampled correctly. 10 and 1
1 shows two modifications of the change point detection circuit 6, and FIG. 12 shows the main signals of each modification.

In the example shown in FIG. 10, the external input signal 102
Is applied to the delay element 63, one input terminal of the AND gate 64 and one inverting input terminal of the AND gate 66,
The signal 160 delayed by the delay element 63 is applied to the other input terminal of the AND gate 64 and the other inverting input terminal of the AND gate 66. The output signal 161 of the AND gate 64 is applied to the set terminal S of the RS flip-flop 65, and the output signal 163 of the AND gate 66 is RS.
When applied to the reset terminal R of the flip-flop 65, the Q terminal output 164 becomes a noise-free signal as shown in FIG. From the Q terminal output 164, the change point is detected by the delay element 67 and the EX-OR gate 68 as shown in FIG.

In the example shown in FIG. 11, the external input signal 102
Is applied to the two-stage delay element 69, one input terminal of the AND gate 64-1 and one inverting input terminal of the AND gate 66-1. The signal 161 delayed by two stages by the delay element 69 is applied to one input terminal of the AND gate 64-2 and one inverting input terminal of the AND gate 66-2, and the signal delayed by one stage by the delay element 69. 160 is applied to the other input terminals of the AND gates 64-1 and 64-2 and the other inverting input terminals of the AND gates 66-1 and 66-2.

Also, the output signal 1 of the AND gate 64-2
72 is a set terminal S of the RS flip-flop 65-2
When the output signal 173 of the AND gate 66-2 is applied to the reset terminal R of the RS flip-flop 65-2, the Q terminal output 174 outputs two stages of the external input signal 102 as shown in FIG. The signal is noise-free delayed by a minute.

The output signal 1 of the AND gate 64-1
62 is a set terminal S of the RS flip-flop 65-1
When the output signal 163 of the AND gate 66-1 is applied to the reset terminal R of the RS flip-flop 65-1, the Q terminal output 164 outputs noise of the external input signal 102 delayed by one stage. There will be no signal. The change point of the external input signal 102 can be detected by the exclusive OR of the Q terminal outputs 174 and 164 (107c in FIG. 12).

In the second embodiment as well, it is needless to say that the clock generator for generating the internal clock signal 101 preferably has a small error such as a crystal oscillator (XO), but the external input signal 102 is also preferable. The same data speed as the NRZ serial data is used. In the above description, N is used as the external input signal 102.
Although the case where RZ serial data is sampled is taken as an example, the internal clock 101 is output as the output signal 103 even when the external input signal 102 has a low frequency such as 1/2 or 1/4 of the internal clock 101 as shown in FIG. It can also be taken out as.

Next, a third embodiment will be described with reference to FIGS. FIG. 14 is a block diagram showing the outline of the second embodiment, and the multistage delay element 1 and the selector 2 are the same as those in the first and second embodiments. The select value setting unit 9 encodes a plurality of clock signals delayed by the multi-stage delay element 1 to generate a plurality of selection signals for the selector 2 to select each clock signal, and one of the plurality of selection signals. Is latched at the change point of the external input signal 102 and applied to the selector 2.

FIG. 15 is a block diagram showing an example of the circuit shown in FIG. 14 in detail, and the select value setting section 9 includes an inverter 4
11, encoder 412, EX-OR gate 413-1
˜413-7, inverters 414-1, 414-2 and data latch 415.

As the encoder 412, for example, a logic IC “SN74148” as shown in FIGS. 18 and 19 is used, and this logic IC and the inverter 411, EX-OR.
Gates 413-1 to 413-7, inverter 414-
As shown in FIG. 16, the outputs A10 and A of the inverters 414-1 and 414-2 are combined depending on the combination of No. 1 and 414-2.
11 and the output A12 of the inverter 411 are configured to obtain a 3-bit selection signal in the sections P0 to P7 in which the internal clock 101 is divided into eight.

The signal T0 is inverted by the inverter 411 and input to the input "0" of the encoder 412, and the signal T1
And T2, signals T2 and T3 to signals T6 and T7, and the signals of the next stage and the EX-OR gate 413, respectively.
Input to each input "1" to "7" of the encoder 412 via -1 to 413-7. 3-bit selection signal A1
0, A11, and A12 are latched by the data latch 415 at the rising edge of the external input signal 102 and applied to the selector 2.

The operation of this embodiment will be described with reference to FIGS. 16 and 17. First, after the signal T0 rises, 1
In the section P0 for 0 nsec, the selection signals A10, A1
1 and A12 are "0, 0, 0", therefore, when the external input signal 102 rises in this section P0, the selection signals A10, A11, and A12 are transmitted to the data latch 41.
The signal T0 is selected because it is latched by 5 and applied to the selector 2. Similarly, when the external input signal 102 rises in the section P1 to P7 within 10 nsec after the rise of the signals T1 to T7, respectively, the signals T1 to T7.
Is selected.

By the way, the above operation is performed by the select value setting unit 9
Although the delay due to the internal logic circuit has been ignored, the delay can be ignored if the internal clock 101 has a low frequency. However, when the frequency of the internal clock 101 is as high as 12.5 MHz, that is, when the sections P0 to P7 are as short as 10 nsec,
The delay of the logic IC "SN74148" is about several tens of nanoseconds, and the high speed logic IC "74F" is used instead.
Even if “148” is used, there is a delay of several nanoseconds, and this delay cannot be ignored.

FIG. 20 shows a circuit corresponding to the case where the internal clock 101 is high speed. The select value setting unit 9 includes the data latches 421 and 422, the delay element 423 and the encoder 4.
22, the delay element 423 applies the signal 452 obtained by delaying the rising J1 of the external input signal 102 to K1 to the data latch 422 as shown in FIG. The output signal 457 of the selector 2 is delayed by the delay element 424.

As shown in FIG. 21, the data latch 421 latches the signals T1 to T7 at the rising edge of the external input signal 102 and outputs eight 4-bit signals U3 to U0.
The encoder 430 outputs the 4-bit signals U3 to U0 to 3
Converted to bit selection signals X2 to X0, and data latch 4
Reference numeral 22 latches the selection signals X2 to X0 with the signal 452 obtained by delaying the external input signal 102 by the delay element 423 and applies it to the selector 2. Here, since the encoder 430 may operate during the delay time of the delay element 423, the delay element 423 whose delay time (section J1-K1 shown in FIG. 22) is longer than the operation delay time of the encoder 430 is selected. To be done.

Further, the delay element 424 connected to the output of the selector 2 is selected to have a delay time of 5 nsec which is half the delay time (10 nsec) per stage of the delay element 1. The purpose is to bring the change point of the output signal 458 of the delay element 424 close to the change point of the external input signal 102, whereas the output signal 457 of the selector 2 is -10 to 0 nsec with respect to the external input signal 102. , The output signal 458 of the delay element 424 is -5 to 5 ns.
The error becomes small as ec. Since this calculation ignores the operation delay and setup time of the selector 2 and the data latch 421, the delay time of the delay element 424 is set according to the actual operation delay.

Also in the third embodiment, similarly, when the external input signal 102 is disconnected or does not change, the signals T1 to T7 are selected based on the selection signal previously latched by the data latch 422. Therefore, the phases can be almost synchronized regardless of the state of the external input signal 102.

Further, in the first and second embodiments, the UD counter 4 counts up or down by one in one cycle of the internal clock 101. Therefore, when the phase of the external input signal 102 is largely deviated in the initial stage. However, in the third embodiment, the signals T0 to T8 generated by the external input signal 102 are encoded and one of the signals T0 to T8 is selected. The time can be shortened.

Next, a fourth embodiment will be described with reference to FIGS. In FIG. 23, the internal clock signal 10
The frequency of 1 is, for example, 8 times the frequency of the external input signal 102, and is divided into 1/8 by the frequency dividing counter 204. The frequency-divided signal 511 is shifted by the shift register 206 with the internal clock signal 101, and the external input signal 1
02 is output as a clock signal 512 having the same frequency as 02.

The change point detection circuit 201 uses the external input signal 10
The rising edge is detected as the second change point, and the change point detection pulse 503 is detected. The length counter 202 detects the interval of the change point detection pulse 503, and the control circuit 203 initializes the frequency division counter 204 by generating a clear pulse 508 when this interval is within a predetermined range. Also,
The synchronization detection circuit 205 outputs to the control circuit 203 a signal 506 indicating a synchronization pull-in state or an out-of-synchronization state based on whether or not the interval between the change point detection pulses 503 is within a predetermined range, and a clear pulse in the out-of-synchronization state. Do not generate 508.

FIG. 24 shows a change point detection circuit 20 shown in FIG.
1, the length counter 202 and the control circuit 203 are shown in detail, and FIG. 25 shows the phase synchronization detection circuit 205 shown in FIG. 23 in detail. In FIG. 24, a change point detection circuit 201
Is composed of two-stage flip-flops 211 and 212 and a NAND gate 213, detects a rising edge of the external input signal 102, and outputs a change point detection pulse 503 which is at a low level during one cycle of the internal clock signal 101.

The length counter 202 is a synchronous clear type binary counter, for example, "74HC163" is used, and count operation is performed at the rising edge of the internal clock signal 101 input to the clock terminal CK to output terminals QA, QB, QC. Output a 3-bit count value from
In addition, the change point detection pulse 50 input to the clear terminal CL
Even when 3 is low level, the initialization operation is performed at the rising edge of the internal clock signal 101. Note that the numerical load function is not used, and the load terminal LD is pulled up by the power supply.

In the control circuit 203, the gate 231
The count value “0” of the length counter 202 is detected by, and the count values “6” and “7” of the length counter 202 are detected by the gate 232. OR gate 234
Performs its synthesis, and therefore its output signal 504 has a count value of the length counter 202 of “0”, “6”,
When it is "7", it becomes high level, and other values "1" to "5"
At low level.

This signal 504 and the change point detection pulse 50
The signal obtained by inverting 3 by the inverter 234 is applied to the AND gate 235, and the output signal of the AND gate 235 is applied to the data terminal D of the F / F 236. F / F2
36 operates by the clock signal obtained by inverting the internal clock signal 101 by the inverter 237 and outputs the Q terminal output 505 to the synchronization detection circuit 205. Also, this signal 505
And the phase detection signal 506 from the synchronization detection circuit 205 is NA
The clear pulse 508 is output to the frequency dividing counter 204 via the ND gate 238.

The operation will be described with reference to FIG. 26. The count value of the length counter 202 is "0", "6", "7".
26A, the output signal 504 of the OR gate 233 becomes high level, and when the change point detection pulse 503 becomes low level during this period, the F / F 236 operates at the next rising point K1 of the internal clock signal 101. However, since the D input is high level, the Q terminal output 505 becomes high level. Further, in this case, the synchronization detection circuit 20
When the detection signal 506 from 5 is at a high level, a low level clear pulse 508 is output.

On the other hand, when the count value of the length counter 202 is another value "1" to "5", for example, FIG.
As shown in (4), the change point detection pulse 503 is at a low level when it is "4", but at the next rising point K2 of the internal clock signal 101, the output signal 504 of the OR gate 233 is at a low level, so that the Q of the F / F 236 is The terminal output 505 remains low level, and the low-level clear pulse 508 is not output.

Next, referring to FIG. 25, the synchronization detection circuit 20
5, the circuit 205 has three F / Fs.
251 to 253 and four gates 254 to 257. The change point detection pulse 503 is applied to the clock terminals of the F / Fs 251 to 253, and the F / Fs 251 to 253 operate at the rising edge of the change point detection pulse 503. Further, the signal 505 from the control circuit 203 and the Q output 551 of the F / F 251
Is high level, the output signal 553 of the AND gate 254 becomes high level. Further, the signal 505 from the control circuit 203, the Q output 551 of the F / F 251 and the F / F
Gate 2 when the Q outputs 552 of 252 are both low level
The output signal 555 of 57 goes low.

Further, the output signal 55 of the AND gate 254
3 is at a high level and the Q output (phase detection signal) 506 of the F / F 253 is at a high level, the output signal of the OR gate 255 becomes a high level, and further, the output signal of the OR gate 255 and the output signal of the gate 257. When both 555 are high level, the output signal 556 of the AND gate 256 becomes high level. F / F 253 is a change point detection pulse 503
The output signal 556 of the AND gate 256 is output as the phase detection signal 506 at the rising edge of.

Referring to FIG. 27, this synchronization detection circuit 205
Will be described. When the count value of the length counter 202 that detects the rising point interval of the external input signal 102 is “0”, “6”, or “7”, the control circuit 20
The signal 505 input from 5 becomes a high pulse, the output signal 506 of the synchronization detection circuit 205 becomes a high level when the high pulse continues twice, and the output signal 506 becomes a low level when the state without the high pulse continues three times. . When the output signal 506 becomes low level, the signal 508 in the control circuit 203 does not become low level. Therefore, when the output signal 506 of the synchronization detection circuit 205 is high level, the synchronization pull-in state is set, and when it is low level, the synchronization loss state is set.

FIG. 28 shows the length counter 20 due to noise.
The figure shows a case where the count value of 2 goes out of the set range and the state shifts from the synchronization pull-in state to the synchronization loss state three times in a row. Here, since the shift register 206 is composed of three stages and operates at the rising edge of the internal clock signal 101, its output 512 is the output 51 of the frequency division counter 204.
The internal clock signal 101 is delayed by 2.5 from 1 so that the output 512 of the shift register 206 approaches the changing point of the external input signal 102 by this configuration.

FIG. 29 shows a case in which the state where the count number of the length counter 202 is within the set range shifts from the out-of-sync state to the synchronous pull-in state twice in succession. Since the state shifts to the synchronous pull-in state after two consecutive times in this way, when there is noise such that the count number of the length counter 202 falls within the set range in the external input signal 102 in the non-synchronized state, the frequency division counter is present. 204 is not cleared.

FIG. 30 shows a case where the external input signal 102 becomes a burst signal, and when the signal is disconnected, the clear pulse 50
Since 8 is not output, the frequency division counter 204 is free-running and the phase before the signal interruption is maintained. Therefore, also in the fourth embodiment, similarly, a signal input from the outside is intermittent like a burst signal, or when there is no signal in the serial data signal or the same data does not continuously change. Even in this case, the phases can always be synchronized.

In the fourth embodiment, the frequency of the internal clock signal 101 and the frequency division ratio of the frequency division counter 204 are not limited to the above numerical values, and the count value of the length counter 202 is "0". , "6", "7".

Here, when the frequency of the external input signal 102 is 1/16 of the internal clock signal 101, the count value of the length counter 202 is "0" after it makes one round idle.
When it is "6" or "7", it is determined to be in the synchronization range, so that the phases can be synchronized. That is, the shift register 20
If the frequency of the output 512 of 6 is N, its input 511
The frequency is synchronized with N / 2. Similarly, N / 3, N / 4
Can be synchronized with.

[0084]

As described above, according to the first to fourth aspects of the invention, the phase lead and the phase lag of the external input signal with respect to the clock signal are detected, and the up / down counter counts up based on the phase lead or the phase lag. Alternatively, the counter is down-counted and the clock signal having the phase closest to the external input signal is selected by the selector, so that the phase can be always synchronized even when the phase shift between the input data and the internal clock occurs.

According to the fifth aspect of the invention, the first and second flip-flops are initialized every cycle of the internal clock signal, so that the up / down counter is incremented when the external input signal is disconnected. It is possible to prevent the counting or down-counting operation from being repeated, so that the phase can always be synchronized even when a phase shift occurs between the input data and the internal clock, and the state of the input signal can be reduced with an inexpensive configuration. The phase can always be synchronized regardless of.

According to the sixth aspect of the present invention, the noise of the external input signal is removed and the change point is detected. Therefore, when the NRZ serial data is input as the external input signal, normal sampling can be performed.

According to the seventh aspect of the present invention, the clock signal selected by the selector is used for the NRZ by the shift register.
The NRZ serial data can be normally sampled by taking the serial data and converting it into parallel data.

According to the present invention, the plurality of clock signals are encoded to generate the plurality of selection signals of the selector, and one of the plurality of selection signals is latched at the change point of the external input signal to the selector. Is applied,
Even if a phase shift occurs between the input data and the internal clock, the phase can always be synchronized, and the phase can always be synchronized regardless of the state of the input signal with an inexpensive configuration. Further, since the delay element takes into consideration the operation delay time of the encoder, it is possible to prevent the loss of synchronization.

According to the eleventh to thirteenth aspects of the present invention, the interval between the changing points of the external input signal is detected, the frequency dividing counter is cleared when the interval between the changing points is within a predetermined range, and the interval between the changing points is determined. If the sync pull-in state or the out-of-sync state is detected based on whether it is within or outside a predetermined range, and the clear means is prohibited from clearing in the out-of-sync state, a phase shift between the input data and the internal clock occurs. Even in the case of doing so, the phase can always be synchronized. Also, when the external input signal is disconnected, the frequency divider counters the free run and maintains the phase before the signal is disconnected, so it is possible to always synchronize the phase regardless of the state of the input signal with an inexpensive configuration. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a phase locked loop circuit according to the present invention.

FIG. 2 is a block diagram showing in detail an example of the phase locked loop circuit of FIG.

FIG. 3 is a timing chart showing main signals of the phase locked loop circuit of FIG.

FIG. 4 is a block diagram showing a modification of the phase locked loop circuit of FIG.

5 is a block diagram showing a main part of another modification of the phase locked loop circuit of FIG.

6 is a timing chart showing main signals of the phase locked loop circuit of FIG.

FIG. 7 is a block diagram showing a phase locked loop circuit according to a second embodiment.

FIG. 8 is a block diagram showing in detail an example of the phase locked loop circuit of FIG. 7.

9 is a timing chart showing main signals of the phase locked loop circuit of FIG.

10 is a block diagram showing a modification of the change point detection circuit of FIG.

11 is a block diagram showing another modification of the change point detection circuit of FIG.

12 is a timing chart showing main signals of the circuits of FIGS. 10 and 11. FIG.

FIG. 13 is a timing chart showing main signals of a modification of the second embodiment.

FIG. 14 is a block diagram showing a phase locked loop circuit according to a third embodiment.

15 is a block diagram showing an example of the phase locked loop circuit of FIG. 14 in detail.

16 is an explanatory diagram showing the logic of the encoder of FIG. 15. FIG.

17 is a timing chart showing main signals of the circuit of FIG.

18 is an explanatory diagram showing the encoder of FIG. 15. FIG.

19 is a logic circuit diagram showing the encoder of FIG. 18. FIG.

20 is a block diagram showing a modification of the phase locked loop circuit of FIG.

21 is an explanatory diagram showing the logic of the encoder of FIG. 21. FIG.

22 is a timing chart showing main signals of the circuit of FIG. 21. FIG.

FIG. 23 is a block diagram showing a phase locked loop circuit according to a fourth embodiment.

FIG. 24 is a block diagram showing in detail the change point detection circuit, length counter, and control circuit of FIG. 23.

FIG. 25 is a block diagram showing in detail the phase synchronization detection circuit of FIG. 23.

FIG. 26 is a timing chart showing main signals of the circuit of FIG. 24.

FIG. 27 is a timing chart showing main signals of the circuit of FIG. 25.

FIG. 28 is a timing chart showing main signals in the case of shifting from the sync pull-in state to the sync loss state in the fourth embodiment.

FIG. 29 is a timing chart showing main signals in the case of shifting from the out-of-sync state to the synchronous pull-in state in the fourth example.

FIG. 30 is a timing chart showing main signals when the external input signal is disconnected in the fourth embodiment.

FIG. 31 is a block diagram showing a conventional phase locked loop circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 multi-stage delay element 2,2-1,2-2 selector 3 phase detection circuit 4 up-down (UD) counter 6 change point detection circuit 7 shift register 8 rising point detection circuit 9 select value setting unit 31, 32, 65, 65 -1,65-2 Flip-flop (F / F) 32 AND gate 33,63,69,423 Delay element (DL) 412,430 Encoder 415,421,444 Data latch 201 Change point detection circuit 202 Length counter 203 Control Circuit 204 Dividing counter 205 Synchronous detection circuit 206 Shift register

Claims (13)

[Claims] 1. A multi-stage delay element that delays an internal clock signal in multiple stages to output a plurality of clock signals, and a selector that selects one of the plurality of clock signals delayed by the multi-stage delay element based on a selection signal. A phase detecting means for detecting a phase lead or a phase lag of the external input signal with respect to the clock signal selected by the selector, and up-counting or down-counting based on the phase lead or the phase lag detected by the phase detecting means. A phase synchronization circuit having an up-down counter for applying a count value to the selector as a selection signal so that the selector selects a clock signal having a phase closest to an external input signal. 2. A multistage delay element for delaying an internal clock signal in multiple stages to output a plurality of clock signals, and a selector for selecting one of the plurality of clock signals delayed by the multistage delay element based on a selection signal. A change point detecting means for detecting both rising and falling edges of the external input signal, and an external input signal for the clock signal selected by the selector at the changing point of the external input signal detected by the changing point detecting means. Phase detection means for detecting phase advance and phase delay, and up-count or down-count based on the phase advance or phase delay detected by the phase detection means, the selector outputs a clock signal of the phase closest to the external input signal. An up-down counter for applying a count value as a selection signal to the selector so as to select Phase synchronization circuit having. 3. The first phase detection means latches a first clock signal selected by the selector at a change point of an external input signal, and a first clock signal selected by the selector. 1
A delay element for delaying by a stage, a second flip-flop for latching the second clock signal delayed by the delay element at a change point of the external input signal, and a change point of the external input signal for the first and second The up-down counter is up-counted when it is ahead of both the change points of the clock signal, and the up-counter is up when the change point of the external input signal is located between the change points of the first and second clock signals. Means for stopping the operation of the down counter and up-counting the up-down counter when the change point of the external input signal is behind both the change points of the first and second clock signals. The phase-locked loop circuit according to claim 1. 4. The phase detection means includes a first flip-flop that latches the first clock signal selected by the selector at a change point of an external input signal, and a plurality of clocks delayed by the multistage delay element. A second selector for selecting a second clock signal delayed from the signal by one stage from the clock signal selected by the selector; and a second clock signal selected by the second selector as an external input signal. A second flip-flop that latches at the change point and an up-down counter that counts up when the change point of the external input signal is ahead of both the change points of the first and second clock signals. Deactivating the up / down counter when a signal change point is located between the change points of the first and second clock signals, 3. The phase according to claim 1, further comprising: means for up-counting the up-down counter when the change point of the input signal of the second section is delayed from both the change points of the first and second clock signals. Synchronous circuit. 5. The phase detecting means has a circuit for initializing the first and second flip-flops for each cycle of an internal clock signal.
The phase synchronization circuit described. 6. The change point detecting means removes noise of an external input signal by an RS flip-flop that is set by one level of two input signals and reset by the other level. The phase locked loop circuit according to any one of claims 2 to 5. 7. The external input signal is NRZ serial data, and further comprises a shift register for taking in the NRZ serial data with a clock signal selected by the selector and converting it into parallel data. 7. The phase locked loop circuit according to any one of items 2 to 6. 8. A multi-stage delay element that delays an internal clock signal in multiple stages to output a plurality of clock signals, and a selector that selects one of the plurality of clock signals delayed by the multi-stage delay element based on a selection signal. An encoder that generates a plurality of selection signals for the selector to select each clock signal by encoding a plurality of clock signals delayed by the multistage delay element; and a plurality of selection signals generated by the encoder. Latching means for latching one of the two at a change point of an external input signal and applying it to the selector. 9. The phase locked loop circuit according to claim 8, further comprising a delay element for delaying an external input signal and applying it to the latch means for a time longer than an operation delay time of the encoder. 10. A delay element for delaying the clock signal selected by the selector so as to approach the change point of the external input signal.
The phase synchronization circuit described. 11. A frequency dividing counter for dividing an internal clock signal, which is faster than an external input signal, into the same frequency as the external input signal, change point interval detecting means for detecting an interval between change points of the external input signal, and the change. Clearing means for clearing the frequency division counter when the interval between the changing points detected by the point interval detecting means is within a predetermined range, and whether the interval between the changing points detected by the changing point interval detecting means is within a predetermined range. Alternatively, a phase synchronization circuit having a synchronization detection means for detecting whether the synchronization pull-in state or the out-of-synchronization state is detected based on whether or not there is, and for inhibiting the clearing means from clearing in the case of the out-of-sync state. 12. The phase locked loop circuit according to claim 11, further comprising a shift register that shifts the signal divided by the divider counter with an internal clock signal. 13. The change point interval detection means is a counter for counting the change point interval of an external input signal by an internal clock signal, and the synchronization detection means is in a synchronous pull-in state based on the count value of the counter, or 13. The phase locked loop circuit according to claim 11, wherein the phase locked loop circuit detects whether it is out of synchronization.