JPH08148659A - Manufacture of soi substrate - Google Patents

Abstract

PURPOSE: To form the final Si-Ge, Si-C, or Si active layer, which has an equal thickness with small dispersion (TTV) and besides has small surface roughness, on an insulating layer, and also, to reduce the probability of void occurrence at the lamination face. CONSTITUTION: An Si buffer layer 12 less than 1×10<18> /cm<3> in impurity concentration is made on the first Si substrate 1 containing As or Sb by 1×10<18> /cm<3> or more, and a compound semiconductor layer 13 consisting of Si and Ge, or Si and C is made on this Si buffer layer 12, and an insulating layer 16 is made on this compound semiconductor layer 13. Next, the main face of a support substrate 17 is stuck together to the insulating layer 16, and a great part of the first Si substrate 1 is removed to make it into an Si film 11a 5μm or under in thickness, and this Si film 11a is removed in the first chemical etchant, and then the Si buffer layer 12 is removed in the second chemical etchant, leaving the insulating layer 16 and the compound semiconductor layer 13 on the main face of the support substrate 17.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a Si on SiO ₂ insulation layer
-Ge, Si-C or SOI forming an active layer of Si
(Silicon-On-Insulator) Substrate manufacturing method. More specifically, it relates to a method for manufacturing an SOI substrate based on a bonded wafer method in which silicon wafers are bonded to each other via an insulating film.

[0002]

2. Description of the Related Art In order to break the limit of VLSI using silicon (Si), SOI technology for forming a single crystal Si layer on an insulating substrate has been widely studied worldwide. This S
As OI technology, SIMOX (Separation by
Implanted Oxygen) method and bonded wafer method are attracting attention.

Among them, the SIMOX method is a method for forming a SOI (Si active layer on a SiO ₂ insulating layer) by ion-implanting oxygen into a Si substrate at a high concentration. Crystal defects such as dislocations generated in the Si active layer due to the ion implantation limit the performance of a device (for example, CMOS) formed using the Si active layer. On the other hand, in the bonded wafer method, one or two of the two wafers are thermally oxidized, then the two wafers are bonded to each other, and one wafer is thinned to form an SOI. Techniques such as grinding and polishing are used as the technique for thinning the wafer, but the current mechanical polishing method has a limitation in polishing accuracy, and the Si active layer having a film thickness of about 1 μm ± 10% is used. I could only get it.

Further, in VLSI / CMOS, S
Since an i active layer having a thickness of 0.1 μm or less is required, bond and etch back SOI (Bond and Etc
A method called h back Silicon-On-Insulator (BESOI) method has been studied. In this BESOI method, S
A method of controlling the film thickness of the Si active layer by providing an etching stop layer on the i substrate and selectively performing etch back, and measuring the thickness of the Si active layer and locally based on the data. Si by plasma etching
There is a method of controlling the film thickness of the active layer.

A general method for manufacturing a BESOI substrate will be described below with reference to FIG. That is, as shown in FIG. 8 (a), first, a Si high concentration boron (B) doped p ⁺ -type Si layer 52 as an etching stop layer on the substrate 51 as a seed wafer to form, this p ⁺
After the Si active layer 53 is formed on the type Si layer 52, the S
A silicon dioxide (SiO ₂ ) film 54 is formed on the i active layer 53.

Next, as shown in FIG.
Another Si substrate 55 serving as a support substrate (also called a handle wafer) is attached to the O ₂ film 54. Next, after the Si substrate 51, which is a seed wafer, is thinned to a thickness of 1 to 2 μm by grinding and polishing from the back surface side, the remaining thinned Si substrate 51 is
As described in Electrochemical Society, Vol. 137, 3626 (1990), it is removed by chemical etching using a mixed solution of ethylenediamine-pure water-pyrocatechol-pyrazine. During this etching, the selective etching ratio of the Si substrate 51 with respect to the p ⁺ -type Si layer 52 can be increased due to the difference in the concentration of B in Si. Therefore, even if the remaining Si substrate 51 is completely removed by etching, p ⁺
The type Si layer 52 is hardly etched. After this, p ⁺
The type Si layer 52 is completely removed by chemical etching using a mixed solution of hydrofluoric acid-nitric acid-acetic acid. As a result, the surface of the Si active layer 53 is exposed as shown in FIG. 8C, and the desired SOI substrate is manufactured.

[0007]

However, in the above-described conventional method of manufacturing an SOI substrate, the future ultra LSI.
An SOI (S) having a film thickness of 50 nm or less, a TTV (Total Thickness Variation) of the film of 10% or less of the film thickness, and a surface roughness of 0.3 nm or less, which is required when manufacturing a MOS.
It was difficult to realize the i-active layer). For example, in local etch back using plasma etching,
When the film thickness is 100 nm or less, it is difficult to achieve an SOI (Si active layer) of 10% or less of the film thickness as TTV. Also heavily doped more of B in order to increase the selective etching ratio in a method for selectively etched back by a B-doped p ⁺ -type Si layer 52 as an etching stop layer is provided, but then the p ⁺ -type Si layer Crystal defects such as dislocations are generated in 52, and p ⁺ type S
Si active layer 53 epitaxially grown on i layer 52
In addition, crystal defects are generated, or B in the p ⁺ -type Si layer 52 diffuses into the Si active layer 53 due to high-temperature heat treatment during wafer bonding, which interferes with CMOS manufacturing.

On the other hand, Japanese Patent Publication No. 4-506587 discloses an SO based on the BESOI method using an etching stop layer made of a compound of Si and other group IV elements.
A method of manufacturing an I substrate is disclosed. According to this method, it is possible to make the final Si layer substantially uniform and eliminate impurities and defects in the final Si layer. However, when the content of the other group IV element is increased to increase the selective etching ratio by using the above etching stop layer, distortion occurs in the etching stop layer,
Dislocations are generated in order to relax the strain, or the etching stop layer is provided to increase the TTV and surface roughness of the Si active layer 53. This causes a bubble to be generated on the bonded surface of the wafer and lowers the bonding strength. In addition, when an ultrathin gate oxide film having a thickness of 5 nm is formed on the surface of the Si active layer 53, the dielectric breakdown voltage thereof is increased. In the future, which makes it difficult to apply to future VLSI manufacturing. That is, the conventional SO described above
Each of the I substrate manufacturing methods is an SO having a small TTV, a uniform active layer thickness, and a small surface roughness required for manufacturing a VLSI / CMOS.
It was difficult to manufacture the I substrate.

Therefore, an object of the present invention is to provide a final Si-Ge, Si-C or Si active layer having a small TTV, a uniform active layer thickness and a small surface roughness on the insulating layer. It is to provide a method for manufacturing an SOI substrate to be formed in. Another object of the present invention is to provide a method for manufacturing an SOI substrate that reduces the probability of void generation on the bonding surface.

[0010]

The inventors of the present invention have proposed the conventional S
As a result of intensive research to solve the above problems of the method for manufacturing an OI substrate, the following findings were obtained. That is, the high concentration B-doped p is obtained by thermally diffusing B on the surface of the Si substrate.
A sample having a ⁺ type Si layer was prepared, and the surface roughness of this p ⁺ type Si layer was measured by an atomic force microscope (AFM).
As a result, the surface roughness of the p ⁺ -type Si layer varies depending on the B concentration, but is as large as about 0.2 to 0.4 nm, and the depth of the surface of the p ⁺ -type Si layer depends on the thermal diffusion conditions. 1
It was found that a deep recess of ~ 3 nm was generated. Furthermore, it was found that this deep recess is also generated by cleaning the sample.

The cause of such deep recesses on the surface of the p ⁺ -type Si layer has not been clarified yet, but S
One of the causes is that boride of silicon, which has high hardness, is formed into fine particles on the surface when B ⁺ is thermally diffused on the surface of the i substrate to form a p ⁺ type Si layer, and that is taken for some reason. Conceivable. Thus, B-doped p ⁺ surface roughness of the type Si layer is large, the possibility exists for deeper recesses on its surface, a high concentration B-doped p ⁺ -type Si layer by the diffusion of B by annealing further subsequent step Since the concentration distribution of B at the interface with the Si substrate becomes unclear and the interface is likely to move, the inventors of the present invention have used the conventional method of manufacturing an SOI substrate by the BESOI method to produce B-doped p ^The present invention has been achieved by using a layer containing As or Sb in a high concentration, which has a diffusion coefficient in Si smaller than B and can increase the etching rate as compared with Si, instead of the ⁺ type Si layer.

(A) First SOI Substrate Manufacturing Method As shown in FIG. 1, the first SOI substrate manufacturing method according to the first embodiment of the present invention includes a first SOI substrate containing As or Sb of 1 × 10 ¹⁸ / cm ³ or more.
A step of forming the Si buffer layer 12 having an impurity concentration of less than 1 × 10 ¹⁸ / cm ³ on the Si substrate 11 (see FIG.
(A)), a step of forming a compound semiconductor layer 13 made of Si and Ge or Si and C on the Si buffer layer 12 (FIG. 1B), and an insulating layer 1 on the compound semiconductor layer 13.
6 (FIG. 1C), and a step of bonding the main surface of the support substrate 17 onto the insulating layer 16 (FIG. 1C).
(D), (e)), a step of removing most of the first Si substrate 11 to form a Si thin film 11a having a thickness of 5 μm or less (FIG.
(F)), a step of removing the Si thin film 11a with the first chemical etching solution (FIG. 1 (g)), the Si buffer layer 12
Is removed by the second chemical etching solution to leave the insulating layer 16 and the compound semiconductor layer 13 on the main surface of the supporting substrate 17 (FIG. 1 (h)).

The first Si substrate 11 is an n ⁺ type Si single crystal substrate containing As or Sb having a relatively small diffusion coefficient in Si of 1 × 10 ¹⁸ / cm ³ or more. The concentration of As or Sb is preferably 10 ¹⁹ / cm ³ or more. This S
Concentration of As or Sb of i substrate 11 and Si buffer layer 1
If the impurity concentration of 2 is not the above value, a sufficient etching selection ratio cannot be obtained. When As and Sb are compared as impurities contained in the Si substrate 11, As is S
It is preferable because it has a higher solid solubility in Si and a smaller diffusion coefficient than b. The Si buffer layer 12 is B, P, A
It may be a so-called “non-doped” layer having an impurity concentration of s, Sb or the like of less than 1 × 10 ¹⁸ / cm ³ and containing no impurities. The impurity concentration is preferably 10 ¹⁷ / cm ³ or less. The film thickness of the Si buffer layer is determined so that As or Sb in the Si substrate 11 does not diffuse to the entire region of the Si buffer layer by the heat treatment in the subsequent process. As a method of forming this Si buffer layer, CVD (chemical vapor deposition) is used.
Method, MBE (Molecular Beam Epitaxial Growth) method, or the like, or a method of heat-treating the Si substrate 11 to diffuse As or Sb in Si of the substrate surface layer outward.

A compound semiconductor layer 13 is formed on the Si buffer layer 12. As the compound semiconductor layer, Si and G
Examples thereof include compounds of e or Si and C. Specifically, Si
_1-x Ge _x layer or Si _1-x C _x layer with a composition ratio x of 0.
It is 03-0.3. This compound semiconductor layer has a layer thickness of 10
It is up to 150 nm and is formed by the CVD method, the MBE method or the like. The insulating layer 16 on the compound semiconductor layer 13 is formed by thermal oxidation or a CVD method. In the case of thermal oxidation, the thermal oxidation temperature is preferably 950 ° C. or lower in order to prevent As or Sb in the Si substrate 11 from thermally diffusing over the entire region of the Si buffer layer 12. About 900 ° C is more preferable.

In order to bond the main surface of the supporting substrate 17 onto the insulating layer 16, the surfaces of the two substrates 11 and 17 are cleaned and activated with a cleaning liquid such as SC1 and then activated, and then they are heat-laid on each other and fixed. . The heat treatment temperature is preferably 950 ° C. or lower, and more preferably about 900 ° C. for the same reason as in the thermal oxidation. The first Si substrate 11 is ground and polished to be removed to form a Si thin film 11a having a high concentration of As or Sb. This Si thin film 11a has a thickness of 5 μm or less, preferably 2 μm or less. The thinner the film thickness and the smaller the TTV, the better the flatness of the final active layer. The Si thin film 11a is completely removed by the first chemical etching solution. Examples of the first chemical etching solution include a mixed solution of hydrofluoric acid-nitric acid-acetic acid. The Si single crystal having an impurity concentration of 1 × 10 ¹⁷ / cm ³ or less and the Si single crystal having an impurity concentration of 1 × 10 ¹⁹ / cm ³ or more are 1:10.
An etching selection ratio of 0 or more can be obtained. Si thin film 11a
After removing the Si buffer layer 12 with the second chemical etching solution.
Is removed, an SOI substrate having the compound semiconductor layer 13 as a final active layer is obtained. Examples of the second chemical etching solution include a mixed solution of potassium hydroxide-potassium dichromate-isopropyl alcohol. If the final active layer is thermally oxidized to form an insulating film and the insulating film is treated with hydrofluoric acid and removed, the active layer can be made thinner.

(B) Second SOI Substrate Manufacturing Method As shown in FIG. 2, the second SOI substrate manufacturing method according to the second embodiment of the present invention includes a first SOI substrate containing As or Sb of 1 × 10 ¹⁸ / cm ³ or more.
A step of forming the Si buffer layer 12 having an impurity concentration of less than 1 × 10 ¹⁸ / cm ³ on the Si substrate 11 (see FIG.
(A)), a step of forming a compound semiconductor layer 13 made of Si and Ge or Si and C on the Si buffer layer 12 (FIG. 2B), and a Si active layer 14 on the compound semiconductor layer 13. The step of forming (FIG. 2C) and the step of forming the insulating layer 16 on the Si active layer 14 (FIG. 2C).
(D)), a step of adhering the main surface of the support substrate 17 onto the insulating layer 16 (FIGS. 2E and 2F), and most of the first Si substrate 11 is removed to have a thickness of 5 μm or less. Si thin film 1
1a (FIG. 2 (g)), this Si thin film 11a
With a first chemical etching solution (see FIG. 2).
(H)), a step of removing the Si buffer layer 12 with a second chemical etching solution to leave the insulating layer 16, the Si active layer 14, and the compound semiconductor layer 13 on the main surface of the supporting substrate 17 (FIG. 2).
(I)) is included.

Other than forming the Si active layer 14,
This is similar to the first manufacturing method of (a). The Si active layer 14 is formed in the same manner as the Si buffer layer 12, and the film thickness thereof is determined in the range of 3 nm to 3 μm according to the desired final thickness of the active layer. After forming the Si active layer 14, it is preferable to polish the layer surface in the depth range of 5 to 200 nm because the surface roughness is further improved.

(C) Third Method for Manufacturing SOI Substrate A third method for manufacturing an SOI substrate according to the present invention is, as shown in FIG. 3, a second Si substrate having an impurity concentration of less than 1 × 10 ¹⁸ / cm ³ .
A step of forming an impurity rich Si layer 19 containing 1 × 10 ¹⁸ / cm ³ or more of As or Sb on the substrate 18 (FIG.
(A)), a step of forming the Si buffer layer 12 having an impurity concentration of less than 1 × 10 ¹⁸ / cm ³ on the impurity-rich Si layer 19 (FIG. 3B), and Si on the Si buffer layer 12. And Ge or compound semiconductor layer 13 composed of Si and C
And a step of forming an insulating layer 16 on the compound semiconductor layer 13 (FIG. 3D),
The step of attaching the main surface of the support substrate 17 onto the insulating layer 16 (FIGS. 3E and 3F), the second Si substrate 18 and the impurity-rich Si layer 19 are partially removed to have a thickness. 5
a step of forming a Si thin film 19a having a thickness of less than or equal to μm (see FIG.
(G)), a step of removing the Si thin film 19a with the first chemical etching solution (FIG. 3 (h)), the Si buffer layer 12
Is removed by the second chemical etching solution to leave the insulating layer 16 and the compound semiconductor layer 13 on the main surface of the supporting substrate 17 (FIG. 3 (i)).

The second Si substrate 18 has an impurity concentration of B, P, As, Sb, etc. less than 1 × 10 ¹⁸ / cm ³ .
If the impurity concentration is less than this value, the Si substrate 18 is n
Type Si single crystal substrate or p type Si single crystal substrate. The impurity-rich Si layer 19 is shown in FIGS.
Of the first Si substrate 11. The impurities in the impurity-rich layer 19 are so-called “dopants”. As a method for forming the impurity-rich Si layer 19, there are an epitaxial growth method such as a thermal diffusion method, a CVD method, and an MBE method, in addition to the ion implantation method. This impurity-rich Si layer 1
The steps after the step of forming 9 are the same as those of the first manufacturing method. After forming the impurity-rich Si layer 19, it is preferable to polish the layer surface in the depth range of 5 to 200 nm because the surface roughness is further improved.

(D) Fourth SOI Substrate Manufacturing Method As shown in FIG. 4, the fourth SOI substrate manufacturing method according to the present invention is performed with the second Si having an impurity concentration of less than 1 × 10 ¹⁸ / cm ³ .
A step of forming an impurity-rich Si layer 19 containing 1 × 10 ¹⁸ / cm ³ or more of As or Sb on the substrate 18 (FIG.
(A)), a step of forming the Si buffer layer 12 having an impurity concentration of less than 1 × 10 ¹⁸ / cm ³ on the impurity-rich Si layer 19 (FIG. 4B), and Si on the Si buffer layer 12 And Ge or compound semiconductor layer 13 composed of Si and C
And a step of forming the Si active layer 14 on the compound semiconductor layer 13 (FIG. 4C).
(D)), a step of forming the insulating layer 16 on the Si active layer 14 (FIG. 4 (e)), and a step of bonding the main surface of the support substrate 17 on the insulating layer 16 (FIG. 4 (f)). ),
(G)), the entire second Si substrate 18 and the impurity rich S
A part of the i layer 19 is removed to remove the Si thin film 1 having a thickness of 5 μm or less.
9a (FIG. 4 (h)), this Si thin film 19a
With a first chemical etching solution (see FIG.
(I)) a step of removing the Si buffer layer 12 with a second chemical etching solution to leave the insulating layer 16, the Si active layer 14, and the compound semiconductor layer 13 on the main surface of the supporting substrate 17 (FIG. 4).
(J)) is included. Except that the Si active layer 14 is formed, it is the same as the third manufacturing method of (c) above. The Si active layer 14 is formed in the same manner as the Si buffer layer 12, and the film thickness thereof is determined in the range of 3 nm to 3 μm according to the desired final thickness of the active layer.

(E) Fifth SOI Substrate Manufacturing Method In the fifth SOI substrate manufacturing method of the present invention, as shown in FIG. 5, the third Si substrate having an impurity concentration of less than 1 × 10 ¹⁸ / cm ³ is used.
Embedded Si embedded in the substrate 21 to a predetermined depth from the substrate surface so as to contain As or Sb of 1 × 10 ¹⁸ / cm ³ or more.
A step of forming the layer 22 (FIGS. 5A and 5B), and a compound semiconductor layer made of Si and Ge or Si and C on the Si buffer layer 21a of the third Si substrate 21 above the embedded Si layer 22. 13 (FIG. 5C), the step of forming the insulating layer 16 on the compound semiconductor layer 13 (FIG. 5D), and the main surface of the support substrate 17 on the insulating layer 16. The step of bonding (FIGS. 5E and 5F), the third Si substrate 21 and the embedded S below the embedded Si layer 22.
A part of the i layer 22 is removed to remove the Si thin film 2 having a thickness of 5 μm or less.
2a (FIG. 5 (g)), this Si thin film 22a
With a first chemical etching solution (see FIG.
(H)), a step of removing the Si buffer layer 21a with a second chemical etching solution to leave the insulating layer 16 and the compound semiconductor layer 13 on the main surface of the supporting substrate 17 (FIG. 5 (i)). Is characterized by.

The buried Si layer 22 is formed by implanting As ions or Sb ions into the third Si substrate 21 at a high concentration.
It is formed by annealing. The embedded Si layer 22 has a predetermined depth from the surface of the Si substrate 21, for example, 3 nm to 3 μ.
It is formed in a region of m with a thickness of 500 nm to 3 μm. The compound semiconductor layer 1 is formed on the surface of the Si buffer layer 21a.
The steps after the step of forming 3 are the same as those in the third manufacturing method.

(F) Sixth SOI Substrate Manufacturing Method In the sixth SOI substrate manufacturing method of the present invention, as shown in FIG. 6, an impurity concentration of the third Si substrate is less than 1 × 10 ¹⁸ / cm ³ .
Embedded Si embedded in the substrate 21 to a predetermined depth from the substrate surface so as to contain As or Sb of 1 × 10 ¹⁸ / cm ³ or more.
A step of forming the layer 22 (FIGS. 6A and 6B), and a compound semiconductor layer made of Si and Ge or Si and C on the Si buffer layer 21 a of the third Si substrate 21 above the embedded Si layer 22. 13 (FIG. 6C), the step of forming the Si active layer 14 on the compound semiconductor layer 13 (FIG. 6D), and the formation of the insulating layer 16 on the Si active layer 14. Process (FIG. 6 (e)), bonding the main surface of the support substrate 17 on the insulating layer 16 (FIG. 6 (f),
(G)), the third Si substrate 2 below the embedded Si layer 22
1 and a part of the embedded Si layer 22 to form a Si thin film 22a having a thickness of 5 μm or less (FIG. 6 (h)), and a step of removing the Si thin film 22a with a first chemical etching solution (FIG. 6 (i)), the Si buffer layer 21a is removed by the second chemical etching solution to remove the insulating layer 1 on the main surface of the supporting substrate 17.
6, a step of leaving the Si active layer 14 and the compound semiconductor layer 13 (FIG. 6 (j)). Except that the Si active layer 14 is formed, it is the same as the fifth manufacturing method (e). The Si active layer 14 is formed similarly to the Si buffer layer 12 of the first manufacturing method.

(G) Seventh SOI Substrate Manufacturing Method Further, as shown in FIG. 7, the seventh SOI substrate manufacturing method of the present invention is a method for manufacturing second, fourth and sixth SOI substrates. Final compound semiconductor layer 13 obtained in (FIG. 7 (a))
Is further removed to leave the insulating layer 16 and the Si active layer 14 on the main surface of the support substrate 17 (FIG. 7B). The compound semiconductor layer 13 is removed by polishing or a chemical etching solution using a mixed solution of hydrofluoric acid-nitric acid-acetic acid.

[0025]

Conventionally, if the p ⁺ type Si layer doped with B having a large diffusion coefficient in Si is used as an etching stop layer,
The surface roughness is large, and the profile of the B concentration is largely changed by thermal oxidation for forming an insulating layer or annealing treatment after bonding, and the flatness of the layer surface after chemical etching and the uniform layer thickness are obtained. However, in the present invention, since a Si substrate or Si layer containing As or Sb having a diffusion coefficient in Si smaller than B in a high concentration is used in place of the B-doped p ⁺ type Si layer in the present invention, In comparison, since the As or Sb concentration profile can be kept steep even after high-temperature heat treatment, the thickness variation of the active layer after chemical etching is small, and the flatness of the layer surface is good.

[0026]

Embodiments of the present invention will now be described in detail with reference to the drawings. Here, the SOI substrate obtained by the seventh manufacturing method from the second manufacturing method will be described with reference to FIGS.
It will be described based on. As shown in FIG. 2A to FIG. 2I, first, a non-doped Si buffer layer 12 is formed on the first Si substrate 11 containing 5 × 10 ¹⁹ / cm ³ of As having a (100) plane orientation, which is a seed wafer. Was formed by the CVD method. Specifically, 900 at 3 Torr in H ₂ atmosphere
After pretreatment at 3 ° C. for 3 minutes, SiH ₄ gas or Si ₂ H ₆ gas was used as a reaction gas and grown at a temperature of 700 ° C. to form the Si buffer layer 12. The thickness of the Si buffer layer 12 is such that As in the Si substrate 11 is diffused during each heat treatment of thermal oxidation and wafer bonding described later.
It is necessary to have a thickness that does not reach the _1-x Ge _x layer 13. In this example, it was 50 nm.

Subsequently to the Si buffer layer 12, a Si _1-x Ge _x layer 13 and a Si active layer 14 were formed by the CVD method. When epitaxially growing the Si _1-x Ge _x layer 13, SiH ₄ gas and GeH ₄ gas are used as reaction gases, or Si ₂ H ₆ gas and GeH ₄ gas are used, and
Grow at a temperature of 0-800 ° C. Si _1-x Ge _x layer 13
In order to suppress the unevenness of the surface of the
e The composition ratio x was set to 0.1 and the thickness was set to 80 nm. Further, Si ₂ H ₆ gas and GeH ₄ gas were used as reaction gases. The Si active layer 14 was formed in the same manner as the Si buffer layer 12 except that the thickness was 100 nm. Si active layer 1
4 was surface-polished and then thermally oxidized at 900 ° C. in a water vapor atmosphere to form a SiO ₂ insulating layer 16 on the Si active layer 14. After cleaning the Si substrate 11 and another supporting substrate 17 to be the handle wafer with the cleaning liquid of SC1 to activate the bonding surface of both substrates, the insulating layer 16 is superposed on the main surface of the supporting substrate 17, and at 900 ° C. Heat treated.

Next, the Si substrate 11 was ground and polished from the surface opposite to the bonding surface of the Si substrate 11 to remove most of the thin film to make a thin film, and a Si thin film 11a of about 1 μm was left. This Si thin film 11a was removed by chemical etching with a mixed solution of hydrofluoric acid-nitric acid-acetic acid. In this example, the selective etching ratio between the Si substrate 11 having a high As concentration and the Si buffer layer 12 can be about 1: 150. Then Si
The buffer layer 12 was removed by chemical etching with a mixed solution of potassium hydroxide-potassium dichromate-isopropyl alcohol. In this example, the Si buffer layer 12 and Si
The selective etching ratio with the _1-x Ge _x layer 13 can be about 1:25. Finally, the Si _1-x Ge _x layer 13 is removed by chemical etching with a mixed solution of hydrofluoric acid-nitric acid-acetic acid. As shown in FIG. An SOI substrate having the active layer 14 left was obtained. In this example, the selective etching ratio between the Si _1-x Ge _x layer 13 and the Si active layer 14 can be about 1:20. In this SOI substrate, the Si active layer 14 has a film thickness of 50 nm.
Where TTV is 3% of film thickness and surface roughness is 0.2n
It was m.

[0029]

As described above, according to the method for manufacturing an SOI substrate of the present invention, a Si substrate or Si layer containing As or Sb having a diffusion coefficient in Si smaller than B at a high concentration is conventionally B-doped. Since it is used instead of the p ⁺ -type Si layer, the As or Sb concentration profile can be kept steep even when subjected to a high temperature heat treatment as compared with the conventional method, so that the variation in the thickness (TTV) of the active layer after chemical etching is reduced. It is small and the flatness of the layer surface is good. Further, since the surface roughness of the bonded surface is small, the probability of occurrence of voids in the bonded surface can be reduced. From these things, the SO of the present invention
The I substrate is suitable for a highly integrated semiconductor integrated circuit substrate.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a first SOI substrate of the present invention in the order of steps.

2A to 2D are cross-sectional views showing a method of manufacturing a second SOI substrate of the present invention in the order of steps.

3A to 3C are cross-sectional views showing a method of manufacturing a third SOI substrate of the present invention in the order of steps.

4A to 4D are cross-sectional views showing a fourth SOI substrate manufacturing method of the present invention in the order of steps.

FIG. 5 is a cross-sectional view showing the fifth method of manufacturing an SOI substrate of the present invention in the order of steps.

6A to 6C are cross-sectional views showing a method of manufacturing a sixth SOI substrate of the present invention in the order of steps.

7A to 7D are cross-sectional views showing a seventh SOI substrate manufacturing method of the present invention in the order of steps.

FIG. 8 is a cross-sectional view showing a method of manufacturing a conventional SOI substrate in the order of steps.

[Explanation of symbols]

 11 1st Si substrate 11a Si thin film 12 Si buffer layer 13 compound semiconductor layer 14 Si active layer 16 insulating layer 17 supporting substrate 18 2nd Si substrate 19 impurity rich Si layer 19a Si thin film 21 3rd Si substrate 21a Si buffer layer 22 embedded Si layer 22a Si thin film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeshi Matsushita 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) In-house Yoshio Nakajima 3-8-16 Iwamoto-cho, Chiyoda-ku, Tokyo No. Sanritsu Material Silicon Co., Ltd. (72) Inventor Takayuki Shinko, 297-1, Kitabukuro-cho, Omiya City, Saitama Prefecture Central Research Laboratory, Mitsubishi Materials Corporation

Claims (7)

[Claims] 1. An impurity concentration of 1 × 10 ¹⁸ / c on a first Si substrate (11) containing 1 × 10 ¹⁸ / cm ³ or more of As or Sb.
forming a Si buffer layer (12) of less than m ³ ; forming a compound semiconductor layer (13) made of Si and Ge or Si and C on the Si buffer layer (12); (13) forming an insulating layer (16) on the insulating layer (16), attaching the main surface of the supporting substrate (17) on the insulating layer (16), and removing most of the first Si substrate (11) To form a Si thin film (11a) having a thickness of 5 μm or less, a step of removing the Si thin film (11a) with a first chemical etching solution, and a step of removing the Si buffer layer (12) with a second chemical etching solution. And a step of leaving the insulating layer (16) and the compound semiconductor layer (13) on the main surface of the supporting substrate (17). 2. An impurity concentration of 1 × 10 ¹⁸ / c on a first Si substrate (11) containing 1 × 10 ¹⁸ / cm ³ or more of As or Sb.
forming a Si buffer layer (12) of less than m ³ ; forming a compound semiconductor layer (13) made of Si and Ge or Si and C on the Si buffer layer (12); Forming a Si active layer (14) on (13), forming an insulating layer (16) on the Si active layer (14), and supporting substrate (17) on the insulating layer (16) Bonding the main surfaces of the first Si substrate (11), removing most of the first Si substrate (11) into a Si thin film (11a) having a thickness of 5 μm or less, and forming the Si thin film (11a) into a first chemical etching solution. And a step of removing the Si buffer layer (12) with a second chemical etching solution to form the insulating layer (16), the Si active layer (14), and the Si active layer (14) on the main surface of the supporting substrate (17). A step of leaving the compound semiconductor layer (13) and a method of manufacturing an SOI substrate. 3. As or Sb on the second Si substrate (18) having an impurity concentration of less than 1 × 10 ¹⁸ / cm ³ and 1 × 10 ¹⁸ / cm.
A step of forming an impurity-rich Si layer (19) containing ³ or more, and an impurity concentration of 1 × 10 on the impurity-rich Si layer (19).
A step of forming a Si buffer layer (12) of less than ¹⁸ / cm ^3, a step of forming a compound semiconductor layer (13) made of Si and Ge or Si and C on the Si buffer layer (12), A step of forming an insulating layer (16) on the semiconductor layer (13); a step of bonding the main surface of a supporting substrate (17) on the insulating layer (16); The impurity-rich Si
By removing a part of the layer (19), a Si thin film (19
a), a step of removing the Si thin film (19a) with a first chemical etching solution, and a step of removing the Si buffer layer (12) with a second chemical etching solution. And a step of leaving the insulating layer (16) and the compound semiconductor layer (13) on the surface thereof. 4. As or Sb of 1 × 10 ¹⁸ / cm on a second Si substrate (18) having an impurity concentration of less than 1 × 10 ¹⁸ / cm ^3.
A step of forming an impurity-rich Si layer (19) containing ³ or more, and an impurity concentration of 1 × 10 on the impurity-rich Si layer (19).
A step of forming a Si buffer layer (12) of less than ¹⁸ / cm ^3, a step of forming a compound semiconductor layer (13) made of Si and Ge or Si and C on the Si buffer layer (12), A step of forming a Si active layer (14) on the semiconductor layer (13), a step of forming an insulating layer (16) on the Si active layer (14), and a supporting substrate ( 17) bonding the main surfaces of the second Si substrate (18) and the impurity-rich Si
By removing a part of the layer (19), a Si thin film (19
a), a step of removing the Si thin film (19a) with a first chemical etching solution, and a step of removing the Si buffer layer (12) with a second chemical etching solution. A method of manufacturing an SOI substrate, comprising a step of leaving the insulating layer (16), the Si active layer (14) and the compound semiconductor layer (13) on the surface. 5. A third Si substrate (21) having an impurity concentration of less than 1 × 10 ¹⁸ / cm ³ is embedded to a predetermined depth from the substrate surface so as to contain As or Sb of 1 × 10 ¹⁸ / cm ³ or more. A step of forming a buried Si layer (22), and S of the third Si substrate (21) above the buried Si layer (22).
forming a compound semiconductor layer (13) made of Si and Ge or Si and C on the i buffer layer (21a); forming an insulating layer (16) on the compound semiconductor layer (13); Bonding the main surface of the support substrate (17) on the insulating layer (16), and removing a part of the third Si substrate (21) and the embedded Si layer (22) below the embedded Si layer (22) To form a Si thin film (22a) having a thickness of 5 μm or less, a step of removing the Si thin film (22a) with a first chemical etching solution, and a step of removing the Si buffer layer (21a) with a second chemical etching solution. And a step of leaving the insulating layer (16) and the compound semiconductor layer (13) on the main surface of the supporting substrate (17). 6. A third Si substrate (21) having an impurity concentration of less than 1 × 10 ¹⁸ / cm ³ is embedded to a predetermined depth from the substrate surface so as to contain As or Sb of 1 × 10 ¹⁸ / cm ³ or more. A step of forming a buried Si layer (22), and S of the third Si substrate (21) above the buried Si layer (22).
a step of forming a compound semiconductor layer (13) made of Si and Ge or Si and C on the i buffer layer (21a), and a step of forming a Si active layer (14) on the compound semiconductor layer (13), A step of forming an insulating layer (16) on the Si active layer (14); a step of bonding a main surface of a support substrate (17) on the insulating layer (16); and a step of forming the embedded Si layer (22). A step of removing a part of the lower third Si substrate (21) and the embedded Si layer (22) to form a Si thin film (22a) having a thickness of 5 μm or less; And a step of removing the Si buffer layer (21a) with a second chemical etching solution to form the insulating layer (16), the Si active layer (14), and the Si active layer (14) on the main surface of the supporting substrate (17). A step of leaving the compound semiconductor layer (13) and a method of manufacturing an SOI substrate. 7. A supporting substrate obtained by removing a compound semiconductor layer (13).
7. The method for manufacturing an SOI substrate according to claim 2, further comprising the step of leaving the insulating layer (16) and the Si active layer (14) on the main surface of (17).