JPH08148470A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH08148470A
JPH08148470A JP28664094A JP28664094A JPH08148470A JP H08148470 A JPH08148470 A JP H08148470A JP 28664094 A JP28664094 A JP 28664094A JP 28664094 A JP28664094 A JP 28664094A JP H08148470 A JPH08148470 A JP H08148470A
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Japan
Prior art keywords
film
plasma
surface
wiring layer
formed
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP28664094A
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Japanese (ja)
Inventor
Eiichi Mitsusaka
栄一 三坂
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Sanyo Electric Co Ltd
三洋電機株式会社
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Priority to JP28664094A priority Critical patent/JPH08148470A/en
Publication of JPH08148470A publication Critical patent/JPH08148470A/en
Application status is Pending legal-status Critical

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Abstract

PURPOSE: To protect Al against corrosion and a semiconductor device against contamination caused by heavy metal in an etching device by a method wherein an oxide film is formed on the side wall of an At wiring layer, and then a second silicon oxide film and an SOG film formed on all the surface are etched back.
CONSTITUTION: An Al wiring layer 32 is formed on a BPSG film 31 provided onto a silicon substrate, a plasma Si3N4 film 33 is formed covering the Al wiring layer 32, and then a first plasma TEOS film is formed on all the surface. Then, the first plasma TEOS film is etched throughout its surface making the surface of plasma Si3N4 film 33 function as an etching end point detection plane, whereby a side wall oxide film 35 is formed on the side wall of the Al wiring layer 32. Then, a second plasma TEOS film 36 is formed on all the surface of the substrate, SOG is applied onto all the surface of the second plasma TEOS film 36 by spin coating so as to form an SOG film 37 to fill recesses located on the second plasma TEOS film 36. An interlayer insulating film flattened by etching back is formed.
COPYRIGHT: (C)1996,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、半導体装置の製造方法に関し、さらに詳しく言えばAl配線層上に形成する層間絶縁膜の平坦化方法の改善に関する。 The present invention relates relates to a method of manufacturing a semiconductor device, to an improved method of planarization of an interlayer insulating film formed on the Al wiring layer more particularly.

【0002】 [0002]

【従来の技術】従来の半導体装置の製造方法を図6乃至図13を参照しながら説明する。 It will be described with reference to FIGS. 6 to 13 the method for producing a conventional semiconductor device. まず、図6に示すように、半導体基板上に形成したBPSG膜(1)上に、Al First, as shown in FIG. 6, on the BPSG film formed on a semiconductor substrate (1), Al
配線層(2)を形成し、そのAl配線層(2)を被覆するように、プラズマCVD装置によりプラズマTEOS膜3を形成する。 Forming a wiring layer (2), so as to cover the Al wiring layer (2), to form a plasma TEOS film 3 by plasma CVD apparatus. 次に、図7に示すように、そのプラズマTEOS膜(3)上の全面にSOGを回転塗布する。 Next, as shown in FIG. 7, spin-coated on the entire surface SOG of the plasma TEOS film (3) on. すると、プラズマTEOS膜(3)の凹部を充填するようにSOG膜(4)が形成される。 Then, SOG film (4) is formed so as to fill the recess of the plasma TEOS film (3). そして、図8に示すように、全面エッチバックにより、平坦化された層間絶縁膜を形成している。 Then, as shown in FIG. 8, the entire surface is etched back to form a planarized interlayer insulating film. しかしながら、プラズマTEOS膜(3)は、オーバーハングした形状を有するために、エッチバック後にSOG膜の残り(4A)が生じ、このためプラズマTEOS膜(3)のクラック(5)の発生を招いていた。 However, the plasma TEOS film (3) in order to have an overhanging shape, remaining SOG film (4A) occurs after the etch-back, have led to occurrence of cracks (5) in this order plasma TEOS film (3) It was.

【0003】その一方、SOG膜の残り(4A)を防止するためにSOGのエッチングレートをプラズマTEO [0003] On the other hand, plasma SOG etching rate in order to prevent the remaining SOG film (4A) TEO
Sのエッチングレートに比して大きく設定することは、 It is greater than the etching rate of S is
両者のエッチングレートを等しくするというエッチバック本来の特徴が生かせず、十分な平坦性が得られないという欠点がある。 Not Ikase is etched back inherent feature of equalizing the etching rate of both, there is a drawback that sufficient flatness can not be obtained. そこで、上記の課題を解決するために、Al配線層の側壁酸化膜を設けることにより、プラズマTEOS膜(3)がオーバーハング形状となりSOG Therefore, in order to solve the above problems, by providing a side wall oxide film of the Al wiring layer, a plasma TEOS film (3) becomes the overhang SOG
膜が残るのを防止する方法が考えられた。 How to prevent the film remains were considered. 以下、その製造方法を図9乃至図13を参照しながら説明する。 It will be described below with reference to FIGS. 9 to 13 a method of manufacturing. まず、図9に示すように、半導体基板上に形成したBPS First, as shown in FIG. 9, BPS formed on a semiconductor substrate
G膜(11)上に、Al配線層(12)を形成し、そのAl On G film (11), to form Al wiring layer (12), the Al
配線層(12)を被覆するように、プラズマCVD装置により第1のプラズマTEOS膜(13)を形成する。 As the wiring layer (12) covering, forming a first plasma TEOS film (13) by a plasma CVD apparatus.
次に、図10に示すように、第1のプラズマTEOS膜(13)をエッチバックし、側壁酸化膜14を形成する。 Next, as shown in FIG. 10, the first plasma TEOS film (13) is etched back to form a sidewall oxide film 14. 第2のプラズマTEOS膜(15)を形成する。 Forming a second plasma TEOS film (15). このとき、側壁酸化膜(14)を設けたことにより下地に傾斜がついているので第2のプラズマTEOS膜(1 At this time, the second plasma TEOS film Comes is inclined to the substrate by providing the side wall oxide film (14) (1
5)はオーバーハングした形状とはならない。 5) is not a overhang shape.

【0004】次いで、図12に示すように、その第2のプラズマTEOS膜(13)上の全面にSOGを回転塗布し、プラズマTEOS膜(15)の凹部を充填するようにSOG膜(16)を形成する。 [0004] Then, as shown in FIG. 12, SOG was spin-coated on the entire surface of the second plasma TEOS film (13), SOG film so as to fill the recess of the plasma TEOS film (15) (16) to form. そして、図13に示すように、全面エッチバックにより平坦化した層間絶縁膜(17)を形成する。 Then, as shown in FIG. 13, to form a planarized interlayer insulating film (17) by etching back the entire surface. 上記の製造方法によれば、第2 According to the manufacturing method described above, the second
のプラズマTEOS膜(15)がオーバーハングした形状とならないので、SOG膜の残りが発生しにくくなり、層間絶縁膜(17)にクラックが入ることが防止されるとともに、プラズマTEOSとSOGに対するエッチングレートを等しくできるので、より平坦化した層間絶縁膜を形成することが可能となる。 Because of the plasma TEOS film (15) is not an overhanging shape, becomes the remaining SOG film hardly occurs, with cracks that enters is prevented in the interlayer insulating film (17), the etching rate for plasma TEOS and SOG since the possible equal, it is possible to form a more planarized interlayer insulating film.

【0005】 [0005]

【発明が解決しようとする課題】しかしながら、上記の半導体装置の製造方法では、図10に示すように、選択酸化膜(14)の形成時にAl配線層(12)の表面が露出するため、Alコロージョンが発生したり、エッチング装置内に重金属類の汚染が発生するなどの問題があった。 [SUMMARY OF THE INVENTION However, in the method of manufacturing a semiconductor device, as shown in FIG. 10, since the surface of the Al wiring layer when forming the selective oxide film (14) (12) exposed, Al corrosion may occur, contamination of heavy metals is a problem, such as occurs in the etching apparatus.

【0006】 [0006]

【課題を解決するための手段】本発明は、上記課題を解決するために、Al配線層をシリコン窒化膜で被覆した後にプラズマTEOS膜を全面に形成し、そのプラズマT Means for Solving the Problems The present invention, in order to solve the above problems, a plasma TEOS film is formed on the entire surface after coating the Al wiring layer in the silicon nitride film, the plasma T
EOS膜をエッチバックして側壁酸化膜を形成する際に、エッチングレートの差を利用してシリコン窒化膜の表面でエッチングの終点検出を行うようにした。 The EOS film is etched back during the formation of the sidewall oxide films and by utilizing the difference in etching rate at the surface of the silicon nitride film to perform end point detection of the etching.

【0007】 [0007]

【作用】本発明によれば、Al配線層をシリコン窒化膜で被覆しているので、側壁酸化膜を形成するときにAl配線層が露出することがなくなり、Alコロージョンの発生やエッチング装置の重金属汚染等を防止することができる。 According to the present invention, since the covering the Al wiring layer in the silicon nitride film, prevents the Al wiring layer is exposed when forming a sidewall oxide film, heavy metals Al corrosion generation and etching apparatus it is possible to prevent contamination and the like. また、本発明によれば、Al配線層の側壁酸化膜を形成しているので、プラズマTEOS膜をオーバーハングした形状とならず、この結果SOG膜の残りが発生しにくくなり、層間絶縁膜にクラックが入ることが防止されるとともに、プラズマTEOSとSOGに対するエッチングレートを等しくできるので、より平坦化した層間絶縁膜を形成することが可能となる。 Further, according to the present invention, since the forming side wall oxide film of the Al wiring layer, not the plasma TEOS film and overhanging shape, the result becomes the remaining SOG film hardly occurs in the interlayer insulating film together with the cracks is prevented, it is possible to equalize the etching rate of the plasma TEOS and SOG, it is possible to form a more planarized interlayer insulating film.

【0008】 [0008]

【実施例】以下で、本発明の半導体装置の製造方法の一実施例を図1乃至図5を参照しながら説明する。 EXAMPLES In the following, an embodiment of a method of manufacturing a semiconductor device of the present invention will be described with reference to FIGS. まず、 First of all,
図1に示すように、シリコン基板上に形成したBPSG As shown in FIG. 1, BPSG was formed on a silicon substrate
膜(31)上に、5000Åから7000Å程度のAl配線層(32)を形成し、そのAl配線層(32)を被覆するように、500Åから1000Å程度のプラズマSi3N On the membrane (31), 5000 Å to form a 7000Å about Al wiring layer (32) from, so as to cover the Al wiring layer (32), from 500Å to about 1000Å plasma Si3N
4膜(33)を形成し、その後5000Åから7000 4 to form a film (33), then 7000 from 5000Å
Å程度の第1のプラズマTEOS膜(34)を全面に形成する。 Å about the first plasma TEOS film (34) is formed on the entire surface. プラズマSi3N4膜(33)は、プラズマCVD Plasma Si3N4 film (33), a plasma CVD
装置を使用し、NH3,SiH4, N2 のガス系を反応させて得ている。 Using the device, it is obtained by reacting gas system of NH3, SiH4, N2. また、プラズマTEOS膜についても同様にプラズマCVD装置を使用し、O2, TEOSのガス系を反応させて得ている。 Further, using a plasma CVD apparatus Similarly for plasma TEOS film, it is obtained by reacting gas system of O2, TEOS.

【0009】次に、図2に示すように、プラズマSi3N4 [0009] Next, as shown in FIG. 2, the plasma Si3N4
膜(33)の表面をエッチングの終点検出面として前記第1のプラズマTEOS膜(34)を全面エッチングすることによりAl配線層(32)の側壁に側壁酸化膜(3 Film sidewall on the sidewall oxide film of the Al wiring layer by a surface entirely etching the first plasma TEOS film (34) as an end point detection surface of the etching of the (33) (32) (3
5)を形成する。 5) to form a. すなわち、本工程では、プラズマTE In other words, in this step, the plasma TE
OSとプラズマSi3N4とが異なるエッチングレートを示すことを利用して、プラズマSi3N4膜(33)の表面が露出した段階でエッチングを停止し、Al配線層(32) By utilizing the fact that exhibit different etch rates and OS and plasma Si3N4, plasma Si3N4 film surface (33) stops etching at the stage of exposure, Al wiring layer (32)
の表面が露出するのを防止している。 It is prevented from being exposed surfaces. したがって、プラズマTEOSのプラズマSi3N4に対する選択比をできるだけ大きくとることが望まれる。 Therefore, it is desirable that as large as possible the selectivity with respect to the plasma Si3N4 plasma TEOS.

【0010】本願発明者の実験によれば、RIE装置を使用した場合では、エッチングガスとしてC4F8, CF4, A According to the present inventor's experiments, in the case of using an RIE apparatus, C4F8, CF4, A as the etching gas
r, CO を用い、それぞれの流量を、3sccm,5sccm, r, using CO, and each flow rate, 3 sccm, 5 sccm,
600sccm,150sccmとし、圧力100mT,パワー1 600sccm, and 150sccm, pressure 100mT, Power 1
000Wの条件でエッチングすると、選択比として1 When etching in the conditions of 000W, 1 as a selection ratio
0:1程度が得られた。 0: about 1 was obtained. さらに、選択比を高めるには、 Furthermore, to increase the selection ratio,
RIE装置では困難であり、例えば誘導結合型エッチング装置を使用する必要がある。 It is difficult with a RIE apparatus, it is necessary to use for example an inductive coupling type etching apparatus. 本装置を使用した場合、 If you use the device,
エッチングガスとしてC2F6(流量25sccm)を用い、圧力2.5mT、ソースパワー2500W、バイアスパワー725Wの条件でエッチングしたところ、選択比として40:1という高い値が得られた。 C2F6 (the flow rate 25 sccm) as an etching gas, pressure 2.5 mT, a source power 2500W, was etched under the conditions of bias power 725W, 40 as a selection ratio: high value of 1 is obtained.

【0011】次に、図3に示すように、基板上の全面に第2のプラズマTEOS膜(36)を形成する。 [0011] Next, as shown in FIG. 3, a second plasma TEOS film over the entire surface of the substrate (36). 本工程では、プラズマCVD装置を使用し、O2, TEOSのガス系を反応させて、5000Åから7000ÅのTEOS膜を形成している。 In this step, using a plasma CVD apparatus, by reacting gas system of O2, TEOS, forming the TEOS film of 7000Å from 5000 Å. このとき、側壁酸化膜(35)を設けたことにより下地に傾斜がついているので第2のプラズマTEOS膜(36)はオーバーハングした形状とはならない。 At this time, the second plasma TEOS film (36) so that with a sloping base by providing the side wall oxide film (35) is not a overhanging shape.

【0012】次いで、図4に示すように、その第2のプラズマTEOS膜(36)上の全面にSOGを回転塗布し、第2のプラズマTEOS膜(36)の凹部を充填するようにSOG膜(37)を形成する。 [0012] Then, as shown in FIG. 4, the SOG is spin-coated on the entire surface of the second plasma TEOS film (36), SOG film so as to fill the recess of the second plasma TEOS film (36) to form (37). そして、図5に示すように、全面エッチバックにより平坦化した層間絶縁膜(38)を形成する。 Then, as shown in FIG. 5, to form a planarized interlayer insulating film (38) by etching back the entire surface. この後、さらに全面にプラズマTEOS膜を形成し、層間絶縁膜(38)の膜厚を十分確保してもよい。 Thereafter, further the plasma TEOS film is formed on the entire surface, it may be sufficiently secured the thickness of the interlayer insulating film (38).

【0013】このように、本実施例の製造方法によれば、Al配線層(32)をプラズマSi3N4膜(33)で被覆しているので、側壁酸化膜(35)を形成するときに [0013] Thus, according to the manufacturing method of this embodiment, since the coating with Al wiring layer (32) a plasma Si3N4 film (33), when forming the sidewall oxide films (35)
Al配線層(32)が露出することがなくなり、Alコロージョンの発生やエッチング装置の重金属汚染等を防止することができる。 It prevents the Al wiring layer (32) is exposed, it is possible to prevent the heavy metal contamination of the Al corrosion generation and etching apparatus. また、第2のプラズマTEOS膜(3 The second plasma TEOS film (3
6)がオーバーハングした形状とならないので、SOG Since 6) is not an overhang shape, SOG
膜の残りが発生しにくくなり、層間絶縁膜(38)にクラックが入ることが防止されるとともに、プラズマTE It remaining film hardly occurs, with cracks that enters is prevented in the interlayer insulating film (38), plasma TE
OSとSOGに対するエッチングレートを等しくできるので、より平坦化した層間絶縁膜を形成することが可能となる。 Since it equal etching rates for OS and SOG, it is possible to form a more planarized interlayer insulating film.

【0014】 [0014]

【発明の効果】以上説明したように、本発明の半導体装置の製造方法によれば、Al配線層をシリコン窒化膜で被覆しているので、側壁酸化膜を形成するときにAl配線層が露出することがなくなり、Alコロージョンの発生やエッチング装置の重金属汚染等を防止することができる。 As described in the foregoing, according to the manufacturing method of the semiconductor device of the present invention, since the covering the Al wiring layer in the silicon nitride film, exposed Al wiring layer when forming the sidewall oxide films it is not possible to, it is possible to prevent the heavy metal contamination of the Al corrosion generation and etching apparatus.

【0015】また、本発明によれば、Al配線層の側壁酸化膜を形成しているので、プラズマTEOS膜をオーバーハングした形状とならず、この結果SOG膜の残りが発生しにくくなり、層間絶縁膜にクラックが入ることが防止されるとともに、プラズマTEOSとSOGに対するエッチングレートを等しくできるので、より平坦化した層間絶縁膜を形成することが可能となる。 Further, according to the present invention, since the forming side wall oxide film of the Al wiring layer, not the plasma TEOS film and overhanging shape, the result becomes the remaining SOG film hardly occurs, inter with cracks that enters is prevented in the insulating film, it is possible to equalize the etching rate of the plasma TEOS and SOG, it is possible to form a more planarized interlayer insulating film.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施例に係る半導体装置の製造方法を説明する第1の断面図である。 1 is a first cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】本発明の一実施例に係る半導体装置の製造方法を説明する第2の断面図である。 2 is a second cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図3】本発明の一実施例に係る半導体装置の製造方法を説明する第3の断面図である。 3 is a third cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図4】本発明の一実施例に係る半導体装置の製造方法を説明する第4の断面図である。 4 is a fourth cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図5】本発明の一実施例に係る半導体装置の製造方法を説明する第5の断面図である。 5 is a fifth cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図6】従来例に係る半導体装置の製造方法を説明する断面図である。 6 is a sectional view for explaining a method for manufacturing a semiconductor device according to a conventional example.

【図7】従来例に係る半導体装置の製造方法を説明する断面図である。 7 is a sectional view for explaining a method for manufacturing a semiconductor device according to a conventional example.

【図8】従来例に係る半導体装置の製造方法を説明する断面図である。 8 is a sectional view for explaining a method for manufacturing a semiconductor device according to a conventional example.

【図9】従来例に係る半導体装置の製造方法を説明する断面図である。 9 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a conventional example.

【図10】従来例に係る半導体装置の製造方法を説明する断面図である。 10 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a conventional example.

【図11】従来例に係る半導体装置の製造方法を説明する断面図である。 11 is a sectional view for explaining a method for manufacturing a semiconductor device according to a conventional example.

【図12】従来例に係る半導体装置の製造方法を説明する断面図である。 12 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a conventional example.

【図13】従来例に係る半導体装置の製造方法を説明する断面図である。 13 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a conventional example.

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半導体基板上に形成した絶縁膜上にAl配線層を形成する工程と、前記絶縁膜およびAl配線層の表面を被覆するようにシリコン窒化膜を形成する工程と、 And 1. A process for forming an Al wiring layer on an insulating film formed on a semiconductor substrate, forming a silicon nitride film so as to cover the surface of the insulating film and the Al wiring layer,
    全面に第1のシリコン酸化膜を形成する工程と、前記シリコン窒化膜の表面をエッチングの終点検出面として前記第1のシリコン酸化膜を全面エッチングすることにより前記Al配線層の側壁酸化膜を形成する工程と、全面に第2のシリコン酸化膜を形成する工程と、全面にSOG Forming a first silicon oxide film on the entire surface, forming a sidewall oxide film of the Al wiring layer by blanket etching said first silicon oxide film of the surface of the silicon nitride film as an end point detection surface of the etching a step of, forming a second silicon oxide film on the entire surface, SOG on the entire surface
    膜を塗布する工程と、前記第2のシリコン酸化膜および前記SOG膜をエッチバックする工程とを有することを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device characterized by comprising the steps of applying a film, and a step of etching back the second silicon oxide film and the SOG film.
  2. 【請求項2】 シリコン基板上に形成した上にBPSG 2. A BPSG on formed on the silicon substrate
    膜上にAl配線層を形成する工程と、前記BPSG膜およびAl配線層の表面を被覆するようにプラズマSi3N4膜を形成する工程と、全面に第1のプラズマTEOS膜を形成する工程と、前記プラズマSi3N4膜の表面をエッチングの終点検出面として前記第1のプラズマTEOS膜を全面エッチングすることにより前記Al配線層の側壁にプラズマTEOSからなる側壁酸化膜を形成する工程と、 Forming an Al wiring layer on the membrane, forming a plasma Si3N4 film so as to cover the surface of the BPSG film and the Al wiring layer, forming a first plasma TEOS film is formed on the entire surface, the forming a side wall oxide film made of the plasma TEOS in the side wall of the Al wiring layer by etching the entire surface of the first plasma TEOS film surface of the plasma Si3N4 film as an end point detection surface of the etching,
    全面に第2のプラズマTEOS膜を形成する工程と、全面にSOG膜を塗布する工程と、前記第2のプラズマT Forming a second plasma TEOS film on the entire surface, a step of applying the entire surface SOG film, the second plasma T
    EOS膜および前記SOG膜をエッチバックする工程とを有することを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device characterized by a step of etching back the EOS film and the SOG film.
  3. 【請求項3】 前記第1のプラズマTEOS膜を全面エッチングして側壁酸化膜を形成する工程で、誘導結合型エッチング装置を使用することを特徴とする請求項2記載の半導体装置の製造方法。 Wherein the first plasma TEOS film in the step of forming a sidewall oxide film is entirely etched, the method of manufacturing a semiconductor device according to claim 2, wherein the use of inductively coupled etching system.
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