JPH08148470A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To protect Al against corrosion and a semiconductor device against contamination caused by heavy metal in an etching device by a method wherein an oxide film is formed on the side wall of an At wiring layer, and then a second silicon oxide film and an SOG film formed on all the surface are etched back. CONSTITUTION: An Al wiring layer 32 is formed on a BPSG film 31 provided onto a silicon substrate, a plasma Si3 N4 film 33 is formed covering the Al wiring layer 32, and then a first plasma TEOS film is formed on all the surface. Then, the first plasma TEOS film is etched throughout its surface making the surface of plasma Si3 N4 film 33 function as an etching end point detection plane, whereby a side wall oxide film 35 is formed on the side wall of the Al wiring layer 32. Then, a second plasma TEOS film 36 is formed on all the surface of the substrate, SOG is applied onto all the surface of the second plasma TEOS film 36 by spin coating so as to form an SOG film 37 to fill recesses located on the second plasma TEOS film 36. An interlayer insulating film flattened by etching back is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for planarizing an interlayer insulating film formed on an Al wiring layer.

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device will be described with reference to FIGS. First, as shown in FIG. 6, Al is formed on the BPSG film (1) formed on the semiconductor substrate.
A wiring layer (2) is formed, and a plasma TEOS film 3 is formed by a plasma CVD apparatus so as to cover the Al wiring layer (2). Next, as shown in FIG. 7, SOG is spin-coated on the entire surface of the plasma TEOS film (3). Then, the SOG film (4) is formed so as to fill the concave portion of the plasma TEOS film (3). Then, as shown in FIG. 8, a flattened interlayer insulating film is formed by etching back the entire surface. However, since the plasma TEOS film (3) has an overhanging shape, the rest (4A) of the SOG film is generated after the etching back, which causes cracks (5) in the plasma TEOS film (3). It was

On the other hand, in order to prevent the remaining (4 A) of the SOG film, the etching rate of SOG is set to plasma TEO.
Setting larger than the etching rate of S is
The original characteristic of etch-back that the etching rates of both are equalized cannot be utilized, and there is a drawback that sufficient flatness cannot be obtained. Therefore, in order to solve the above-mentioned problems, by providing a sidewall oxide film of the Al wiring layer, the plasma TEOS film (3) becomes an overhang shape and becomes SOG.
A method of preventing the film from remaining was considered. The manufacturing method will be described below with reference to FIGS. 9 to 13. First, as shown in FIG. 9, BPS formed on a semiconductor substrate
An Al wiring layer (12) is formed on the G film (11) and the Al
A first plasma TEOS film (13) is formed by a plasma CVD apparatus so as to cover the wiring layer (12).
Next, as shown in FIG. 10, the first plasma TEOS film (13) is etched back to form the sidewall oxide film 14. A second plasma TEOS film (15) is formed. At this time, since the side wall oxide film (14) is provided, the base is inclined, so that the second plasma TEOS film (1
5) does not have an overhanging shape.

Next, as shown in FIG. 12, SOG is spin-coated on the entire surface of the second plasma TEOS film (13) to fill the recesses of the plasma TEOS film (15). To form. Then, as shown in FIG. 13, a planarized interlayer insulating film (17) is formed by etch back. According to the above manufacturing method, the second
Since the plasma TEOS film (15) does not have an overhanging shape, the SOG film is less likely to remain, cracks are prevented from being formed in the interlayer insulating film (17), and the etching rate for the plasma TEOS and SOG is reduced. Can be made equal to each other, so that it is possible to form a flatter interlayer insulating film.

[0005]

However, in the above-described method for manufacturing a semiconductor device, the surface of the Al wiring layer (12) is exposed when the selective oxide film (14) is formed, as shown in FIG. There are problems such as corrosion and contamination of heavy metals in the etching apparatus.

[0006]

According to the present invention, in order to solve the above-mentioned problems, a plasma TEOS film is formed on the entire surface after coating an Al wiring layer with a silicon nitride film.
When the EOS film was etched back to form the sidewall oxide film, the etching end point was detected on the surface of the silicon nitride film by utilizing the difference in etching rate.

[0007]

According to the present invention, since the Al wiring layer is covered with the silicon nitride film, the Al wiring layer is not exposed when the sidewall oxide film is formed, and the occurrence of Al corrosion and the heavy metal of the etching apparatus. It is possible to prevent pollution and the like. Further, according to the present invention, since the sidewall oxide film of the Al wiring layer is formed, the plasma TEOS film does not have an overhanging shape, and as a result, the SOG film is less likely to remain, and the interlayer insulating film is not formed. Since cracks can be prevented and the etching rates for the plasma TEOS and SOG can be made equal, it is possible to form a flatter interlayer insulating film.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a semiconductor device of the present invention will be described below with reference to FIGS. First,
As shown in FIG. 1, BPSG formed on a silicon substrate
An Al wiring layer (32) of about 5000 Å to 7000 Å is formed on the film (31), and plasma Si3N of about 500 Å to 1000 Å is formed so as to cover the Al wiring layer (32).
4 membranes (33) are formed, then 5000 Å to 7000
A first plasma TEOS film (34) having a thickness of about Å is formed on the entire surface. Plasma Si3N4 film (33) is plasma CVD
It is obtained by reacting a gas system of NH3, SiH4, and N2 using a device. Similarly, the plasma TEOS film was obtained by using a plasma CVD apparatus and reacting a gas system of O2 and TEOS.

Next, as shown in FIG. 2, plasma Si3N4
The first plasma TEOS film (34) is entirely etched by using the surface of the film (33) as an etching end point detection surface, and thereby the side wall oxide film (3) is formed on the side wall of the Al wiring layer (32).
5) is formed. That is, in this process, plasma TE
Utilizing the fact that the OS and plasma Si3N4 have different etching rates, etching is stopped when the surface of the plasma Si3N4 film (33) is exposed, and the Al wiring layer (32)
The surface of the is prevented from being exposed. Therefore, it is desired to make the selection ratio of the plasma TEOS to the plasma Si3N4 as large as possible.

According to the experiments conducted by the inventor of the present application, when the RIE apparatus is used, C4F8, CF4, A is used as an etching gas.
Using r and CO, each flow rate is 3sccm, 5sccm,
600sccm, 150sccm, pressure 100mT, power 1
When etching under the condition of 000W, the selection ratio is 1
About 0: 1 was obtained. Furthermore, to increase the selection ratio,
This is difficult with an RIE apparatus, and it is necessary to use an inductively coupled etching apparatus, for example. When using this device,
When C2F6 (flow rate 25 sccm) was used as etching gas and etching was performed under the conditions of pressure 2.5 mT, source power 2500 W and bias power 725 W, a high selection ratio of 40: 1 was obtained.

Next, as shown in FIG. 3, a second plasma TEOS film (36) is formed on the entire surface of the substrate. In this step, a plasma CVD apparatus is used to react a gas system of O2 and TEOS to form a TEOS film of 5000 Å to 7000 Å. At this time, the second plasma TEOS film (36) does not have an overhanging shape because the base is inclined due to the provision of the sidewall oxide film (35).

Then, as shown in FIG. 4, SOG is spin-coated on the entire surface of the second plasma TEOS film (36) to fill the recesses of the second plasma TEOS film (36). (37) is formed. Then, as shown in FIG. 5, an interlayer insulating film (38) is formed by planarizing the entire surface by etching back. After that, a plasma TEOS film may be further formed on the entire surface to secure a sufficient film thickness of the interlayer insulating film (38).

As described above, according to the manufacturing method of this embodiment, since the Al wiring layer (32) is covered with the plasma Si3N4 film (33), when the side wall oxide film (35) is formed.
The Al wiring layer (32) is not exposed, and the occurrence of Al corrosion and the heavy metal contamination of the etching apparatus can be prevented. In addition, the second plasma TEOS film (3
6) does not have overhanging shape, so SOG
Remaining of the film is less likely to occur, cracks are prevented from entering the interlayer insulating film (38), and plasma TE
Since the etching rates for OS and SOG can be made equal, it is possible to form a flatter interlayer insulating film.

[0014]

As described above, according to the method of manufacturing a semiconductor device of the present invention, since the Al wiring layer is covered with the silicon nitride film, the Al wiring layer is exposed when the sidewall oxide film is formed. As a result, it is possible to prevent Al corrosion and heavy metal contamination of the etching apparatus.

Further, according to the present invention, since the sidewall oxide film of the Al wiring layer is formed, the plasma TEOS film does not have an overhanging shape, and as a result, the SOG film is less likely to remain, and the interlayer is not formed. Since cracks can be prevented from occurring in the insulating film and the etching rates for the plasma TEOS and SOG can be made equal, it is possible to form a flatter interlayer insulating film.

[Brief description of drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a fifth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example.

FIG. 7 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example.

FIG. 8 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example.

FIG. 9 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example.

FIG. 10 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example.

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example.

FIG. 12 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 13 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

Claims (3)

[Claims] 1. A step of forming an Al wiring layer on an insulating film formed on a semiconductor substrate, and a step of forming a silicon nitride film so as to cover the surfaces of the insulating film and the Al wiring layer,
A step of forming a first silicon oxide film on the entire surface, and a sidewall oxide film of the Al wiring layer is formed by completely etching the first silicon oxide film using the surface of the silicon nitride film as an etching end point detection surface. And a step of forming a second silicon oxide film on the entire surface, and SOG on the entire surface
A method of manufacturing a semiconductor device, comprising: a step of applying a film; and a step of etching back the second silicon oxide film and the SOG film. 2. A BPSG formed on a silicon substrate
Forming an Al wiring layer on the film, forming a plasma Si3N4 film so as to cover the surfaces of the BPSG film and the Al wiring layer, forming a first plasma TEOS film on the entire surface, Forming a sidewall oxide film made of plasma TEOS on the sidewall of the Al wiring layer by completely etching the first plasma TEOS film using the surface of the plasma Si3N4 film as an end point detection surface for etching;
A step of forming a second plasma TEOS film on the entire surface, a step of applying an SOG film on the entire surface, and the second plasma T
And a step of etching back the EOS film and the SOG film. 3. The method of manufacturing a semiconductor device according to claim 2, wherein an inductively coupled etching apparatus is used in the step of forming a sidewall oxide film by etching the entire surface of the first plasma TEOS film.