JPH08147999A - Test method for contents address system memory - Google Patents

Abstract

PURPOSE: To shorten the test time and to reduce the test cost by using plural kinds of checker patterns as the storage data and performing the test with coincidence retrieval for respective checker patterns. CONSTITUTION: A checker pattern inverting between 0 and 1 every bit and word is written in a memory part 16 of a contents address system memory(CAM) 10, and is made to be storage data of the memory part 16. Then, either one of even or odd bit of the retrieval data is masked by a mask register 12, and either an all one pattern or an all zero pattern is written as the retrieval data, and test by four kinds of coincidence retrieval is performed. Further, the checker pattern in which zero and one are inverted is written as the storage data, and the test by four kinds of coincidence retrieval is performed similarly. Thus, the coincidence detection of the storage data and confirmation of a mask function are performed simultaneously without depending on the bit width of the CAM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a content addressable memory (hereinafter, referred to as CAM), and more specifically, a test time can be determined without depending on the bit width or the number of words of the CAM. The present invention relates to a CAM test method that can be shortened.

[0002]

2. Description of the Related Art A CAM is a data dictionary such as a Japanese dictionary, a person's directory, a sports yearbook, etc. Data), search data and stored data (hereinafter referred to as stored data) are searched for in a single cycle, and whether or not there is data that matches the search data is stored. The memory address, the data stored in this memory address, and the like are output. For example, to give an example of a Japanese dictionary, when "semiconductor" is given as the search data, the stored data is automatically searched and the target "semiconductor: having an electric conductivity intermediate between the conductor and the insulator" is obtained. material"
It is possible to obtain output data such as

Here, the configuration and operation of a conventional CAM will be described with reference to FIGS. 3 and 4.

FIG. 3 is a block diagram of an example of a conventional CAM. This CAM 30 has a mask register 12 for invalidating a search function of predetermined bits of search data and outputting masked search data, a bit string in the horizontal direction and a word row in the vertical direction, and a mask for each word memory. A memory unit 16 that performs a match search between the search data output from the register 12 and the stored data and outputs a match search signal via the match line 14, and via the word line 18 for each word memory of the memory unit 16. A decoder unit 20 that outputs a word signal and writes or reads data to or from the word memory of the memory unit 16 designated by an input address signal, and the memory unit 1.
The encoder unit 22 encodes a memory address in which stored data matching the search data is stored according to the state of the match search signal output from the encoder 6 and outputs the encoded address as a match address signal.

In the CAM 30 described above, first, the search data input to the mask register 12 is output with the predetermined bits masked or as the input search data is output and is input to the memory section 16. Then, in each word memory of the memory unit 16, the search data and the stored data are simultaneously searched for in a single cycle,
Matching or mismatching is detected, and is input to the encoder unit 22 via the matching line 14 as a matching search signal. In the masked bits of the search data, a match with the corresponding bit of the stored data is always detected. Then, in the encoder unit 22, the memory address corresponding to the highest priority match line 14 is encoded from the match lines 14 to which the match search signal in which the match is detected is output, and is output as a match address signal. It is input to the decoder unit 20 as needed. Then, the decoder unit 2
At 0, the input address signal is decoded, the word signal corresponding to the input address signal is output, and is input to the memory section 16 via the word line 18. Finally, in the memory section 16, the word memory corresponding to the word line 18 to which the active word signal is output is accessed, and data is input or output.

Next, FIG. 4 is a configuration circuit diagram of an example of a CAM cell that constitutes a CAM memory section. The CAM cell 32 is composed of a storage unit 34 that stores storage data and a search unit 36 that performs a match search between the search data and the storage data. The storage unit 34 described above is a general SRAM cell and includes inverters 38a and 38b and transfer gates 40a and 40b. Here, the word line 18 is connected to the gate end of the transfer gate 40a, one input / output end thereof is connected to the bit line 42a, and the other input / output end thereof is connected to the input end of the inverter 38a and the output end of the inverter 38b. It is connected. Similarly, the word line 18 is connected to the gate end of the transfer gate 40b, and the input / output end on one side is the inverted bit line 4
2b, and the other input / output terminal is connected to the output terminal of the inverter 38a and the input terminal of the inverter 38b. Further, the search unit 36 uses the transfer gates 44a, 4a.
4b and a discharge transistor 46. Here, the gate ends of the transfer gates 44a and 44b are respectively connected to the inverters 38a and 38 of the storage section.
The output end of b, that is, the inverted storage data and the storage data are input, and one of the input / output ends thereof is connected to the bit line 4 respectively.
2a and the inverted bit line 42b, the other input / output terminal is short-circuited, and is input to the gate terminal of the discharge transistor 46. Further, one terminal of the discharge transistor 46 is grounded and the other terminal is connected to the match line 14.

In the CAM cell 32 described above, in order to write the storage data, after driving the storage data to the bit line 42a and the inverted storage data to the inverted bit line 42b,
The word line 18 may be driven actively. As a result, inverted storage data and storage data can be written to the output terminals of the inverters 38a and 38b, respectively. To read the stored data, the bit line 42a
The word line 18 may be driven actively after the high-impedance state of the inverted bit line 42b. As a result, the stored data can be read to the bit line 42a and the inverted storage data can be read to the inverted bit line 42b. To perform a match search between the search data and the stored data, the bit line 42a and the inverted bit line 42b are driven to the low level, the match line 14 is driven to the high level, and then the search data and the inverted bit are written to the bit line 42a. It is sufficient to drive the inverted search data on the line 42b. As a result, when a match or a mismatch is detected, a high level or a low level is output to the match line 14, respectively. In the bit for which the search function is disabled by the mask register 12 described above, the search data is stored in the bit line 42a.
Inverted search data is not driven to the inverted bit line 42b, and both the bit line 42a and the inverted bit line 42b remain driven to the low level. As a result, the bits for which the search function is disabled in the mask register 12 are always in the state of being matched.

The structure and operation of the conventional CAM have been described above. Now, a method of testing the conventional CAM will be described below. The conventional CAM test is for each C
This is performed to check whether or not there is a defective bit in the AM cell 32, and generally, the storage unit 34 of the CAM cell 32 is used.
And the test of the search unit 36 are performed separately.

In the test of the storage unit 34, a specific pattern is written into a word memory designated by an input address signal and then read out, so that the decoder unit 20, the storage unit 34 of the memory unit 16 and the like are read. The function and the connection of the word line 18, the bit line 42a, the inverted bit line 42b, etc. are tested. For example, the decoder unit 20
By inputting the input address signal to the memory unit 1,
All 6 word memories have a specific pattern, for example, all 0 pattern (word memory all bits are "0" pattern), all 1 pattern (word memory all bits are "1" pattern), checker pattern (word memory (A pattern in which "0" and "1" are exchanged for each bit and for each word) is written, and then the specific patterns written in all the word memories of the memory unit 16 are sequentially read and written in the predetermined word memory. Pattern,
Confirm that the pattern matches the pattern read from the specified word memory.

In order to avoid mutual interference between bits, the above-mentioned checker pattern is used, or, for example, after writing all 0 patterns in all word memories of the memory section 16, the input address signal is input to the decoder section 20. After inputting, writing the all 1 pattern only in the predetermined word memory of the memory section 16, reading this,
It is confirmed that the all-1 pattern written only in the predetermined word memory and the pattern read from the predetermined word memory match, and then the all-0 pattern is written again in the predetermined word memory to write all the words in the memory unit 16. A test method or the like in which the memory is returned to the all 0 pattern and this is repeated is also used.

Further, the test of the search unit 36 is performed by performing a match search between the stored data and the search data using a specific pattern, so that, for example, the search unit 36 of the encoder unit 22, the mask register 12, the memory unit 16 and the like. The function and the connection of the match line 14, the bit line 42a, the inverted bit line 42b, etc. are tested. For example, it is possible to write a specific pattern, for example, an all 0 pattern or an all 1 pattern, in all the word memories of the memory unit 16 and give the same specific pattern to the search data to detect a match, or to give a different specific pattern to the search data. It is confirmed that matching can be detected by masking with the mask register 12, or that mismatch can be detected by giving different specific patterns to the search data.

Here, the above-mentioned conventional CAM test method will be described more specifically by taking an N word × m bit CAM as an example.

All 0 patterns are written in all the word memories of the memory section 16 and the mask register 12 is set so that only 1 bit of the search data is the object of the match search. "0" is written in the bit that is, and "1" is written in all the other bits masked by the mask register 12. Then, after performing a coincidence search in all the word memories at the same time, the bit to be the subject of the coincidence search is changed and the search operation is repeated. That is, in the case of the m-bit CAM test, the above operation is repeated m times.

An example of setting the mask register 12 and the search data from the first time to the m-th time when the meaning of the bits of the mask register 12 is masked by "0" and unmasked by "1" is shown below. Mask register search data 1st time "1000 ... 0""0111 ... 1" 2nd time "0100 ... 0""1011 ... 1" 3rd time "0010 ... 0""1101..." 1 "・ ・ m-th time" 0000 ・ ・ ・ 1 "" 1111 ・ ・ ・ 0 "

In the conventional CAM test described above, a match is detected between "0" written in all word memories of the memory section 16 and "0" written in the bit to be searched for a match in the search data. , "0" written in all the word memories of the memory unit 16 and "1" written in all the other bits masked by the mask register 12 of the search data are detected to be coincident by the mask function. , Can be confirmed for each bit.

All 1 patterns are written in all the word memories of the memory section 16 and the mask register 12 is set so that only 1 bit of the search data is the object of the match search. By writing "1" in the bit that becomes, and "0" in all other bits masked by the mask register 12,
"1" written in all the word memories of the memory unit 16 and "1" written in the bit to be searched for the match of the search data are detected as coincidence and written in all the word memories of the memory unit 16. It can be confirmed for each bit that "1" and "0" written in all the other bits masked by the mask register 12 of the search data are coincidentally detected by the mask function.

When a match address signal is output from the encoder unit 22 to confirm that a match is detected, if there is no defective bit, the search data and the stored data are stored in all word memories. Since they match, it is necessary to read and check the match address signal N times each time a match search is performed. Therefore, in the N word × m bit CAM, as described above, “0” and “1” are written as the storage data, and it is confirmed that the search data “0” and “1” match each other. To do this, a test time of 2 × N × m cycles is required. In addition to the above-mentioned test, for example, a test for confirming that a mismatch is detected is required.

An example of the conventional CAM test method has been described above. However, since the conventional CAM test method uses the mask function to perform a match search for each bit, the test cycle (test time) is short. It depends on the bit width (m) of the CAM. Therefore, when the bit width of the CAM is increased, there is a drawback that the test time becomes longer accordingly. In addition, when the memory address storing the storage data that matches the search data is read and confirmed by the encoder unit, there is a problem that the test time becomes long depending on the number of words (N). . The conventional CAM test method is an effective method for confirming the presence or absence of a defective bit in a specific word at the early stage of CAM development, for example. As a shipping test, there has been a problem that such a long test time results in an increase in test cost.

[0019]

SUMMARY OF THE INVENTION The object of the present invention is to solve various problems based on the above-mentioned prior art, to use two kinds of checker patterns as stored data, and to perform four kinds of tests for each checker pattern. By performing the check, it is possible to check the match detection or mismatch check of the predetermined storage data and the mask function at the same time without depending on the bit width of the CAM, which shortens the test time and reduces the test cost. Can reduce CAM
To provide a test method of.

[0020]

In order to achieve the above object, the present invention provides a mask register for invalidating a search function of a predetermined bit of search data, and storage data written in advance, the search data and the storage. A method for testing a content addressable memory, comprising: a memory section that performs a match search with data; and an encoder section that encodes a memory address where the search data and the stored data are detected as a match and outputs a memory address signal. Then, a checker pattern in which 0 and 1 are inverted for each bit and for each word is written as the storage data of the memory unit, and then the mask register is set to mask even bits of the search data, and the search is performed. A match search between the search data and the stored data performed by writing all 1 patterns as data, Register for masking even bits of the search data, and writing an all 0 pattern as the search data to perform a match search between the search data and the stored data. Set to mask
And a match search between the search data and the stored data, which is performed by writing an all-one pattern as the search data,
And a test by four types of match search of match search between the search data and the stored data, which is set by masking odd bits of the search data in the mask register and by writing all 0 patterns as the search data. Then, as the storage data of the memory unit,
A test method for a content addressable memory is provided in which a checker pattern in which 0 and 1 of the checker pattern are inverted is written and a test is performed by the four types of match search.

Here, every time the matching search is performed, it is preferable to sequentially read all the memory address signals encoded by the encoder section to confirm that the predetermined stored data is detected as a match or a mismatch. .

Further, the content addressable memory is further provided with a test circuit for outputting a test signal indicating that predetermined storage data is detected as coincident and predetermined storage data is detected as not coincident, and the coincidence search is performed. Each time, it is preferable to confirm by the test signal that the predetermined storage data is detected as coincident or non-coincident.

[0023]

According to the CAM test method of the present invention, two types of checker patterns are used as stored data, specifically, the even bits of even words and the odd bits of odd words are "0", and the odd bits of even words. And a checker pattern in which the even bit of the odd word is "1", and a checker pattern in which the even bit of the even word and the odd bit of the odd word are "1" and the odd bit of the even word and the even bit of the odd word are "0" Using two patterns as search data, that is, an all 1 pattern and an all 0 pattern, and masking either even or odd bits of the search data by a mask register to search data for each checker pattern described above. And 4 types of match search by combination of mask register That. Therefore, according to the CAM test method of the present invention, since the checker pattern is used for the stored data, there is no mutual interference between bits and words, and the test time does not depend on the bit width of the CAM. The test time can be shortened and the test cost can be reduced. Further, since the checker pattern can be used as a normal memory test pattern, the CAM test can be efficiently performed by testing the storage unit and the search unit using the same checker pattern. Further, when the layout area has a margin, a test circuit is provided which outputs a test signal indicating that the predetermined storage data and the search data have been detected as coincident and that the predetermined storage data and the search data have not been detected as coincident. By doing so, it is possible to confirm that a match or a mismatch is detected without reading the match address signal from the encoder section, and it is possible to greatly reduce the test time without depending on the number of words in the CAM. is there.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The CAM test method of the present invention will be described in detail below with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram of a CAM to which the CAM test method of the present invention is applied. This CAM10 is
A mask register 12 for invalidating the search function of predetermined bits of the search data and outputting masked search data, and 6 bits in the horizontal direction and 6 words in the vertical direction, are provided from the mask register 12 for each word memory. The memory unit 16 that performs a match search between the output search data and the stored data and outputs a match search signal via the match line 14, and the memory unit 1.
A memory unit 1 that outputs a word signal via the word line 18 for each of the 6 word memories and is designated by the input address signal.
The decoder unit 20 that writes or reads data in the word memory 6 and the memory address in which the data matching the search data is stored is encoded according to the state of the match search signal output from the memory unit 16. The encoder unit 22 outputs as a signal, and preferably includes a test circuit 24 which is provided as a part of the encoder unit 22 and compresses a test result and outputs it as a test signal.

In the CAM 10 described above, the memory unit 1
Write the checker pattern in all 6 word memories. In the CAM 10 shown in FIG. 1, the right side of the bit string is bit 0, the left side is bit 5, the upper side of the word row is word 0, the lower side is word 5, and the even bit of the even word memory is "0" and the odd bit is A checker pattern is written in which "1", the even-numbered bit of the odd-numbered word memory is "1", and the odd-numbered bit is "0". Note that CA
Since writing the stored data to M10 takes a very long time, the storage section of the CAM cell is tested using a checker pattern, that is, the test section of the CAM cell is tested while the checker pattern is written. It is preferable to perform them at the same time because the test time can be shortened.

Then, as shown in the setting example of the mask register 12 in the same figure, all 1 patterns are written as search data and even bits are masked (in the figure, the shaded area is masked and the white area is unmasked). ) And simultaneously perform a match search in all word memories. As a result, in the even word, the odd number “1” and the search data “1” are detected as coincident, and the even bit “0” and the search data “1” are detected as coincident by the mask function. In addition, in the odd word, a mismatch between the odd bit “0” and the search data “1” is detected, and the even bit “1” is detected.
And the search data “1” are detected by the mask function. That is, if there is no defective bit, even words are detected as coincidence and odd words are detected as non-coincidence.

Then, as shown in the setting example of the mask register 12a in the figure, all 0 patterns are written as search data, even bits are masked, and a match search is simultaneously performed in all word memories. As a result, in the odd-numbered word, the odd-numbered bit "0" and the search data "0" are detected as coincident, and the even-numbered bit "1" and the search data "0" are detected as coincident by the mask function. In the even-numbered word, a mismatch between the odd-numbered "1" and the search data "0" is detected, and the even-numbered "0" is detected.
And the search data "0" are detected by the mask function. That is, if there is no defective bit, the odd words are detected as coincident and the even words are detected as not coincident.

Subsequently, as shown in the setting example of the mask register 12b in the same figure, an all-1 pattern is written as search data, the odd-numbered bits are masked, and a match search is simultaneously performed in all word memories. As a result, even-numbered bits "1" and search data "1" in the odd-numbered word are detected as coincident, and odd-numbered bits "0" and search data "1" are detected as coincident by the mask function. In the even-numbered word, a mismatch between the even-numbered bit “0” and the search data “1” is detected, and the odd-numbered bit “1” is detected.
And the search data “1” are detected by the mask function. That is, if there is no defective bit, the odd words are detected as coincident and the even words are detected as not coincident.

Then, as shown in the setting example of the mask register 12c in the figure, an all 0 pattern is written as search data, the odd bits are masked, and a match search is simultaneously performed in all word memories. As a result, in the even-numbered word, the even-numbered bit "0" and the search data "0" are detected as coincident, and the odd-numbered bit "1" and the search data "0" are detected as coincident by the mask function. In addition, in the odd word, the even bit "1" and the search data "0" are detected to be inconsistent, and the odd bit "0" is detected.
And the search data "0" are detected by the mask function. That is, if there is no defective bit, even words are detected as coincidence and odd words are detected as non-coincidence.

In the above-mentioned four types of tests, the checker pattern written in all the word memories of the memory section 16 and the data written in the bit to be searched for a match of the search data are detected as a match or a mismatch, and the memory is detected. The checker pattern written in all word memories of the unit 16 and the search data mask register 1
The fact that the data written in all the other bits masked by 2 is detected by the mask function,
It is possible to check for each bit and each word without interference between each bit and each word. Needless to say, the four types of tests described above may be performed in any order.

All the word memories of the memory section 16 have the above-mentioned checker pattern "0" and "1".
Write a checker pattern in which the even bit of the even word memory is "1", the odd bit is "0", and the even bit of the odd word memory is "0" and the odd bit is "1". Then, by repeating the above-mentioned four types of tests, it is possible to perform the test in which the coincidence or non-coincidence is detected and the logic "0" and "1" of the mask function are inverted. Also, by performing a match search by masking all the bits of the search data, it is possible to perform a test in which the stored data in all word memories and the search data are detected as a match. By performing a match search as a non-mask, it is possible to perform a test in which the stored data in all word memories and the search data are not matched.

When the CAM of N words × m bits is used in the same manner as in the conventional example, in order to confirm the coincidence detection or the non-coincidence detection, the coincidence address signal is output from the encoder unit 22 and the confirmation is performed. If there is no defective bit, the search data matches the stored data in the word memory of either the odd word or the even word. Therefore, it is necessary to read and confirm the match address signal N / 2 times each time a match search is performed. There is. For this reason, two types of checker patterns are written as stored data, and "0" and "1" of the search data are detected as coincidence and non-coincidence, and the coincidence is detected by the mask function of "0" and "1". To confirm that, 2 x 4 x N
A test time of / 2 = 4N cycles is required.

The above-mentioned 4N cycle test time is the same when the bit width is 2 bits as compared with the conventional example, and the test time is shortened when the bit width is 3 bits or more. means. That is, C of the present invention
According to the AM test method, since the test time does not depend on the memory width (m) of the CAM, the effect is great especially in the test of the CAM having a large bit width. Further, it is of course possible to confirm the coincidence detection of both logic "0" and "1" and the confirmation of the mask function, and of course, the discrepancy detection of both logic "0" and "1" which is separately performed in the conventional example. Since the confirmation can be performed at the same time, the test time can be further shortened, and it is particularly effective in reducing the test cost by using it for a shipping test in mass production.

Here, the effect of using the checker pattern for all word memories of the memory section will be described.

First, as described in the conventional example, when all 0 patterns or all 1 patterns are written in all the word memories of the memory section 16, for example, search data is used as a checker pattern and the CAM of the present invention is used.
By conducting a test by masking odd or even bits as in the test method described in (1), the test can be performed by performing four kinds of searches as in the CAM test method of the present invention. However, since the same data is written in all the word memories and a match or a mismatch is detected in all the word memories, the match address signal read from the encoder unit 22 is compared with the CAM test method of the present invention. 2 times, that is, twice the test time is required.

In the conventional CAM test method, when all 0 patterns are written in all word memories of the memory section 16, for example, all 1 patterns are used as search data and all bits are set by the mask register 12. It was necessary to separately detect the mismatch by performing the search as a non-mask. On the other hand, in the CAM test method of the present invention, by performing the above-mentioned four types of searches, not only a match but also a mismatch detection can be performed at the same time, so that the test time can be further shortened.

When an arbitrary pattern is written in all word memories of the memory section 16, two types of patterns are written in one word memory, for example, an arbitrary pattern and a reverse pattern of this arbitrary pattern are used, and all of them are used. If an inversion pattern is written in at least one of the word memories of the above, the test can be performed by performing the same four searches as in the CAM test method of the present invention. However, in the case of N word CAM, it is necessary to write the pattern N times, so it takes a very long time to write the pattern to the memory unit 16. In this case, the pattern combinations are innumerable depending on the bit width. Therefore, it is difficult to find out what kind of pattern is appropriate, that is, to find a pattern having a high failure detection rate without being affected by the interference between bits and between words, depending on the configuration of the CAM.

As already mentioned, the checker pattern can also be used as a test pattern for the memory portion of the CAM cell. Therefore, when testing the memory,
When the checker pattern is used, for example, after the test of the storage unit of the CAM cell is completed, that is, in a state where the checker pattern is stored in all the word memories of the memory unit, the checker pattern of By performing the test of the search unit of the CAM cell using the test method, the time for writing the checker pattern in all the word memories of the memory unit 16 can be omitted, and the test can be performed very efficiently. Even when an arbitrary pattern is written in the CAM, the masking is performed every other bit to perform the test as in the CAM test method of the present invention, and the matching is performed for each bit using the mask function. Although the test time can be shortened as compared with the conventional method of searching, as described above, the test time can be most effectively shortened by using the checker pattern as the pattern to be stored in the CAM memory unit. .

Next, the test circuit in the CAM shown in FIG. 1 will be described. FIG. 2 is a configuration circuit diagram of an embodiment of a test circuit used in the CAM of the present invention. The test circuit 24 includes a test signal TOUT1 of the CAM 10 having the memory unit 16 of 6 words × 6 bits shown in FIG.
A circuit for outputting TOUT2, which has an AND gate 26 to which one input end is inverted and an AND gate 28 to which the output ends of these AND gates 26 are input
It has two output circuits composed of.

Here, in one of the output circuits, AND
The match search signals output from the word memories 0, 2, and 4 are input to the inverting input terminals of the gate 26 via the match line 14, and the other input terminals are input from the word memories 1, 3, and 5, respectively. The match search signal that is output is match line 1
4, and the test signal TOUT1 is output from the output terminal of the AND gate 28. Similarly, in the other output circuit, the match search signals output from the word memories 1, 3, and 5 are input to the inverting input terminals of the AND gate 26 via the match line 14, and the other input terminal is input. The match search signals output from the word memories 0, 2, and 4 are input to each of the word memories 0 through 4, and the test signal TOU is output from the output end of the AND gate 28.
T2 is output.

In the above-described test circuit 24, the test signal TOUT1 of one output circuit is matched with the odd-numbered word memories of the memory section 16 (a high level is output to the match search signal) and is not matched with the even-numbered word memories ( A high level is output when a low level is output to the match search signal. In addition, the test signal TO of the other output circuit
In UT2, the even word memory of the memory unit 16 matches,
When the odd word memories do not match, a high level is output. In other cases, the test signal TO
Both UT1 and TOUT2 output a low level. By using this test circuit 24, it is possible to confirm that a match or mismatch is detected in a predetermined odd or even word memory in the above-described CAM test method of the present invention.

Therefore, when there is a margin in the layout area, by adding the test circuit as described above,
Since it is not necessary to read out the coincidence address signal that is coincident and detected from the encoder unit, the test time can be greatly shortened regardless of the number of words (N). The test circuit 24 is an example, and the test circuit used in the CAM test method of the present invention is
The present invention is not limited to this, and any test circuit may be configured as long as it is a test circuit that outputs a test signal capable of confirming that a match or a mismatch is detected when performing a match search.

[0044]

As described above in detail, the CA of the present invention
In the test method of M, two checker patterns are used for the stored data, all 0 patterns and all 1 patterns are used for the search data, and even or odd bits of the search data are masked by the mask register, and each checker pattern is used. Four types of tests are performed for each pattern. Therefore, according to the CAM test method of the present invention, a checker pattern can be used to perform a test without receiving mutual interference between bits and words, and the checker pattern can also be used for testing a storage unit. Therefore, both the storage unit and the search unit can be tested with the same checker pattern, which is very efficient.
Further, according to the CAM test method of the present invention, the checker pattern is used, so that the test time does not depend on the bit width. Further, since the test circuit is provided, the test time does not depend on the number of words. It can be significantly shortened to reduce the test cost.

[Brief description of drawings]

FIG. 1 is a CAM to which a CAM test method of the present invention is applied.
It is a block diagram of an example of.

FIG. 2 is a CAM of the present invention used in the CAM shown in FIG.
3 is a configuration circuit diagram of an example of a test circuit used in the test method of FIG.

FIG. 3 is a block diagram of an example of a conventional CAM.

FIG. 4 is a configuration circuit diagram of an example of a conventional CAM cell.

[Explanation of symbols]

 10, 30 CAM (content address memory) 12 mask register 14 match line 16 memory section 18 word line 20 decoder section 22 encoder section 24 test circuit 26, 28 AND gate 32 CAM cell 34 storage section 36 search section 38a, 38b inverter 40a , 40b, 44a, 44b Transfer gate 42a Bit line 42b Inverted bit line 46 Discharge transistor

Claims (3)

[Claims] 1. A mask register for disabling a search function of a predetermined bit of search data, a memory section in which storage data is written in advance and which performs a match search between the search data and the storage data, the search data and the A method for testing a content addressable memory, comprising: an encoder unit that encodes a memory address that is detected to match stored data and outputs a memory address signal, wherein the stored data in the memory unit is bit by bit and word by word. After writing a checker pattern in which 0 and 1 are inverted, the search data and the stored data are set by masking even bits of the search data in the mask register and writing an all-1 pattern as the search data. Search for a match with, mask the even bits of the search data in the mask register And a match search between the search data and the stored data, which is performed by writing an all-0 pattern as the search data, the mask register is set to mask odd bits of the search data, and the search data is set as the search data. A match search between the search data and the stored data, which is performed by writing all 1 patterns, and an odd bit of the search data is set to be masked in the mask register, and an all 0 pattern is written as the search data, A test is performed by four types of match search of the search data and the stored data, and then a checker pattern in which 0 and 1 of the checker pattern are inverted is written as the stored data of the memory unit, and the four types of the check patterns are written. It is characterized by performing a match search for The test method of address expression memory. 2. The method according to claim 1, wherein every time the matching search is performed, all memory address signals encoded by the encoder section are sequentially read to confirm that the predetermined storage data is matched or mismatched. Content of description Test method for addressable memory. 3. The content addressable memory is further provided with a test circuit for outputting a test signal indicating that predetermined storage data has been detected as a match and predetermined storage data has been detected as a mismatch, and the match search is performed. 2. The method for testing a content addressable memory according to claim 1, wherein the test signal is used to confirm that predetermined storage data is matched or mismatched.