JPH08147251A - Parallel computer - Google Patents

Abstract

PURPOSE: To improve system performance by improving network transfer throughput at the time of message transfer concerning the distributed memory type parallel computer. CONSTITUTION: Concerning the parallel computer in which plural processor nodes are provided, the respective processor nodes are equipped with CPU 102 and 112 for performing calculation processing, independent storage devices 105 and 115 and network adapters 107 and 117 for performing the message transfer with a network, the processor nodes are coupled by a network 121 and the data required for parallel processing between the processor nodes are exchanged by the message transfer, the network adapters 107 and 117 are provided with compression means for compressing message data and expansion means for expanding the message data. At the time of message transmission, a message is transferred by the network 121 after the message data are compressed by the compression means and at the time of message reception, the message is expanded by the expansion means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distributed storage type parallel computer, and more particularly to a system for improving network transfer throughput at the time of message transfer and improving system performance.

[0002]

2. Description of the Related Art A distributed storage type parallel computer has a storage device for each processor and connects the processors via a network. The data exchange required for parallel processing is realized by exchanging messages via the network. The performance of such a computer requires processor performance and network performance commensurate with it.

The amount of calculation performed in each processor and the amount of data transfer to another processor depend on the application to be executed. It is necessary to shorten the message communication time in the network compared to the calculation time in the processor. Especially in scientific and engineering calculations, the amount of data exchanged with other processors is large, and transfer throughput closer to main memory access is required for message transfer.

However, since the path between the CPU and the main memory is close in distance, it can be accessed at high speed. However, in the network coupled with other processors, the transmission path is long and the transfer pitch is high due to the rounding of the waveform. Difficult to do. In addition, it is difficult to increase the number of signal lines because there are many cases of connecting with cables. Due to such restrictions, the network throughput tends to be lower than the main storage throughput.

Access to an input / output device such as a disk device is solved by using a compression technique as follows.

Image data stored in the disk device
A moving image display system for displaying in real time will be described. The image data is very large, and if it is stored on the disk as it is, a large amount of disk capacity is required.
Further, since the read speed of the disk device is slower than the display speed of the moving image, it cannot be displayed in real time. So, store the compressed image data on the disk,
The compressed image data read from the disk is decompressed by dedicated hardware or software, transferred to the frame buffer, and displayed on the screen. Image data can be compressed with a very high efficiency by utilizing the fact that the data is very similar in the X-direction, Y-direction, and time-axis direction of the image, and can be compressed to several tenths to a hundredth. Due to this high compression rate, it is possible to compensate for the delay in disk access, and it is possible to read image data required for moving image reproduction from the disk in real time. An example of applying the compression technology to image display and transmission is described in the "Technology of Image Compression Technology that Produced HDTV / CD-I / Facsimile".

There are two compression schemes, one belonging to the lossless coding scheme and the other belonging to the lossy coding scheme. The lossless coding method can restore the original data as it is when it is coded and then decoded. However, the compression rate of this method is not so high that it can be compressed only to half to several times. The lossy coding scheme is not the same as the original data when decoded. This is suitable for cases where image data and audio data cannot be combined into the same data but have a high compression rate and can be combined into similar data. This method can compress from a few tenths to a hundredth. In the above video display system example, JPE cannot be decrypted to the original data.
A lossy encoding method such as G, MPEG is used.

[0008]

In a parallel computer having a plurality of processors and connecting them through a network, the network transfer speed between the processors affects the system performance. The path between the CPU and the main memory can be accessed at high speed because the distance is short, but it is difficult to increase the transfer pitch in the network coupled with other processors due to the long distance of the transmission path and the rounding of the waveform. In addition, it is difficult to increase the number of signal lines because the cables are often connected. Due to such restrictions, the network throughput tends to be lower than the main storage throughput. Although the transfer rate of the network can be improved by increasing the number of signal lines and using expensive drivers and cables, the system becomes expensive.

Further, when the system performance is desired to be upgraded, the system performance cannot be improved simply by replacing the CPU with a high speed version because the network performance remains the same and the message transfer overhead increases. At the same time as the processor, network performance must be changed to a high-speed version to improve system performance.

[0010]

In a parallel computer having a plurality of processors and connecting them through a network, when transferring data for operation to another processor, the transfer data of a message is compressed and expanded in the processor. Provide a function. The sending processor compresses the data of the message to be transferred and transfers the compressed data to the network as a message. The receiving processor receives the message data, decompresses it, restores it to the original data, and uses it for the calculation.

[0011]

In a parallel computer having a plurality of processors and connecting them via a network, a function of compressing / expanding the transfer data when the data for operation is transferred to another processor is added. The transfer data amount of the actual message is reduced, and as a result, the transfer throughput is improved. The improved transfer throughput improves system performance.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 shows the configuration of the parallel computer of the embodiment.

In FIG. 1, reference numerals 101 and 111 denote processors forming a parallel computer. The contents of 101 and 111 are the same, and they perform independent processing such as independent operations. Reference numeral 121 denotes a network, which performs data transfer between processors and synchronization processing.

CPUs 102 and 112 execute programs such as arithmetic processing. Reference numerals 103 and 113 are hardware for performing calculation. 104 and 114 are registers for temporarily storing data to be calculated and calculation results. Reference numerals 105 and 115 are main memories for storing operating systems, applications, data, etc., which are programs executed by the CPU. 106 and 116 are main memory controllers for controlling the main memories 105 and 115, and CPUs 102 and 112.
Access to the main memory 105, 115 from.
It also transfers the data in the main memory 105, 115 to the network or receives the data from the network and writes the data in the main memory. 107 and 117 are network adapters that request transmission data from the main storage controllers 106 and 116 to send messages to the network 121, and write received data of messages from the network 121 to the main storage controllers 106 and 116 to perform network transmission / reception processing. Do. The network adapter has compression / expansion logic 108, 118. Arrows 131,132,133,141,142,14
3, 151 indicates a data flow when data is transmitted from the processor A 101 to the processor B 111 via the network 121.

FIG. 2 shows processors A 201 through B 21.
FIG. 6 is a diagram for explaining a data flow when data is transferred to 1. 201 and 211 are processors, which have resources for performing arithmetic processing. 202 and 212 include programs and calculation data for executing calculation processing by an application. 203 and 213 are operation data of the application and include a global data area that needs to exchange data with other processors. 204
Is a buffer for transmission and is a buffer area that is temporarily stored when data is transferred to another processor. The arrow 205 indicates the movement of data from the operation data 203 of the application A 202 to the transmission buffer 204, and the memory copy is performed by the transmission routine. The arrow 221 indicates the movement of data from processor A to processor B,
The message is transferred through the network and the data is transferred to the reception buffer 214 of the processor B 211. 215
Indicates the movement of the array data 213 of the application A 212 of the same 211 from the reception buffer 214 of the processor B 211, and the memory copy is performed by the reception routine.

When the send routine is called in order for the application A 202 to send the operation data 203 to the application A 212 of the processor B 211, the send routine copies the data to the send buffer as indicated by an arrow 205. 204
After copying the data to the send buffer, the network
Start transferring data to the other processor, processor B 211, via 221. The transmission routine is the transmission buffer 204
The process ends when the data is transferred to the application A 202, and the application A 202 on the processor A 201 side starts the next arithmetic processing. When the data is sent from the network 221, the processor B 211 stores the received data in the reception buffer 214. Application A 212 of processor B 211 is processor A 20
When the calculation data sent from 1 is required, the application A212 calls the reception routine. The receive routine confirms that the data has arrived in the receive buffer 214, and if so, the receive buffer 2 of the processor B 211.
Copy from 14 to the calculation data area 213 of the application A 212.

First, the procedure of data transfer between processors in the prior art will be described with reference to FIG. Arrows 131,1 in Figure 1
Reference numerals 32, 133, 141, 142, 143, and 151 indicate data flows when a message is transmitted from the processor A 101 to the processor B 111 via the network 121. The calculation data 203 to be transmitted is stored in the main memory 105. When the application A 202 calls the transmission routine, the transmission routine causes the CPU 102 to read the data of the operation data 203 in the main memory 105 as indicated by an arrow 205, and the register 10 as indicated by an arrow 131.
Store in 4. Next, the CPU 102 writes in the transmission buffer 204 as indicated by the arrow 132. This operation is performed for all the operation data to be transmitted. When the CPU 102 finishes copying to the transmission buffer 204, it activates the network adapter 107. When activated, the network adapter 107 requests the main memory controller 106 for the data in the transmission buffer 204 stored in the main memory 105, and the data is transferred to 107 as indicated by arrow 133. Then the network adapter 107,
Send data to network 121 like
Transfer data to 111. Compression / expansion logic 10
Do not go through 8,118. Upon receiving the data from the network 121, the network adapter 117 of the processor B 111 writes the received data in the reception buffer 214 of the main memory 115 through the main memory controller 116 as indicated by an arrow 143. When the data is required, the application A 212 on the processor B 111 side confirms whether the data has arrived in the reception buffer 214, and if it has arrived, the CPU 112 reads it and stores it in the register 114 in the CPU 112 as indicated by the arrow 141. To be done. Next, the CPU 112 displays the application of the main memory 115 as shown by arrow 142.
Write to the calculation data area 213 of A212. The above is the data transfer procedure from the processor A 101 to the processor B 111 of the conventional technique.

In the case of the present invention, the network adapter 107,
117 has compression / expansion logic, which sends out compressed data at the time of network transmission and expands it at the receiving side. This behavior 10
Perform at 8,118. At the time of transmission, the network adapter requests the transmission data from the main storage controller 106, and reads the transmission data from the transmission buffer 204 of the main storage 105 as indicated by the arrow 133. The data is compressed by the compression / expansion logic 108 and a message is transmitted to the network 121 as indicated by an arrow 151. When the data arrives at the network adapter 117 of the processor B 111, the compression / expansion logic 118 decompresses the reception data and writes it in the reception buffer 214 of the main memory 115. This method uses compression / expansion logic 1 for network adapters 107 and 117.
The software may be the same as that of the prior art, only by adding 08,118.

Further, instead of the compression / expansion by the compression / expansion logic 108, 118, the compression may be performed by the CPU. In Figure 1, the arrow 131 indicates the CPU
After storing the data in the register 104 of 102, the data is written in the transmission buffer 204 of the main memory 105 as indicated by the arrow 132. Instead of this, the arithmetic unit 103 is used to compress the data by the program and the transmission of the main memory 105 is performed. Store in buffer 204.
Then, on the processor B 111 side, an arrow 141 indicates the register 11
After being stored in 4, the data is decompressed by the program using the arithmetic unit 113 instead of the arrow 142 and stored in the arithmetic data area 213 of the main memory 115. By compressing / expanding the data in this way, the paths 132, 133, 151, 143, 141 can be transferred with a higher throughput than the physical transfer width.

This system has a large software overhead because the CPU expands and compresses it, but it can be realized without providing special hardware for compression and expansion. Further, by compressing and transferring the data, the buffer usage amount of the transmission buffer 204 and the reception buffer 214 is reduced, and the buffer capacity can be reduced.

FIG. 3 illustrates a message output to the network 121. FIG. 3 (1) shows a conventional message, and FIG. 3 (b) shows a packet of the present invention. In FIG. 3A, 301 and 302 are one message, which is composed of a message header 301 and transfer data 302.

302 is the data that the application transfers from the processor A to the processor B, and the message header 301 is the data of 302, which is the application A of the processor B.
It contains information for forwarding to 212. The message header 301 stores a processor address for transfer to the partner processor, a main memory address of the partner processor, a transfer data length, OS process information, and the like. Also, error correction information is included in the message header. The message header has important information for identifying the message in this way, and identifies the message when a failure occurs during message transmission, and transmits it without compression to facilitate error handling. By having the error identification information in the message header, it is possible to correct a data error due to a message failure and restore the transferred data. Even if the message failure is severe and the compressed transfer data cannot be decompressed, the uncompressed message header information can be used to report damage information to the sending processor and retransmit the message. , Can improve the reliability of message transfer.
By not compressing the message header, performance is slightly reduced, but error handling when a failure occurs becomes easier.

Reference numerals 303 and 304 denote the next messages. The message header 303 and the transfer data 304 are followed by the messages 305 and 306, which are sequentially transferred. FIG. 3 (b) shows the message of the present invention, which corresponds to the prior art message of (a), 301 and 311, 302 and 312, 303 and 313, 304 and 314, 305 and 3.
15,306 and 316 correspond respectively. The message headers 311, 313, 315, 317, 319 are output to the network as they are without being compressed. Since the transfer data 312, 314, 316, 318, 320 are compressed by the compression / expansion logic 108, they can be transferred on the network in a shorter time than the conventional technique, and the network throughput is improved.

By thus compressing the data, the throughput can be effectively improved, and the performance of the inter-processor transfer can be improved. A cheaper network can be used and the cost of the system can be reduced. The LZW algorithm is an example of a compression / expansion method belonging to the lossless encoding method, which is already used in personal computers.

[0025]

In a parallel computer having a plurality of processors and connecting them via a network, a function of compressing / expanding the transfer data when transferring message data for operation to another processor is added. The amount of data transferred to transfer the message to the network is reduced, resulting in improved transfer throughput. The improved transfer throughput improves system performance.

Since the actual throughput is high even if the physical throughput is low, a slower and cheaper network can be used and the system cost can be reduced.

High-speed CP with the same network performance
By replacing with U and adding a compression function, the performance of both processor calculation performance and network message transfer performance is improved. When upgrading the system performance, the system performance can be improved without replacing the processor and replacing the network.

[Brief description of drawings]

FIG. 1 shows the configuration of a computer in an embodiment of the present invention.

FIG. 2 illustrates an outline of data transfer between processors that occurs when performing parallel calculations in the embodiment of the present invention.

FIG. 3 is an explanation of a message of message transfer according to the embodiment of the present invention.

[Explanation of symbols]

101 ... Processor (Processor A), 102 ... CPU, 10
3 ... arithmetic unit, 104 ... register, 105 ... main memory, 106 ...
Main memory controller, 107 ... Network adapter,
108 ... compression / expansion logic, 111 ... processor (processor
B), 112 ... CPU, 113 ... Arithmetic unit, 114 ... Register,
115 ... Main memory, 116 ... Main memory controller, 117 ...
Network adapter, 118 ... Compression / expansion logic, 121 ...
Network, 131 ... Data flow when main memory is read, 132 ... Data flow when main memory is written, 133 ... Data flow from main memory to network adapter during network transmission, 141 ... Data when main memory is read Flow, 142 ... Data flow at main memory write, 143 ... Data flow from network adapter to main memory at network reception, 151 ... Network message flow, 201 ... Processor (processor A), 202 ... Application (Application A), 203 ... Operation data area, 204 ... Transmission buffer, 205 ... Copy operation from operation data area to transmission buffer, 211 ... Processor (processor B), 212 ... Application (application
A), 213 ... Operation data area, 214 ... Reception buffer, 21
5… Copy operation from receive buffer to operation data area, 2
21 ... Network transfer operation, 301, 303, 305 ... Prior art message header (uncompressed), 302, 304, 306 ... Prior art transfer data (uncompressed), 311, 313, 315, 317, 319 ... Inventive message header (uncompressed), 312, 314, 316, 318, 320 ... Invented transfer data (compressed), 351 ... Prior Art Message A, 352
... Conventional message B, 353 ... Conventional message C,
361 ... Message of the present invention A, 362 ... Message of the present invention
B, 363 ... Inventive message C, 364 ... Inventive message D, 365 ... Inventive message E.

Claims (5)

[Claims] 1. A plurality of processor nodes comprising a plurality of processor nodes each comprising an instruction processor (hereinafter abbreviated as CPU), a storage device, and a network adapter for transferring a message between the network and a network connecting the processor nodes. In a parallel computer that performs the data exchange required for parallel processing by means of message transfer, the amount of data in the message is reduced before the message is sent to the network while retaining the information in the original data (hereinafter, the original information The reduction of the amount of data while holding the above is referred to as compression), and a message including the compressed data is transferred to the network. 2. The parallel computer according to claim 1, wherein a message containing compressed data is received from a network and the data of the message is expanded. 3. The parallel computer according to claim 1, wherein the message data is compressed before the message is transmitted to the network, the message including the compressed data is transferred to the network, and the message is received after the message is received. A parallel computer characterized by expanding data. 4. The parallel computer according to claim 1, wherein each network adapter has a compression device for compressing data and a decompression device for decompressing the data, and the message is compressed by the compression device before the message is transmitted to the network. A parallel computer, which compresses data, transfers a message including the compressed and reduced data to a network, and decompresses data of the message by a decompression device after receiving the message. 5. The parallel computer according to claim 1, wherein before the message is transmitted to the network, the data of the message is compressed by the CPU, the message including the compressed and reduced data is transferred to the network, and the message is transmitted. A parallel computer characterized by decompressing message data by the CPU after receiving.