JPH08146095A - Semiconductor device - Google Patents

Abstract

PURPOSE: To load a logical LSI device with a large number of measuring elements having characteristics almost the same as those off a substrate element becoming an object of characteristic evaluation by arranging a characteristic measuring part within an effective region of a semiconductor substrate and separately providing the pad of a measuring power supply and to enable a characteristic measuring test after the cutting of a chip to be performed. CONSTITUTION: A characteristic measuring part TEG containing measuring elements subjected to the characteristic evaluation of a fundamental element is arranged, for example, in the effective region containing four corners of a semiconductor substrate. The supply pad for supplying a measuring power supply to the measuring part TEG is provided separately from the pad for supplying an operation power supply to an internal circuit. By this constitution, a large number of the measuring elements having characteristics the same as those of the fundamental element becoming an object of characteristic evaluation can be mounted on a logical LSI device. A characteristic measuring test can be executed over various items without exerting effect on the constitutional elements of the internal circuit and the operation thereof and a characteristic measuring test for analyzing inferiority after the cutting of a chip can be also performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, for example, a large-scale logic integrated circuit device including a plurality of modules and a technique particularly effective for use in evaluating the characteristics thereof.

[0002]

2. Description of the Related Art A MOSFET (metal oxide semiconductor type field effect transistor. In this specification, a MOSFET is used as a general term for an insulated gate type field effect transistor) is used as a basic element and is used in a central processing unit, a random access memory or the like. There are large scale logic integrated circuit devices that include multiple modules. In these large-scale logic integrated circuit devices and the like, characteristic evaluations of basic elements are performed during development and mass production, and based on the results, product performance confirmation, characteristic improvement, defect analysis, etc. are realized. In a conventional large-scale logic integrated circuit device or the like, a characteristic measuring unit T including a measuring element for characteristic evaluation
The EG is not in the effective area of the semiconductor substrate (chip) on which the large-scale logic integrated circuit device or the like is formed, but as shown in FIG. 4, for example, a cutting (dicing) area of the wafer WAF, that is, an empty area between the chips CHP. It is not used after cutting the chip.

[0003]

However, as the scale and performance of semiconductor integrated circuits have increased and the number and types of measuring elements required for characteristic evaluation of basic elements have increased, conventional large-scale logic has been adopted. It has been clarified by the inventors of the present application that the following problems occur in integrated circuit devices and the like. That is, in a conventional large-scale logic integrated circuit device,
As described above, since the characteristic measuring unit TEG is formed not in the effective area of the semiconductor substrate but in the cutting area of the wafer, it is possible to configure the large-scale logic integrated circuit device, etc. Differences occur between the characteristics and the characteristics of the measuring element arranged in the cut area of the wafer, which impairs the reliability of the characteristic measurement test. Further, as is well known, the cutting region provided between the chips of the wafer has a small width of about a hundred and several tens of micrometers (micrometers), so that a large number of measuring elements including pads cannot be arranged. Limits the number of characteristic measurement tests that can be performed. Furthermore, since the characteristic measuring unit TEG is arranged in the cutting region of the wafer and cannot be used after cutting the chip, the characteristic measuring test for failure analysis or the like cannot be carried out after assembling, which results in the large-scale logic integrated circuit device. It hinders efficient development.

An object of the present invention is to mount a large number of measuring elements having substantially the same characteristics as the basic element to be evaluated in a large-scale logic integrated circuit device, etc., and perform a characteristic measurement test after cutting the chip. Is to enable. Another object of the present invention is to improve the reliability of the characteristic measurement test of a large-scale logic integrated circuit device or the like and solve the limitation on the number of measurement items thereof, thereby making the development of the large-scale logic integrated circuit device efficient. .

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor device such as a large-scale logic integrated circuit device having a predetermined internal circuit for realizing its main function, a characteristic measuring section including a measuring element used for characteristic evaluation of a basic element is provided in a semiconductor substrate. Eg 4
The pad for arranging in the effective region including the corner and supplying the measuring power supply to the characteristic measuring section is provided separately from the pad for supplying the operating power supply to the internal circuit.

[0007]

According to the above-mentioned means, a large number of measuring elements having almost the same characteristics as the basic element to be evaluated can be mounted on a large-scale logic integrated circuit device, etc. The characteristic measurement test can be carried out over various items without affecting the operation, and the characteristic measurement test for defect analysis etc. after chip cutting can be enabled. As a result, it is possible to improve the reliability of the characteristic measurement test of a large-scale logic integrated circuit device or the like and solve the limitation on the number of measurement items, and to efficiently develop the large-scale logic integrated circuit device or the like.

[0008]

1 is a block diagram of an embodiment of a large-scale logic integrated circuit device LSI to which the present invention is applied. 2 shows a board layout diagram of one embodiment of the large-scale logic integrated circuit device LSI of FIG. 1, and FIG. 3 shows a characteristic measuring unit included in the large-scale logic integrated circuit device LSI of FIG. A layout of one embodiment of TEG1 is shown. Based on these figures, the large-scale logic integrated circuit device L of this embodiment will be described.
The outline and characteristics of the SI configuration and arrangement, and the characteristic measurement test will be described. The large-scale logic integrated circuit device LSI of this embodiment is a so-called CMOS in which P-channel and N-channel MOSFETs are combined.
A plurality of (complementary MOS) circuits are formed on a single wafer made of single crystal silicon. Further, in the following description, the vertical and horizontal directions on the semiconductor substrate are represented by the positional relationship of FIGS. 2 and 3. Further, the following description regarding the characteristic measuring units TEG1 to TEG6 will be mainly performed on the characteristic measuring unit TEG1, but the other characteristic measuring units TEG2 to TEG6 have the same configuration and arrangement as those described above, and therefore should be analogized. .

In FIG. 1, the large-scale logic integrated circuit device LSI of this embodiment is not particularly limited, but the large-scale logic integrated circuit device L has a central processing unit CPU as a basic constituent element.
A logic unit LC which is an internal circuit for realizing the main function of SI and six characteristic measuring units TEG1 to TEG6 are provided. Of these, the central processing unit C that constitutes the logic unit LC
The PU has a multiplier MULT, a read only memory ROM, a random access memory RAM, and a PU via an internal bus.
Interface control unit IFC and input / output port IO
Are combined. The logic unit LC including the above modules includes a power supply voltage supply terminal, that is, a power supply voltage supply pad VCC.
High-potential side operating power supply via, for example + 5V (volt)
Is supplied with a power supply voltage VCC of 0 V, and a ground potential VSS of 0 V, which is a low-potential-side operation power supply, is supplied via a ground potential supply terminal, that is, a ground potential supply pad VSS. Also, the logical unit L
Input / output port IO constituting C is supplied with m-bit input data via data input terminals, that is, data input pads DI1 to DIm, and its n-bit output data is supplied to data output terminals, that is, data output pads DO1 to DI1. D
It is sent to the outside of the large-scale logic integrated circuit device LSI via On.

The input / output port IO of the logic unit LC is composed of four input / output ports IO1 to IO4 as will be described later. The external device of the large-scale logic integrated circuit device LSI and its internal bus, that is, the central processing unit CPU. Alternatively, mediation of data exchange with the interface control unit IFC or the like is performed. on the other hand,
The central processing unit CPU performs step operations according to a control program stored in the read-only memory ROM, executes predetermined logical operation processing, and controls / controls each unit of the logic unit LC. Further, the multiplier MULT executes a part of the logical operation processing of the central processing unit CPU, and the random access memory RAM is the central processing unit C.
The calculation result of the PU and the multiplier MULT, data exchanged with an external device, and the like are temporarily stored. Further, the read-only memory ROM stores control programs and fixed data necessary for the step operation of the central processing unit CPU, and the interface control unit IFC centrally controls the external device and the logic unit LC of the large-scale logic integrated circuit device LSI. Processor C
It controls a series of data transfer between the PU and the random access memory RAM.

On the other hand, the characteristic measuring units TEG1 to TEG6 are
AC of the large-scale logic integrated circuit device LSI, that is, a combination of a predetermined number of measurement devices for evaluating the characteristics of the MOSFET, which is a basic device of the logic unit LC, and a plurality of measurement devices. Each includes a test circuit such as a ring oscillator for evaluating the (alternating) characteristics. Of these, the characteristic measuring unit TEG1 is supplied with a measurement power supply voltage TVC1 which is a high-potential-side measurement power supply via a measurement power-supply voltage supply pad TVC1 and a low-potential side measurement via a measurement ground potential supply pad TVS1. A measurement ground potential TVS1 that is a power source for the power supply is supplied. Further, a predetermined measurement control signal TC1 is supplied via the measurement control pad TC1 and test input signals TI11 to TI12 are supplied via the measurement input pads TI11 to TI12, and the test output signals TO11 to TO12 are It is output via the measurement output pads TO11 to TO12.

Similarly, the characteristic measuring units TEG2 to TEG6 have corresponding measuring power supply voltage supply pads TVC2 to TV.
Power supply voltage for measurement T which is a power supply for measurement on the high potential side via C6
VC2 to TVC6 are respectively supplied, and the measurement ground potentials TVS2 to TVS6, which are low-potential-side measurement power supplies, are supplied via the corresponding measurement ground potential supply pads TVS2 to TVS6. In addition, predetermined measurement control signals TC2 to T are transmitted via corresponding measurement control pads TC2 to TC6.
C6 are respectively supplied and corresponding measurement input pads TI21 to TI22 to TI61 to TI62.
Via test input signals TI21 to TI22 to TI6
1 to TI62 are respectively supplied, and the test output signal T
O21 to TO22 to TO61 to TO62 are measurement output pads TO21 to TO22 to TO61 to TO62.
Is output via.

When the large-scale logic integrated circuit device LSI is under the characteristic measurement test, the measurement power supply voltage supply pads TVC1 to TVC6 and the measurement ground potential supply pads TVS1 to TVS6 and the measurement input pad of the characteristic measurement units TEG1 to TEG6 are measured. TI11 to TI12 to TI61 to TI62 and measurement output pads TO11 to TO12 to TO61
~ TO62 is coupled to an external test device via a predetermined probe card. At this time, the characteristic measuring unit TEG1 to
Each of the measuring elements constituting the TEG6 is connected to a corresponding measuring power supply voltage supply pad TVC1 to TVC from an external test apparatus.
6 and ground potential supply pads TVS1 to TVS for measurement
Power supply voltage for measurement TVC1 to TVC supplied via 6
6 and the ground potentials TVS1 to TVS6 for measurement as the power source for the measurement, and selectively activated or operated in accordance with the measurement control signals TC1 to TC6 supplied from the external test equipment through the corresponding measurement control pads TC1 to TC6. To be in a state. Then, test input signals TI11 to TI12 to T supplied from an external test apparatus via the measurement input pads TI11 to TI12 to TI61 to TI62.
Predetermined test output signal TO11 based on I61 to TI62
To TO12 to TO61 to TO62 are selectively formed, and measurement output pads TO11 to TO12 to TO6 are formed.
1 to TO62 to send to an external test device.

The central processing unit CPU that constitutes the logic unit LC is not particularly limited, but as shown in FIG. 2, most of the central portion of the semiconductor substrate SUB on which the large-scale logic integrated circuit device LSI is formed. Will be occupied. A multiplier MULT is arranged in the lower left part of the central processing unit CPU,
An interface control unit IFC is arranged in the lower right part thereof. A random access memory RAM is arranged in the upper left part of the central processing unit CPU, and a read only memory ROM is arranged in the upper right part thereof. Further, a part of the input / output port IO divided into four, that is, the input / output port IO1 is arranged along the upper side of the semiconductor substrate SUB above the random access memory RAM and the read only memory, and the read only memory ROM and the interface control are provided. The semiconductor substrate SU is provided on the right side of the unit IFC, the lower part of the multiplier MULT and the interface control unit IFC, and the left part of the random access memory RAM and the multiplier MULT.
Another part of the input / output port IO divided into four along the right side, the lower side, and the left side of B, that is, the input / output ports IO2, I
O3 and IO4 are arranged respectively.

In this embodiment, the input / output ports IO1 to IO4 are arranged at the four corners of the semiconductor substrate SUB along the four sides thereof to form empty areas. The portions TEG1 to TEG4 are arranged together with the corresponding pads. Also,
A space is inevitably created between the random access memory RAM and the read-only memory ROM due to the layout design. In this space, two characteristic measuring units T are used.
EG5 and TEG6 are arranged. That is, in the large-scale logic integrated circuit device LSI of this embodiment, the characteristic measuring sections TEG1 to TEG6 including the measuring elements for the characteristic evaluation of the MOSFET, which is the basic element, should be arranged with the respective parts of the logical section LC originally. Since it is arranged in the effective region of the semiconductor substrate SUB, the characteristics of the measuring element can be brought close to the characteristics of the basic element such as MOSFET, and the reliability of the characteristic measurement test can be improved.

By the way, characteristic measuring units TEG1 to TEG6.
Although not particularly limited, each includes six measuring elements TE1 to TE6 arranged substantially in the center thereof, as represented by the characteristic measuring unit TEG1 in FIG. These measurement elements are MOSs that are basic elements of the logic unit LC.
It is composed of a test circuit such as a MOSFET that is formed as a single unit corresponding to the FET or a ring oscillator that is formed by combining a plurality of CMOS inverters. The characteristics of the MOSFET that is the basic element of the logic unit LC and the large-scale logic integrated circuit device LSI It is subjected to a characteristic measurement test for evaluating the AC characteristic. A measurement control pad TC1 and measurement input pads TI11 and TI12 are arranged above the measurement elements TE1 to TE6. Further, on the left side thereof, a measurement output pad TO11 and a measurement power supply voltage supply pad TVC are provided.
1 is arranged, and a measurement output pad TO1 is provided on the right side thereof.
2 and the ground potential supply pad TVS1 for measurement are arranged. As a result, the large-scale logic integrated circuit device L of this embodiment is
The SI is provided with a total of 36 measuring elements and a total of 42 test pads, which makes it possible to solve the limitation on the measurement items of the characteristic measurement test.

In the large-scale logic integrated circuit device LSI of this embodiment, as described above, the characteristic measuring units TEG1 to TEG are used.
Corresponding to EG6, in other words, independently of the power supply voltage supply pad VCC and the ground potential supply pad VSS for supplying the operating power to the logic part LC, the individual power supply voltage supply pads for measurement TVC1 to TVC6 and the measurement are provided. Grounding potential supply pads TVS1 to TVS6 are provided, which allows the logic unit LC and the characteristic measuring units TEG1 to
As a result, the TEG 6 and the TEG 6 are electrically and logically separated from each other. Therefore, for example, a high voltage that causes breakdown of the measuring element without affecting the constituent elements of the logic section LC and the operation thereof can be applied to the characteristic measuring sections TEG1 to TEG.
Since the voltage can be applied to the EG6, the characteristic measurement test of the large-scale logic integrated circuit device LSI can be performed over various items.

On the other hand, as described above, the large-scale logic integrated circuit device LSI of this embodiment is formed on a single wafer by a plurality of chips, and is cut at a cutting region provided between semiconductor substrates, that is, between chips. Although they are individual chips, by disposing the characteristic measuring units TEG1 to TEG6 in the effective region of the semiconductor substrate SUB, each characteristic measuring unit can be used even after the chip is cut. Therefore, of course, the characteristic measurement test in the wafer state before chip cutting is performed. Even after the chip cutting is performed and the large-scale logic integrated circuit device LSI is assembled as a product, the package is partially removed. A characteristic measurement test for failure analysis or the like can be carried out, whereby the development of a large-scale logic integrated circuit device LSI can be made efficient and the development period thereof can be shortened.

The operational effects obtained by the above embodiment are as follows. That is, (1) in a semiconductor device such as a large-scale logic integrated circuit device having an internal circuit for realizing its main function, a semiconductor substrate is provided with a characteristic measuring unit including a measuring element used for characteristic evaluation of a basic element. For example, by arranging it in an effective area including four corners, it is possible to provide a large-scale logic integrated circuit device or the like with a large number of measuring elements having substantially the same characteristics as the basic element to be evaluated. To be (2) According to the above item (1), it is possible to easily perform the characteristic measurement test for failure analysis even after the chip is cut and the large-scale logic integrated circuit device or the like is assembled as a product. Is obtained.

(3) In the above items (1) and (2), a pad for supplying a measuring power source to the characteristic measuring section is provided separately from a pad for supplying an operating power source to the internal circuit. Thus, it is possible to perform a characteristic measurement test over various items because a high voltage that can cause breakdown of the measuring element can be applied without affecting the constituent elements of the internal circuit and its operation. Is obtained. (4) According to the above items (1) to (3), the reliability of the characteristic measurement test of the large-scale logic integrated circuit device, etc. is improved, and the limitation on the number of measurement items is lifted to develop the large-scale logic integrated circuit device. The effect that the efficiency can be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the number of characteristic measuring units provided in the large-scale logic integrated circuit device LSI and the number of measuring input pads and measuring output pads provided corresponding to each characteristic measuring unit are as follows.
It can be set arbitrarily. In addition, the large-scale logic integrated circuit device LS
The logic unit LC that realizes the main function of I can have an arbitrary block configuration, and its bus configuration and pad configuration are also arbitrary. In FIG. 2, the arrangement of the logic part LC and each part thereof is not restricted by this embodiment, and the arrangement and shape of the characteristic measuring parts TEG1 to TEG6 are also arbitrary.
In FIG. 3, the characteristic measuring units TEG1 to TEG6 can each include an arbitrary number of measuring elements, and the arrangement and shape of the measuring elements and pads are also arbitrary.

In the above description, the case where the invention made by the present inventor is mainly applied to a large-scale logic integrated circuit device which is a field of use as the background has been described, but the invention is not limited to this. The present invention can also be applied to various gate array integrated circuits, memory integrated circuits, etc., which are provided with similar measurement elements or characteristic measurement units. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor device that requires at least a measuring element for evaluating the characteristics of basic elements and a system including such a semiconductor device.

[0023]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor device such as a large-scale logic integrated circuit device having a predetermined internal circuit for realizing its main function, a characteristic measuring section including a measuring element used for characteristic evaluation of a basic element is provided in a semiconductor substrate. For example, by arranging it in an effective area including four corners, and providing a supply pad for supplying a measurement power supply to the characteristic measuring section separately from a supply pad for supplying an operating power supply to an internal circuit, A large number of measuring elements having almost the same characteristics as the basic elements to be evaluated can be mounted on a scale logic integrated circuit device, etc., and various items can be implemented without affecting the internal circuit constituent elements and their operation. The characteristic measurement test can be performed over the entire range, and the characteristic measurement test for defect analysis and the like after cutting the chip can also be enabled. As a result, it is possible to improve the reliability of the characteristic measurement test of a large-scale logic integrated circuit device and solve the limitation on the number of measurement items, to improve the efficiency of development of a large-scale logic integrated circuit device and shorten the development period.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a large-scale logic integrated circuit device to which the present invention is applied.

FIG. 2 is a board layout diagram showing an embodiment of the large-scale logic integrated circuit device of FIG.

FIG. 3 is a layout diagram showing an embodiment of a characteristic measuring unit included in the large-scale logic integrated circuit device of FIG.

FIG. 4 is a layout diagram showing an example on a wafer of a conventional large-scale logic integrated circuit device having a characteristic measuring unit.

[Explanation of symbols]

LSI ... Large-scale logic integrated circuit device, LC ... Logic unit, CPU ... Central processing unit, MULT ... Multiplier, ROM ... Read-only memory, RAM ...
Random access memory, IFC ... Interface control unit, IO ... Input / output port, DI1 to DIm ...
Data input pads, DO1 to DOn ... Data output pads, VCC ... Logic part power supply voltage supply pads, V
SS ... Ground potential supply pads for logic part, TEG1 to T
EG6 ... Characteristic measuring section, TC1 to TC6 ... Measuring control pad, TI11 to TI12 to TI61 to TI
62 ... Measurement input pad, TO11 to TO12 to TO61 to TO62 ... Measurement output pad, TVC
1 to TVC6 ... Measuring power supply voltage supply pad, TVS
1-TVS6 ... Ground potential supply pad for measurement. SUB
... Semiconductor substrate, IO1 to IO4 ... Input / output ports. TE1 to TE6 ... Element for measurement. WAF ... wafer, CHP ... chip, TEG ... characteristic measuring unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ken Ono 5-22-1 Kamisuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd.

Claims (4)

[Claims] 1. A semiconductor device, wherein a characteristic measuring section including a measuring element for characteristic evaluation is arranged in an effective region of a semiconductor substrate. 2. The semiconductor device is provided with a predetermined internal circuit provided to realize its main function, and the pad for supplying a measuring power source to the characteristic measuring section is the internal circuit. 2. The semiconductor device according to claim 1, wherein the semiconductor device is provided separately from a pad for supplying operating power to the circuit. 3. The semiconductor device is a large-scale logic integrated circuit device having input / output ports arranged along four sides of a semiconductor substrate, and the input / output ports are arranged in the effective area. 3. The semiconductor device according to claim 1, wherein the semiconductor device includes vacant areas generated at the four corners of the semiconductor substrate. 4. The characteristic measuring section is used for a characteristic measurement test before and after chip cutting of a wafer on which the semiconductor device is formed. Alternatively, the semiconductor device according to claim 3.