JPH08139644A - Waveform equalizing circuit - Google Patents

Abstract

PURPOSE: To reduce equalizing error by correcting the degree of the amplitude reduction of a signal waveform caused by the difference of an inter-code interference amount between adjacent bits caused by coarse and fine data patterns for each bit and correcting those bits themselves. CONSTITUTION: A temporary deciding means 4 temporarily decides output data 9 as previously decided plural digital data and temporarily decided data 10 are outputted. At an error calculating means 5, a standby value corresponding to the temporarily decided data 10 and the error of delay data 11 are calculated. At a correcting value calculating means 6, correction data 13 corresponding to the output data 9 are calculated from error data 12. At a correcting means 7, arithmetic such as the addition of delay data 14 and correction data 13 is performed and corrected output data 15 of a transversal filter 1 are outputted. Thus, the equalizing error such as data amplitude decrease caused by the difference of the inter-code interference amount between the adjacent bits at the time of high-density recording can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-reliability digital data recording / reproducing apparatus for high-density recording, and more particularly to data pattern density (frequency of signal level change).
The present invention relates to a waveform equalization circuit or a signal processing circuit that corrects a signal affected by the intersymbol interference amount between different adjacent bits.

[0002]

2. Description of the Related Art In a digital data recording / reproducing apparatus for performing high-density recording, for example, a magnetic recording apparatus (magnetic disk apparatus) using a disk-shaped recording medium, so-called inter-symbol interference occurs between adjacent bits and a signal waveform Non-linear distortion and decrease in amplitude occur. This intersymbol interference increases as the recording density increases.

Conventionally, an adaptive equalizer, a decision feedback type or the like has been used as a technique for compensating for the non-linear distortion of the signal waveform (such as the signal waveform not being left-right symmetric) and the decrease in amplitude due to such intersymbol interference. There is a waveform equalization technology such as a rectifier. As an example of the adaptive equalizer, there is a technique disclosed in Japanese Patent Laid-Open No. 4-207708. This is configured so that the judgment error is extracted from the output signal and the tap coefficient of the equalizer is updated only when the sign of the output signal of the transversal filter is different from either the sign immediately before or the sign immediately after. .

As an example of the decision feedback equalizer, there is a technique disclosed in Japanese Patent Laid-Open No. 3-284014. This is based on the error signal between the input and output of the determiner and the signals on the taps of the front and rear equalizers.
are) algorithm is used to obtain and correct each tap coefficient.

Further, the digital data recording / reproducing apparatus includes
The need for high-speed data transfer is increasing, and technical papers (1993 IEEE Intern
ational Solid-State Circuits Conference DIGEST OF
TECHNICAL PAPERS p212-p213) is the technology disclosed. In this configuration, the input data of the equalizer is divided into two series, an odd series and an even series, so that the operation clock of the circuit is reduced to half and waveform equalization is performed.

[0006]

SUMMARY OF THE INVENTION In this conventional method,
There are the following issues.

Current recording density (about 50 kfci, fc
In (i: magnetization reversal interval per inch), even if the data pattern was uneven, it was not so large that it was necessary to be aware of the difference in intersymbol interference amount. However, if the density becomes higher in the future, intersymbol interference will become very large in the dense data pattern, and the sparse part will remain small. Therefore, depending on the data pattern, the amount of intersymbol interference between adjacent bits changes significantly, and the degree of non-linear distortion or amplitude reduction of the signal waveform greatly differs.Equalization error (equalizer output and its output The error from the expected data value) increases.

On the other hand, the conventional method of Japanese Patent Laid-Open No.
In the adaptive waveform equalizer disclosed in Japanese Patent No. 207708, the tap coefficient, that is, the equalization characteristic is controlled so as to minimize the averaged error between the determination result and the equalizer output. Therefore, no feedback is given to the determination result or the output of the equalizer at that time, and the feedback is applied from different data after a certain time has passed. With this, it is impossible to correct the non-linearity of the signal waveform that differs depending on the data pattern and the change in the amplitude decrease for each bit, and the equalization error for each bit cannot be reduced.

In the decision feedback type waveform equalizer disclosed in Japanese Patent Laid-Open No. 3-284014, it is possible to feed back the equalizer output itself used for the decision.
In this case, it is necessary to execute the processing time required for the determination, the feedback equalizer and the arithmetic circuit within one clock, and it becomes impossible to cope with the further increase in the speed of data transfer.

Technical papers (1993 IEEE Internationa
l Solid-State Circuits Conference DIGEST OF TECHNI
The high-speed data transfer technology disclosed in CAL PAPERS p212-p213) is basically the same as the adaptive waveform equalizer or the decision feedback waveform equalizer in obtaining the tap coefficient. Exists.

An object of the present invention is to provide a means for correcting the degree of amplitude reduction of a signal waveform caused by a difference in intersymbol interference amount between adjacent bits due to data pattern density, for each bit and for the bit itself. , To reduce the equalization error.

[0012]

In order to solve the above-mentioned problems, the present invention is a waveform equalization circuit for multiplying a certain input signal (data) by a plurality of weighted coefficients and outputting the added value of the multiplication result. In tentative determination means for tentatively determining the output data of the equalization circuit, two delay means for delaying the output data of the equalization circuit, and calculating an error between the output data of the tentative determination means and the delayed data. Error calculating means, correction data calculating means for calculating correction data based on output data of the error calculating means, and correction means for correcting the delayed data corresponding to the correction data. Is.

[0013]

With this configuration, the provisional decision means makes a provisional decision on the output data of the equalization circuit, and the error calculation means obtains an error between the provisional decision result and the output of the equalization circuit to obtain the correction data. The calculation means calculates correction data from the error data. This makes it possible to obtain correction data for each of the output data of the equalization circuit.

The delay means delays each of two types of time, that is, the time required for the temporary determination and the time required for outputting the correction data.

Further, the correction means for correcting the output of the delay means in accordance with the output of the correction data calculation means can correct the bit itself used for obtaining the correction value, thereby achieving the object.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described in detail below with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of a waveform equalizing circuit in a magnetic disk device, wherein 1 is a transversal filter, 2 and 3 are delay means, 4 is temporary judgment means, 5 is error calculation means, and Reference numeral 6 is a correction value calculation means, and 7 is a correction means.

In FIG. 1, the input data 8 of the transversal filter 1 is digital data. The transversal filter 1 is a waveform shaping circuit according to the related art, and has a function of equalizing the input data 8 into predetermined data (expected value). However, in the transversal filter 1, when the recording density for writing data on the magnetic disk, which is a recording medium, becomes large, the intersymbol interference with the adjacent bits becomes large, and the equalization cannot be completed completely, and the equalization error (expected value and transversal The error with the output data 9 of the filter 1) becomes large. The output data 9 including the equalization error is input to each of the delay unit 2, the delay unit 3, and the temporary determination unit 4. The provisional determination means 4 provisionally determines the output data 9 into a plurality of predetermined digital data, and outputs the provisional determination data 10. The delay unit 3 delays the input data 9 by a time equal to the time required for the temporary determination by the temporary determination unit 4 (delay data 11). In the error calculation means 5, the temporary determination means 4
The error between the expected value and the delay data 11 corresponding to the temporary determination data 10 output from is calculated (error data 12). In the correction value calculation means 6, the correction data 13 for the output data 9 of the transversal filter 1 is calculated from the error data 12.
To calculate. The delay unit 2 delays the input data 9 by a time equal to the total time required by each of the temporary determination unit 4, the error calculation unit 5, and the correction value calculation unit 6 (delay data 1
4). In the correction means 7, the delay data 14 and the correction data 13
Is calculated, and the corrected output data 15 of the transversal filter 1 is output. Note that each circuit is synchronized with a clock that takes in the input data 8.

According to the embodiment shown in FIG. 1, the correction data calculated based on the equalization error of the output data of the transversal filter can be added to the output data itself. As a result, it is possible to reduce an equalization error such as a decrease in data amplitude caused by a difference in intersymbol interference amount between adjacent bits during high density recording. This can reduce errors in data discrimination. Further, by providing the delay units 2 and 3, it is not necessary to perform feedback within one clock, and high-speed data transfer can be supported.

Here, regarding the function and configuration of each block,
It will be described in more detail with reference to FIG.

FIG. 2 is a block diagram showing a specific example of the temporary decision means 4, 20 is a data input terminal, 21 is a threshold value input terminal, 22 is a complement circuit, 23 and 24 are comparators, and 25 and 2 are.
Reference numeral 6 is a temporary determination data output terminal. The complement circuit 22 outputs the complement -a of the threshold value a. The comparator 23 outputs a voltage of high level when x> a (x: data amplitude value) and outputs a low level otherwise (output terminal 25). Similarly, the comparator 24 outputs a high voltage when x <-a, and outputs a low level otherwise (output terminal 26). That is, the temporary determination means 4 performs level determination.

FIG. 3 is a block diagram showing a specific example of the error calculating means 5. Reference numerals 25, 26, 30 and 31 are data input terminals, 32 is a complement circuit, 33 and 34 are AND circuits, and 35.
Is an OR circuit, 36 is an adder circuit, and 38 is an error data output terminal. The output 2 of the comparator 23 is connected to the data input terminal 25.
5, the output 26 of the comparator 24 is input to the data input terminal 26. Data input terminal 31 has symbol "+1"
The expected value data b is input, and the complement circuit 32 outputs the complement -b of the expected value data b. The AND circuit 33 outputs a logical product of the input data 25 and the expected value data b,
The AND circuit 34 outputs a logical product of the input data 26 and the complement −b of the expected value data. The OR circuit 35 outputs the logical sum of the outputs of the AND circuits 33 and 34. With these circuits, when the output result of the provisional determination means is "+1", b
However, when "-1", -b is output, and when "0", 0 is output (37). The delay data 11 which is the output of the delay means 3 is input to the data input terminal 30, and the delay data 11 is output from the output 3 of the OR circuit 35 in the adder circuit 36.
7 is subtracted, and error data 38 is output (output terminal 38).

FIG. 4 is a block diagram showing a specific example of the correction data calculating means 6, 38 and 40 being data input terminals.
41 is a complement circuit, 42 and 43 are comparators, 44 is a NOR circuit, 45 is an AND circuit, and 46 is a correction data output terminal. The error data 38 is input to the data input terminal 38, and the threshold value c is input to the data input terminal 39. The complement circuit 41 outputs the complement -c of the threshold value c. The comparator 42 outputs a high voltage when y> c (y: error data value), and outputs a low level voltage otherwise. Similarly, the comparator 43
Outputs a voltage of high when y <−c, and outputs a low level otherwise. The NOR circuit 44 is provided only when the outputs of the comparator 42 and the comparator 43 are low, that is, -c≤y.
A high-level voltage is output only when ≤c, and a low-level voltage is output otherwise. AND circuit 45 is N
The logical product of the output of the OR circuit 44 and the error data 38 is output as the correction data 46. That is, the value of the error data 38 is output only when -c≤y≤c, and otherwise "
0 "is output.

FIG. 5 is a block diagram showing a specific example of the correction means 7. Reference numerals 50 and 51 are data input terminals, 52 is an adder circuit, and 53 is a data output terminal. Data input terminal 5
The delay data 14 output from the delay unit 2 is input to 0, and the correction data 46 is input to the data input terminal 51. The adder circuit 52 adds the two data and outputs the result (output terminal 53).

FIG. 6 is a timing chart of the data relating to the data correction in FIG. 1. 8 is the input data 8 and 9 of the transversal filter 1, 9 is the output data of the transversal filter 1, 25 and 26 are the temporary judgment means. 4, output data 25, 26, which is a specific example of the output data 10 of
Reference numeral 12 is output data 12 of the error calculation means 5, 13 is output data 13 of the correction data calculation means 6, 15 is output data 15 of the correction means 7, and 61 is expected value data. The horizontal axis is the time axis, and one scale indicates the sampling interval. The black circles are sampling data. In No. 8, the waveform is collapsed due to intersymbol interference. Although 9 is the output of the transversal filter 1, the waveform is shaped, but the effect of intersymbol interference cannot be completely removed, and equalization error remains without Nyquist equalization. 25 is “+1” provisional determination, and 26 is “−1” provisional determination. 12
Using these provisional judgment data, the expected value data 61
And error data of the output data of the transversal filter 1 indicated by black circles 9 and 9. Reference numeral 13 is correction data, and in this case, the error data 12 is smaller than a predetermined threshold value, so the error data 12 is the correction data as it is. Reference numeral 15 is data obtained by adding the correction data 13 and the output data 9 of the transversal filter 1 at the same timing.
The error with 1 is gone. Note that FIG. 6 shows a case where the calculation of the error data 12 and the calculation of the correction data 13 each take one clock time.

According to the first embodiment, if the equalization error of the output data of the transversal filter is smaller than a certain threshold value, the equalization error can be added to the output data itself as correction data. As a result, it is possible to reduce an equalization error such as a decrease in data amplitude caused by a difference in intersymbol interference amount between adjacent bits during high density recording. As a result, errors in data discrimination using the output data of this embodiment can be reduced. Further, although the equalization error is used as it is as the correction data in the present embodiment, it is also possible to use data obtained by processing the equalization error, for example, data of multiplying by 0.5 and squaring. .

Further, in the first embodiment, the equalizer circuit is a conventional one-series transversal filter, but the input data shown in the prior art is divided into two series, an odd series and an even series, and the waveform is divided. Even when an equalization circuit configured to perform equalization is used, the same method as in the first embodiment can be used, and the equalization error can be reduced. In this case, an odd-numbered series equalizer circuit output and an even-numbered series equalizer circuit output may be alternately provided as input data. Alternatively, the circuit shown in the first embodiment may be attached to each of the odd series equalizer circuit output and the even series equalizer circuit output.

FIG. 7 is an embodiment showing the configuration of an apparatus when the waveform equalizing circuit shown in FIG. 1 is adopted in, for example, a magnetic disk apparatus, 70 is a magnetic disk apparatus, 71 is a recording medium, and 72 is a recording medium. Is a magnetic head, 73 is a spindle motor,
74 is a voice coil motor (VCM), 75 is a lead /
Write amplifier (R / W amplifier), 76 is an automatic gain control circuit (AGC), 77 is a low pass filter (LPF), 7
8 is an analog / digital converter (A / D), 79
Is a waveform equalizer circuit shown in FIG. 1, 80 is a variable frequency oscillator (VFO), 81 is a gain controller, 82 is a data discrimination circuit, 83 is a modulator / demodulator (ENDEC), 84 is an error correction circuit (ECC), Reference numeral 85 is a hard disk controller (HDC), and 86 is a servo processor.
In FIG. 7, the HDC 85 which has received the read command from the host computer passes through the servo processor 86 to the VC.
The M74 is operated to move the magnetic head 72 to the target cylinder. The magnetic head 72 reads the data on the recording medium 71. The signal read from the magnetic head 72 is amplified by the R / W amplifier 75 and the AGC 76, the LPF 77 removes high band noise, and the aliasing due to sampling is prevented, and the signal is input to the A / D 78. A / D
At 78, the VFO clock created by the VFO 80 is sampled. The sampling data is waveform-equalized by the waveform equalization circuit 79 shown in FIG. Waveform equalization circuit 7
The output data of 9 is VFO80, gain controller 8
1, input to the data discrimination circuit 82. VFO80
Then, a VFO clock is created from the data after this equalization. The gain controller 81 obtains the magnitude relationship between the equalized data and the expected amplitude data value, and if the equalized data is small, the AGC 76 increases the signal amplitude, and if it is large, the signal amplitude decreases. Control the gain. The data discrimination circuit 82 discriminates the data by, for example, Viterbi discrimination or level slice. This discrimination result is decoded by ENDEC83, ECC
The error is corrected at 84 and passed to the HDC 85. HDC
85 returns this data to the host computer.

Since the waveform equalization circuit shown in FIG. 1 can be used by adopting the above configuration, the equalization error is reduced, the discrimination error is reduced, and the reliability of the data as the device can be improved. In addition, the waveform equalizing circuit according to the present invention has an R / W
The amplifier 75 to the data discriminating circuit 82 can be integrated into an LSI as one data channel IC.

[0030]

According to the present invention, in a digital data recording / reproducing apparatus such as a magnetic disk device for high density recording, an equalization error is obtained for each bit of output data of an equalization circuit, and the equalization error is obtained. It is possible to obtain the correction data based on the above, and it is possible to perform the correction by feeding back to the output data itself of the equalization circuit used for obtaining the correction data.

As a result, it is possible to absorb the difference in the intersymbol interference amount due to the density of the data pattern at the time of high density recording, and the equalization error can be reduced by the correction. Therefore, the discrimination error in the Viterbi discrimination circuit in the subsequent stage or the data discrimination circuit such as the level slice can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a waveform equalization circuit.

FIG. 2 is a block diagram showing an example of a provisional determination unit.

FIG. 3 is a block diagram showing an embodiment of error calculation means.

FIG. 4 is a block diagram showing an embodiment of correction data calculation means.

FIG. 5 is a block diagram showing an embodiment of correction means.

FIG. 6 is a timing chart of data related to the data correction in FIG.

FIG. 7 is a block diagram of a magnetic disk device that employs the waveform equalization circuit of FIG.

[Explanation of symbols]

1 ... Transversal filter, 2, 3 ... Delay means, 4
... provisional judgment means, 5 ... error calculation means, 6 ... correction data calculation means, 7 ... correction means, 70 ... magnetic disk device.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kunio Watanabe Inventor Kunio Watanabe 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Ltd. System Development Laboratory, Hitachi, Ltd. Tate Manufacturing Semiconductor Division

Claims (6)

[Claims] 1. A waveform equalizer circuit that multiplies an input signal by a plurality of weighted coefficients and outputs an addition value of the multiplication results, and a provisional determination unit that temporarily determines output data of the waveform equalizer circuit. Two delay means for delaying the output data of the equalization circuit, an error calculating means for calculating an error between the output data of the temporary determining means and the delayed data, and correction data based on the output data of the error calculating means. A waveform equalization circuit comprising: a correction data calculation unit for calculating; and a correction unit for correcting the delayed data corresponding to the correction data. 2. A waveform equalization circuit according to claim 1, wherein said temporary decision means discriminates into digital data based on a magnitude relation between output data of said equalization circuit and predetermined threshold data. 3. The error calculation means according to claim 1 or 2, further comprising: expected value data corresponding to the temporary determination data;
A waveform equalizer circuit for obtaining an error from the output data of the delay means for delaying the output data of the equalizer circuit. 4. The correction data calculation means according to claim 1, 2 or 3, wherein the correction data is the error data, or a waveform or the like, which is zero, depending on the magnitude relation between the error data and a predetermined threshold value data. Circuit. 5. The waveform equalization circuit according to claim 1, 2, 3 or 4, wherein the correction means adds the correction data and the output data of the delay means for delaying the output data of the equalization circuit. . 6. The method according to claim 1, 2, 3, 4 or 5.
The waveform equalization circuit, a recording medium on which a signal to be discriminated into any of a plurality of predetermined digital data is magnetically recorded, a magnetic head for reading the recorded signal, and the read-out signal. It has a preamplifier for amplifying a signal and an analog / digital converter for converting the amplified signal into digital data, and the waveform equalization circuit receives the digital data and receives the output data from the waveform equalization circuit. A magnetic disk device that discriminates data.