JPH08139193A - Semiconductor device - Google Patents

Abstract

PURPOSE: To allow both the high integration and the high yield to be compatible by reducing an aspect ratio even if the area of a metal wiring connecting hole is small. CONSTITUTION: The diffused layer 26c of an Si substrate 21 is electrically connected to an Al layer 37b via a polycrystalline Si layer 33d as an intermediate layer. Thus, even if the area of a connecting hole 44 for the layer 37b is smaller than that of a structure in which the substrate 21 is connected directly to the layer 37b, the aspect ratio is reduced to enhance the step coverage of the layer 37b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor substrate and metal wiring are electrically connected to each other.

[0002]

2. Description of the Related Art FIG. 4 shows a DINOR type flash EE.
The equivalent circuit of PROM is shown. One group 11 of the DINOR type flash EEPROM is composed of a single selection transistor 12 and a plurality of memory cell transistors 13, and a plurality of memory cell transistors 13 connected in parallel to each other are connected in series to the selection transistor 12. It is connected to the. The main purpose of using the selection transistor 12 is to select the memory cell transistor 13 which is not selected.
Is to prevent disturbance from its drain.

The selection transistor 12 is controlled by a selection gate 14, and the memory cell transistor 13 is controlled by a word line 15 as a control gate. Also,
The main bit line 16 is connected to the drain of the selection transistor 12, and the source of the selection transistor 12 and the drain of each memory cell transistor 13 are connected to the sub bit line 1.
Connected by 7. A common source line 18 is connected to the source of each memory cell transistor 13.

FIGS. 5 and 6 show a prior example of such a DINOR type flash EEPROM. In this one prior example, the LOCOS is formed in the element isolation region of the Si substrate 21.
SiO ₂ film 22 is selectively formed by the
_On the surface of the lattice-shaped element active region surrounded by the _two films 22, S as a gate oxide film of the transistors 12 and 13
An iO ₂ film 23 is formed.

In the polycrystalline Si layers 24a and 24b, which are the first wiring layers on the Si substrate 21, the wiring below the selection gate 14 and the floating gate of the memory cell transistor 13 are formed. These polycrystalline Si layers 24a, 2
4b is covered with an insulating film (not shown). And S
Polycide layer 2 which is the second wiring layer on i substrate 21
Wirings on the upper layer side of the selection gate 14 and the word line 15 are formed at 5a and 25b.

In the device active regions on both sides of the polycide layers 25a and 25b, a diffusion layer 26a as a drain of the selection transistor 12, a diffusion layer 26b as a source of the selection transistor 12 and a drain of the memory cell transistor 13, and a memory cell. The diffusion layer 26c serving as the source of the transistor 13 is formed, and the polycide layer 25 is formed.
The layers a, 25b, etc. are covered with the interlayer insulating film 27. The polycide layer 24a and the diffusion layer 26b are formed on the interlayer insulating film 27 and the like.
There are provided connection holes 31 and 32, respectively.

In the polycrystalline Si layers 33a and 33b, which are the third wiring layer on the Si substrate 21, the shunt wiring is connected to both the polycrystalline Si layer 24a and the polycide layer 25a through the connection hole 31. The layer and the sub-bit line 17 connected to the diffusion layer 26b through the connection hole 32 are formed. A polycide layer may be used instead of the polycrystalline Si layers 33a and 33b.

The polycrystalline Si layers 33a, 33b and the like are covered with an interlayer insulating film 34, and connection holes 35, 36 reaching the diffusion layers 26a, 26c are provided in the interlayer insulating film 34 and the like. Then, in the Al layers 37a and 37b, which are the fourth wiring layers on the Si substrate 21, the main bit line 16 connected to the diffusion layer 26a via the connection hole 35 and the diffusion layer 26c via the connection hole 36. And a common source line 18 connected to.

The following Table 1 shows the operating voltage in the selected group 11.

[Table 1]

Table 2 below shows the operating voltage in the non-selected group 11.

[Table 2]

The following Table 3 shows operating voltages in the main bit line 16 and the Si substrate 21.

[Table 3]

[0012]

In the DINOR type flash EEPROM, the polycrystalline Si layers 33a and 33b are compared with the NOR type flash EEPROM which does not require the selection transistor 12 and the sub-bit line 17 and the like.
An interlayer insulating film 34 for covering the above is newly required. Therefore, in the above-described one prior example, as apparent from FIG. 5, the Al layers 37a and 37b to be connected to the diffusion layers 26a and 26c are formed.
The connection holes 35, 36 for use are deep and have a high aspect ratio.

When the aspect ratio of the connection holes 35 and 36 is high, the step coverage of the Al layers 37a and 37b, which originally has a low step coverage, further deteriorates, and the final product yield also decreases. Lower the aspect ratio of the connection holes 35 and 36,
In order to improve the step coverage of the Al layers 37a and 37b, it is possible to increase the area of the connection holes 35 and 36.

However, increasing the area of the connection holes 35, 36 is disadvantageous for high integration. In other words, in the prior art examples shown in FIGS. 5 and 6, it is difficult to achieve both high integration and high yield.

[0015]

According to another aspect of the semiconductor device of the present invention, the semiconductor substrate 21 and the metal wirings 37a, 37b in the upper layer of the semiconductor substrate 21 are conductive layers 33c as intermediate layers.
It is characterized in that they are electrically connected to each other through 33d.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein the conductive layers 33c and 33d are layers containing a semiconductor.

A semiconductor device according to a third aspect is the semiconductor device according to the first or second aspect, wherein the conductive layers 33c and 33d and the metal wirings 37a and 37b are connected to each other on the element isolation region 22. I am trying.

A semiconductor device according to a fourth aspect is the semiconductor device according to any one of the first to third aspects, wherein the conductive layers 33c and 33 are provided.
It is characterized by having a wiring layer 33b in the same layer as d.

A semiconductor device according to a fifth aspect is the semiconductor device according to the fourth aspect, wherein the semiconductor device is a DINOR type and batch erase type non-volatile semiconductor memory device, and the metal wirings 37a and 37b are mainly composed of Al. Main bit line 1
6 and the common source line 18, and the wiring layer 33b is the sub-bit line 17.

[0020]

In the semiconductor device according to the first aspect, the semiconductor substrate 21 and the metal wirings 37a and 37b are the conductive layer 33 as an intermediate layer.
Since they are electrically connected to each other via c and 33d, compared with the structure in which the semiconductor substrate 21 and the metal wirings 37a and 37b are directly connected, the metal wirings 37a and 37
Even if the area of the connection holes 43 and 44 for b is small, the aspect ratio can be lowered and the step coverage of the metal wirings 37a and 37b can be improved.

According to another aspect of the semiconductor device of the present invention, the conductive layer 33 is provided.
Since c and 33d are layers containing a semiconductor, connection holes 41 for the conductive layers 33c and 33d for the semiconductor substrate 21 are provided.
The area of 42 is the connection hole 43 for the metal wirings 37a and 37b,
It can be smaller than the area of 44.

In the semiconductor device of claim 3, the conductive layer 33 is used.
Since c and 33d and the metal wirings 37a and 37b are connected to each other on the element isolation region 22, the conductive layers 33c and 3d.
Compared with the structure in which 3d and the metal wirings 37a and 37b are connected to each other on the element active region, the margin of the pattern is large. Further, if the connection holes 43, 44 for the metal wirings 37a, 37b are located on the other wirings 25a, 25b extending on the element isolation region 22, the connection holes 43, 44 are shallowed, The aspect ratio can be further reduced.

According to another aspect of the semiconductor device of the present invention, the conductive layer 3 is provided.
Since the wiring layer 33b in the same layer as 3c and 33d exists, it is not necessary to provide a new wiring layer for the conductive layers 33c and 33d.

[0024]

EXAMPLE A DINOR type flash EEPRO is described below.
An embodiment of the present invention applied to M will be described with reference to FIGS. In addition, in the embodiment shown in FIGS. 1 to 3, the components corresponding to the preceding examples shown in FIGS. 5 and 6 are denoted by the same reference numerals as those in FIGS.

In order to manufacture this embodiment, as shown in FIGS. 2 and 3A, first, the SiO ₂ film 22 is selectively formed in the element isolation region of the Si substrate 21 by the LOCOS method. , A SiO ₂ film 23 as a gate oxide film of the select transistor 12 and the memory cell transistor 13 is formed on the surface of the lattice-shaped element active region surrounded by the SiO ₂ film 22.

After that, the select gate 1 is formed by using the polycrystalline Si layers 24a and 24b which are the first wiring layers on the Si substrate 21.
4 on the lower layer side and the floating gate of the memory cell transistor 13, and these polycrystalline Si layers 24a, 2
4b is covered with an insulating film (not shown). And the Si substrate 2
Second wiring layer on the first polycide layer 25a, 2a
5b, the wiring on the upper layer side of the selection gate 14 and the word line 1
5 and 5 are formed.

Thereafter, a diffusion layer 26a as the drain of the selection transistor 12, a diffusion layer 26b as the source of the selection transistor 12 and a drain of the memory cell transistor 13, and a memory in the device active regions on both sides of the polycide layers 25a and 25b. The diffusion layer 26c serving as the source of the cell transistor 13 is formed, and the polycide layer 25 is formed.
A, 25b, etc. are covered with an interlayer insulating film 27. Then, the connection holes 31, 41, 32, 42 reaching the polycrystalline Si layer 24a and the diffusion layers 26a to 26c, respectively, are opened in the interlayer insulating film 27 and the like.

Next, as shown in FIGS. 2 and 3B, S
Polycrystalline Si layer 3 which is the third wiring layer on i substrate 21
3a to 33d, the polycrystalline Si layer 24 is formed through the connection hole 31.
a and the polycide layer 25a, the shunt wiring layer, the sub-bit line 17 connected to the diffusion layer 26b through the connection hole 32, and the diffusion layer 26a through the connection holes 41 and 42,
26c and these connecting holes 41, 42 respectively.
And a conductive layer located thereabove. A polycide layer may be used instead of the polycrystalline Si layers 33a to 33d.

Next, as shown in FIGS. 2 and 3C, the polycrystalline Si layers 33a to 33d and the like are covered with an interlayer insulating film 34,
Connection holes 43 reaching the polycrystalline Si layers 33c and 33d,
A hole 44 is formed in the interlayer insulating film 34 or the like. Then, FIGS.
As shown in FIG. 5, in the Al layer 37a and the Al layer 37b which are the fourth wiring layer on the Si substrate 21, the main bit line 16 connected to the polycrystalline Si layer 33c through the connection hole 43 and the connection hole are formed. The common source line 18 connected to the polycrystalline Si layer 33d via 44 is formed.

In the present embodiment manufactured as described above, the polycrystalline Si layers 33c and 33d fill the contact holes 41 and 42, but the polycrystalline Si layers 33a to 33d are usually deposited by the CVD method. Therefore, the connection holes 41 and 42 are made of polycrystalline S
It is sufficiently filled with the i layers 33c and 33d. Therefore, the connection holes 43 and 44 for the Al layers 37a and 37b are formed.
Need only reach the polycrystalline Si layers 33c and 33d,
The aspect ratio of the connection holes 43 and 44 is low.

Therefore, in the present embodiment, the Al layers 37a, 3
The step coverage of 7b is high and the yield is high. Moreover, the polycrystalline Si layers 33c and 33d are the polycrystalline Si layers 33a and 33d.
Since it is the same layer as b, the manufacturing process has not increased,
Manufacturing costs have not increased.

In the above embodiments, the connection holes 41, 4
Although the connection holes 43 and 44 are arranged on the connection hole 2,
3 and 44 are on the SiO ₂ film 22 and further on the SiO ₂ film 22.
It may be arranged on the upper polycide layers 25a and 25b, and in this case, the connection holes 43 and 44 become shallower and the aspect ratio becomes lower.

Further, although the present invention is applied to the DINOR type flash EEPROM in the above embodiments, the present invention can naturally be applied to semiconductor devices other than the DINOR type flash EEPROM.

[0034]

In the semiconductor device according to the first aspect of the present invention, even if the area of the connection hole for the metal wiring is small, the aspect ratio can be lowered to enhance the step coverage of the metal wiring. It is possible to achieve both high yield and high yield.

In the semiconductor device according to the second aspect, the area of the connection hole for the conductive layer to the semiconductor substrate can be made smaller than the area of the connection hole for the metal wiring. Therefore, the area of the connection hole for the metal wiring can be made small. In addition to that, it is possible to achieve higher integration.

In the semiconductor device of the third aspect, the overall pattern margin is large, and the aspect ratio of the connection hole for the metal wiring can be further reduced, so that the yield can be further increased.

In the semiconductor device according to the fourth and fifth aspects, since it is not necessary to provide a new wiring layer for the conductive layer, the manufacturing cost does not increase even if the conductive layer is provided.

[Brief description of drawings]

FIG. 1 shows an embodiment of the invention of the present application, and FIG.
It is a sectional side view in the position which follows the -A line.

FIG. 2 is a plan view of an example.

3 shows the manufacturing process of one embodiment in sequence, and FIG.
It is a sectional side view in the position which follows the AA line of FIG.

FIG. 4 is an equivalent circuit diagram of a DINOR type flash EEPROM to which the invention of the present application can be applied.

FIG. 5 shows a prior example of the invention of the present application, which is indicated by B in FIG.
It is a sectional side view in the position which follows the -B line.

FIG. 6 is a plan view of a prior art example.

[Explanation of symbols]

16 Main bit line 17 Sub-bit line 18 Common source line 21 Si substrate 22 SiO ₂ film 33b Polycrystalline Si layer 33c Polycrystalline Si layer 33d Polycrystalline Si layer 37a Al layer 37b Al layer

Claims (5)

[Claims] 1. A semiconductor device in which a semiconductor substrate and a metal wiring in an upper layer of the semiconductor substrate are electrically connected to each other through a conductive layer as an intermediate layer. 2. The semiconductor device according to claim 1, wherein the conductive layer is a layer containing a semiconductor. 3. The semiconductor device according to claim 1, wherein the conductive layer and the metal wiring are connected to each other on an element isolation region. 4. The semiconductor device according to claim 1, further comprising a wiring layer that is the same layer as the conductive layer. 5. The semiconductor device is a DINOR type and batch erase type non-volatile semiconductor memory device, the metal wiring is a main bit line and a common source line containing Al as a main component, and the wiring layer is a sub-layer. The semiconductor device according to claim 4, wherein the semiconductor device is a bit line.