JPH08130892A - Drive circuit for brushless motor - Google Patents

Abstract

PURPOSE: To eliminate position delay of a rotor position signal for stabilization by adding and subtracting a compensation value determined by the resistor of an armature coil winding and the coil winding current to and from the detector coil winding terminal potential of each phase only for an actual drive period for compensating each phase terminal potential and applying the detected rotor position signal to the armature coil winding of each phase for driving. CONSTITUTION: A terminal potential is compensated and compensation terminal potential signals 1a, 1b, and 1c are outputted to a terminal potential compensation circuit 1. Then, the terminal potential of each compensated phase is compared and logic signals 2a, 2b, and 2c are obtained by a comparison circuit 2. Further, the logical signals 2a, 2b, and 2c are subjected to waveform shaping and rotor position signals 3a, 3b, and 3c are obtained by a waveform-shaping circuit 3. A rotor position signal generation circuit 4 is constituted by including the members of the terminal potential compensation circuit l, the comparison circuit 2, and the waveform-shaping circuit 3. Then, a commutation circuit 9 outputs drive signals 9a-9f according to the state of input signals and switches a group of drive transistors TR1-TR6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a brushless motor.

[0002]

2. Description of the Related Art Rotational drive control of a brushless motor is 2
There are two control functions. One is commutation control for controlling the timing of applying a current to the armature winding of each phase, and the other is speed control for keeping the rotation speed constant. The commutation control requires a rotor position signal indicating the relative position of the armature winding and the rotor, while the speed control requires a speed signal indicating the rotation speed of the rotor.

A rotor position detecting element such as a Hall element is used for commutation switching control of a typical conventional brushless motor. However, the rotor position detecting element is not inexpensive at all, and more wiring is required, which is complicated and causes a cost increase. Further, by mounting the rotor position detecting element, downsizing and thinning of the motor are limited. Further, since the output of the rotor position detecting element changes depending on the temperature and humidity, there is a problem in reliability.

In order to eliminate this drawback, some brushless motor drive systems have been proposed in which the rotor position is detected from the back electromotive force signal induced in the armature winding. As a typical driving method for detecting a position from a back electromotive voltage signal, there is one described in Japanese Patent Publication No. 58-25038. This discloses both position detection by comparing the magnitudes of the terminal potentials and position detection by comparing the neutral point potential of the armature winding with the magnitude of the terminal potentials. There is.

The overall structure of the system for detecting the position by comparing the neutral point potential with the terminal potential is shown in FIG.
Shown in 20. In FIG. 120, reference numerals 12, 13, and 14 denote armature windings of a star-connected brushless motor.
Reference numeral 1 is a bridge circuit that switches the energizing current flowing through the armature windings 12, 13, and 14. The comparator 500 detects the rotor position by comparing the terminal potentials U, V, W of each phase that is not the neutral point of the armature winding with the neutral point potential M, respectively. The commutation control unit 501 controls the bridge circuit 11 according to the rotor position detected by the comparator 500, and energizes the armature winding of a predetermined phase to rotate the rotor.
Further, as a method for correcting the phase delay generated when the terminal potentials are compared, Japanese Patent Laid-Open No. 51-100216 discloses a method in which the resistance drop amount of the armature winding is regarded as a constant value and is corrected by a voltage dividing resistor. ing.

By the way, in the drive system in which the rotor position is detected by using the back electromotive force induced in the armature winding, the rotation speed of the rotor reaches a predetermined value or more and a predetermined value is applied to the terminal of the armature winding. The position of the rotor cannot be detected unless the back electromotive force is generated. For this reason, since the rotor position cannot be obtained at the time of starting, means for forcibly applying the rotating magnetic field from the outside is required. However, when a rotating magnetic field is forcibly given from the outside, the relative position of the rotor and the armature winding does not always stop at a position where it can rotate in the forward rotation direction. There is a problem that torque may act in the rotation direction, and normal startup cannot be performed.

In order to solve this problem, for example, improvement proposals have been proposed in JP-A-57-173385 and JP-A-2-237490. Japanese Patent Application Laid-Open No. 57-173385 includes means for energizing a specific phase of the armature winding for a predetermined time at startup, and means for externally forcibly applying a rotating magnetic field to the armature winding. A starting method is disclosed in which the rotor is started to rotate after the child is fixed in place. The method of Japanese Patent Laid-Open No. 173385/57 will be described with reference to FIG. In FIG. 121 (a), a fixed timer circuit 512 is connected to a power supply 510 via a power switch 511,
Armature winding 12 (U phase) of a three-phase DC brushless motor,
13 (V phase) and 14 (W phase) are connected. The armature windings 12, 13 and 14 have transistors 515 and
The collectors of 516 and 517 are connected, the emitter of this transistor is grounded, and a drive circuit 518 is configured. A switching timer circuit 513 and a rotating magnetic field generating circuit 514 are connected to the fixed timer circuit 512, and the switching circuit 5 is further connected to the switching timer circuit 513.
19 is connected. The switching circuit 519 switches the current for driving the drive circuit 518 output from the rotating magnetic field generation circuit 514 and the drive current based on the induced voltage detected by the armature windings 12, 13, 14 to the drive circuit 518. To supply. The bases of the transistors 515, 516 and 517 of each phase are connected to the output terminal of the switching circuit 519. An induced voltage detection circuit 520 is connected to the input end of the switching circuit 519. The armature windings 12, 13, 14 are connected to the input terminals of the induced voltage detection circuit 520.
Is connected. The switching circuit 519 is configured so that output signals for each of the three phases are input from the rotating magnetic field generation circuit 514 to the input terminal.

With this structure, when the power switch 511 is turned on, the armature windings 12, 13, 14 are turned on.
One of them is connected to the power supply, and at the same time the fixed timer circuit 512
Is operated to excite a certain phase of the armature windings 12, 13, 14 such as the W phase, and the control signal 52 shown in FIG.
1 is output to the rotating magnetic field generation circuit 514 for a certain period of time, and at the same time, is output to the switching timer circuit 513. The fixed timer circuit 512 outputs the control signal 521, and the fixed timer circuit 512 is turned off after a predetermined time has elapsed. With this off, the armature windings 12, 13,
Drive signals 523, 524, 525 shown in FIG. 121 (b) for respectively exciting 14 are output to the bases of the transistors 515, 516, 517 via the switching circuit 519. This switching circuit 519 switches to the connection state of the solid line shown in FIG. 121 (a) by the switching command signal 522 shown in FIG. 121 (b) output from the switching timer circuit 513, and from this switching timer circuit 513. This connection state is maintained until the output switching command signal 522 becomes low.

The drive signal output from the rotating magnetic field generation circuit 514 causes the transistor 515 of the drive circuit 518 to
A driving signal is sequentially applied to the bases of the armature windings 516, 517, and a current is sequentially supplied from the power supply 510 to the armature windings 12, 13, 14 and a rotating magnetic field is generated in the armature windings 12, 13, 14 to cause the rotor to rotate. Starts rotating. When the motor is started in this way and a predetermined time has elapsed, the switching signal 522 output from the switching timer circuit 513 becomes low, and the switching circuit 519 switches. The drive signal output from the induced voltage detection circuit 520 is output to the drive circuit 518, the transistors 515, 516, and 517 are sequentially driven, and the three-phase brushless motor keeps rotating.

Next, JP-A-2-237490 will be described. The brushless motor is provided with a magnetoelectric conversion element for detecting the rotational position of the rotor. And
At start-up, based on the rotational position detected by the magnetoelectric conversion element, a predetermined energization switching pattern corresponding to the rotor stop position is selected from among a plurality of energization patterns preset for starting, and this is selected. The drive current to the stator armature winding is switched by the energization switching pattern to generate a rotating magnetic field and start the rotor. Then, when the induced voltage generated in the stator armature winding reaches the value necessary to detect the rotational position of the rotor, the rotational position of the rotor is detected from the induced voltage, and this detection output is used to output the armature winding. The drive current to the wire is switched and a rotating magnetic field is generated to rotate the rotor.

On the other hand, in speed control of a brushless motor,
Conventionally, a method of keeping the rotation speed constant by controlling the amount of current flowing through the armature winding is generally used. FIG. 122 is a block diagram of a speed control system of a conventional brushless motor drive circuit. 12
2, a speed detection circuit 530 detects the actual rotation speed of the rotor and outputs a speed signal, and a speed detection circuit 531 counts the cycle of the speed signal with a reference clock and outputs a speed error signal having a pulse width corresponding to the speed error. This is a speed error detection circuit that outputs, and the speed error compensation filter 532 outputs a current command value such that the speed error becomes 0 to the current supply circuit 533 based on the speed error signal. The current supply circuit 533 adjusts the amount of current supplied to the armature winding of the brushless motor 534 based on the current command value. In such a conventional brushless motor drive circuit, the speed error compensation filter is composed of an analog filter, and the PI filter 460 and the first-order lag filter 46 as shown in FIG.
What connected 4 in series was used.

Further, in the conventional brushless motor drive circuit, the fact that the cycle of the speed signal is counted by the reference clock makes use of the speed error detector when the commanded rotation speed to the motor changes. The frequency of the input reference clock was changed in proportion to the commanded rotational speed to switch the rotational speed.

Further, as a method for detecting a speed signal for controlling the rotation speed of a brushless motor, a method conventionally known as an FG method using a dedicated frequency generator for speed detection and an armature winding are used. There is a method of detecting the speed by utilizing that the amplitude of the induced back electromotive force signal is proportional to the rotation speed.

[0014]

A conventional driving method for detecting a position by comparing the magnitudes of terminal potentials is as follows.
Since one of the two terminal potentials to be compared is the energized phase and the other is the non-energized phase, the effect of resistance drop in the armature winding of the energized phase increases when the energized current increases during load, and the rotor The position signal has a phase delay.
Due to this phase delay, commutation timing is delayed, the generated torque is reduced, and the rotation speed is reduced. When the rotation speed decreases, the energizing current increases in order to increase the rotation speed, which further causes a vicious circle in which the influence of resistance drop increases. Then, in the worst case, there is a problem that the torque exceeding the load cannot be generated and the vehicle is stopped.

On the other hand, in the conventional drive system for detecting the position by comparing the magnitude of the neutral point potential and the terminal potential, the problem that the phase delay occurs in the position detection signal is solved, but the neutral point is brushless. Since it has to be pulled out from the inside of the motor, there is a problem that the lead processing becomes complicated.

Further, the rotor position signal obtained by comparing the neutral point potential and the terminal potential has a phase difference of 30 degrees in electrical angle with respect to the actually required rotor position signal. Must be done. Usually, an integral filter is often used for phase correction, but when the motor is operated at a variable speed, the constant of the integral filter must be changed. Further, if the constant is fixed, the commutation operation becomes unstable in the transient state.

Further, in both of the above driving methods, there is a problem that the rotor position signal becomes inaccurate due to the influence of spike-like noise generated in the terminal potential waveform due to the switching of the driving transistor.

Further, in the method of detecting the speed by the dedicated frequency generator, a frequency generator with high machining accuracy is required, and since a dedicated detector is used, it is disadvantageous in terms of space efficiency and cost. was there.

In the method of detecting the speed by the amplitude of the counter electromotive voltage, the voltage generated by the driving current flowing through the armature winding is superposed on the counter electromotive voltage, and therefore only the amplitude of the counter electromotive voltage signal is detected. However, there is a problem in that the amplitude fluctuates due to changes in the surrounding environment.

Further, the conventional brushless motor start-up system is constructed as described above, and there is a problem that it takes a long time to start up because it is necessary to wait for a predetermined time in a predetermined phase after the start-up switch is turned on.

Further, since the start-up is performed in an open loop,
There is a problem in that it is impossible to detect whether or not the motor is actually started by the drive signal from the induced voltage detection circuit until the motor is steadily rotated.

Further, when the activation fails, it is necessary to activate the activation again, and there is a problem that the activation takes more time.

Further, since the conventional speed error compensating filter for the brushless motor drive circuit is constructed as described above, when the disturbance in the low frequency range is large, the disturbance cannot be sufficiently compressed. As a result, there was a problem that the specifications of rotation accuracy could not be satisfied.

The conventional brushless motor drive circuit has a function of changing the frequency of the reference clock input to the speed error detector in proportion to the command rotation speed when the command rotation speed of the motor changes. There was a problem that it was necessary.

In the conventional brushless motor drive circuit, the commutation timing and the timing of increasing / decreasing the armature winding current are not synchronized, so that the resistance value of the armature winding and the winding It was not suitable for performing processing such as adding or subtracting a correction value determined by the current value being applied to the winding potential to the actual drive period.

Further, in the conventional brushless motor drive circuit, since the drive transistor is switched by the rectangular wave drive signal, there is a problem that noise is generated during commutation.

The present invention has been made in order to solve the above-mentioned problems, and there is no phase delay in the rotor position signal even when a load is applied, so that the rotor can be stably driven to rotate regardless of the transient state during steady state.
Another object of the present invention is to obtain a brushless motor drive circuit in which the lead processing is not complicated.

A further object of the present invention is to provide a drive circuit for a brushless motor that can accurately detect a rotor position signal even if a spike-like voltage fluctuation occurs in a terminal potential waveform due to switching of a drive transistor. .

A further object of the present invention is to obtain a drive circuit for a brushless motor capable of obtaining a speed signal without providing a dedicated speed detector.

A further object of the present invention is to obtain a drive system for a brushless motor that can be reliably started in the shortest time without being affected by load conditions.

A further object of the present invention is to obtain a brushless motor drive circuit that sufficiently compresses the external disturbance to provide highly accurate rotation even when the external disturbance in the low frequency range is large.

Further, according to the present invention, a drive circuit for a brushless motor capable of stably changing the rotation speed of the motor is obtained by switching the target rotation speed of the speed error detector and the gain element of the speed error compensation filter. The purpose is to

A further object of the present invention is to obtain a brushless motor drive circuit constructed so that the timing of commutation and the timing of increasing or decreasing the armature winding current are synchronized.

A further object of the present invention is to obtain a brushless motor drive circuit that produces less noise during commutation.

[0035]

A brushless motor drive circuit according to the present invention includes a winding terminal potential detecting means for each phase of a brushless motor which drives a rotor by a plurality of phases of armature windings, and an armature winding. Of the phase terminal potential correction means for adding / subtracting the correction value determined by the resistance of the winding and the winding current to / from the detection winding terminal potential of each phase only during the actual driving period, and the comparison means for comparing the magnitude of the phase terminal potential after the correction. The armature winding of each phase is applied and driven by the rotor position signal detected by the comparison means.

Another brushless motor drive circuit of the present invention is a winding terminal potential detecting means for each phase of a brushless motor for driving a rotor with a plurality of phases of armature windings, and a resistance and winding of the armature windings. A voltage difference correction means between each phase that adds or subtracts a correction value determined by the current to the winding terminal voltage difference between each phase only in the actual driving period,
A comparison means for comparing the magnitudes of the voltage differences between the phases after the correction is provided, and the armature winding of each phase is applied and driven by the rotor position signal detected by the comparison means.

Further, a rising / falling signal detecting means for the rotor position signal is provided, and the speed feedback control is performed by regarding the detection result of these signals as a detected speed signal.

Further, the period during which the drive signal to the bridge circuit for exciting and driving the armature winding of each phase is in a drive state is given to each phase terminal potential correcting means as an actual drive period signal.

Further, the period during which the drive signal to the bridge circuit for exciting and driving the armature winding of each phase is in a driving state is given to the inter-phase voltage difference correcting means as an actual drive period signal.

Further, an actual current detecting resistor connected in series to a bridge circuit for exciting and driving the armature winding is provided, and the current flowing through this detecting resistor is given to each phase terminal potential correcting means as a winding current.

Further, an actual current detecting resistor connected in series to a bridge circuit for exciting and driving the armature winding is provided, and the current flowing through this detecting resistor is given to the inter-phase voltage difference correcting means as a winding current.

Further, a differentiation circuit for detecting rising / falling edges of the comparison signal having a large / small terminal potential of each phase or a large / small voltage difference between the phases, and the comparison signal is latched at the timing when the edge is detected by the differentiating circuit. A latch circuit is provided, and the outputs of the respective latch circuits are combined to drive the armature winding of each phase as a rotor position signal.

Another brushless motor drive circuit according to the present invention is a rotation circuit for detecting a position signal of a rotor from a phase terminal potential of each phase or a voltage difference between phases of a brushless motor that drives a rotor with a plurality of phases of armature windings. Child position signal generation means and rising / falling edges of the rotor position signal of the above output are detected, the necessary edge signal is selected from each detected edge signal to be one output, and the necessary edge signal is counted and activated. The counter is used as an applied drive signal for the armature winding of each phase at the time, and one output of this counter is used as input, and pulse generation means for counting up the counter when this input is not obtained for a predetermined time is provided. Sometimes, the counter output is used to drive the armature winding.

Another brushless motor drive circuit of the present invention is a rotation circuit for detecting a position signal of a rotor from a phase-phase terminal potential of a brushless motor which drives a rotor by a plurality of phases of armature windings or a voltage difference between respective phases. Child position signal generation means and rising / falling edges of the rotor position signal of the above output are detected, the necessary edge signal is selected from each detected edge signal to be one output, and the necessary edge signal is counted and activated. A counter that uses an applied drive signal to the armature winding of each phase at the time, pulse output means that inputs one output of this counter, and counts up the counter when this input is not obtained for a predetermined time, and the above rotation Equipped with a steady rotation detection means that monitors the rotation of the motor by the combination of the slave position signal and the counter output, and outputs a restart pulse to start the motor in case of abnormal rotation. , When rotation abnormality has to perform the application operation of the armature winding at the counter output.

Further, at the time of starting or restarting, a switching means and a timer for switching to drive the armature winding of each phase based on the value of the counter in accordance with the rotor position signal in the subsequent steady state are provided to start or restart. The period is set by a timer so that it can be switched.

Further, there is provided switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of starting or restarting, and at the time of steady state thereafter, the counter is set to a predetermined value. When it comes to, it will be switched when the startup or restart period is over.

Further, switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of starting or restarting, and at the time of steady state thereafter, and a speed signal detecting means for the rotor. Is provided, and the switching is performed assuming that the start or restart period has ended when the detected speed signal reaches a predetermined speed.

Further, there is provided switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of starting or restarting, and at the time of steady state thereafter, by switching the armature winding of each phase. When the position signal reaches a predetermined combination of values, switching is performed assuming that the start or restart period has ended.

Further, there is provided switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of start-up or restart, and in the subsequent steady state by the rotor position signal. When the drive signal to the line reaches a predetermined combination of values, switching is performed assuming that the activation or restart period has ended.

Further, switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of starting or restarting, and at the subsequent steady state by the rotor position signal, and if necessary, a timer or a rotation. Provided with a speed signal detecting means for the child so that the time set by the timer elapses or the speed signal detection value reaches a predetermined speed, the counter reaches a predetermined value, or the detected rotor position signal reaches a predetermined combination value or each phase The drive signal to the armature winding is switched to a predetermined combination when a plurality of conditions are satisfied and the startup or restart period ends.

Further, when the rotor position signal input to the counter does not change for a predetermined time, the counter outputs a restart pulse as a rotation abnormality to start the counter, and counts itself.

Further, a position detector for detecting a position deviated from the rotor position signal detected from the phase potential of each phase or the voltage difference between each phase by an electrical angle π / 6, and the output of this position detector and a start instruction. A hold circuit for outputting a selection signal determined by the signal is provided, and the counter determines the combination of the drive signals to the armatures of the respective phases by the selection signal at the time of starting or restarting.

Furthermore, a position detector for detecting a position deviated from the rotor position signal detected from the phase potential of each phase or the voltage difference between each phase by an electrical angle π / 6, the output of this position detector and a start instruction. A hold circuit that outputs a selection signal determined by the signal is provided.The above position detector output is used for the first drive signal to the armature at the time of start-up or restart, and the counter is used for the subsequent drive at start-up or restart. Uses a signal that determines a combination of drive signals to the armatures of each phase by the selection signal.

Another brushless motor drive circuit according to the present invention further comprises, in addition to the basic configuration, a differentiating circuit for detecting rising and falling edges of a comparison signal having a large or small terminal potential of each phase or a large or small voltage difference between phases. The above-mentioned latch circuit is provided with a timer that operates by detecting the edge of the differentiating circuit and stops after a predetermined time, and a latch circuit that latches the comparison signal at the timing when the differentiating circuit detects the edge and releases the latch at the timing when the timer stops. The outputs are combined so that the armature winding of each phase is driven as a rotor position signal.

Furthermore, the timer time length from when the latch circuit latches the comparison signal to when it is unlatched is changed based on the command rotation speed to the armature.

Another brushless motor drive circuit of the present invention is a rotor position signal generating means for detecting a position signal of the rotor from terminal potentials of respective phases of a plurality of phases or a voltage difference between respective phases, and a rotor position of this output. A pulse generating means for detecting rising and falling edges of a signal, selecting a necessary edge signal from each detected edge signal and giving an output pulse train, and giving a pseudo pulse train when the necessary edge signal is not obtained for a predetermined time, A counter that counts the output of the pulse generating means, a steady rotation detecting means that outputs a rotation abnormality signal when the relationship between the rotor position signal and the counter value does not have a predetermined relationship, and the above-mentioned within the set time after starting and restarting. A restart pulse generation means for masking the rotation abnormality signal of the steady rotation detection means and outputting a restart pulse based on the rotation abnormality signal after a set time has elapsed is provided. For example, the startup is in restart setting time by restart pulse, and to perform application driving the armature windings by the counter output.

Further, a switching means and a timer are provided for switching to drive the armature winding of each phase based on the value of the counter at the time of starting or restarting, and based on the rotor position signal at the subsequent steady state. Alternatively, the restart period is set by a timer and switched.

In another brushless motor drive circuit of the present invention, a speed detection means for detecting the speed at which the rotor is rotating and a difference between the detected actual rotation speed of the rotor and the target rotation speed are used as a speed error. A speed error detecting means for outputting as a signal and a parallel circuit of a proportional / integral (PI) filter and a first-order lag filter, which has the detected speed error signal as an input, and an added value of each output of the parallel circuit. It is a series circuit with a first-order lag filter that is an input, and is provided with a speed error compensation filter that uses the added first-order lag output as a current command value to the armature winding.

Also, speed detecting means for detecting the speed at which the rotor is rotating, speed error detecting means for outputting the difference between the detected actual rotation speed of the rotor and the target rotation speed as a speed error signal, and The detected speed error signal is input, and its configuration is a parallel circuit of a series circuit of a proportional / integral filter and a first-order lag filter, and a first-order lag filter provided separately from this series circuit. A speed error compensating filter that uses the added value of each output as a current command value to the armature winding is provided.

Further, speed detecting means for detecting the speed at which the rotor is rotating, and speed error detecting means for outputting the difference between the detected actual rotation speed of the rotor and the target rotation speed as a speed error signal, A speed error compensation filter that obtains a current command value to the armature winding from the detected speed error signal is provided, and the target rotation speed of the speed error detection means and the speed according to the command rotation speed to the brushless motor drive circuit. The gain of the error compensation filter is changed.

Another brushless motor drive circuit of the present invention is a rotor position detecting means for detecting the relative position of the armature winding and the rotor, and a commutation control means for switching the energized phase at the detected rotor position. A speed detecting means for detecting the speed at which the rotor is rotating, a speed error detecting means for outputting a difference between the detected actual rotating speed of the rotor and a target rotating speed as a speed error signal, and this detecting means. A speed error compensation filter that obtains a current command value to the armature winding from the speed error signal is provided, and the energization phase is switched by the commutation control means to increase or decrease the current command value to the armature winding after a fixed time. I chose

Further, the maximum current is applied to the armature winding during the starting and restarting periods.

Another brushless motor drive circuit according to the present invention is a rotor position signal generating means for detecting a rotor position signal from a plurality of phase terminal potentials of a plurality of phases or a voltage difference between each phase, and a rotor position of this output. A pulse generating means for detecting rising and falling edges of a signal, selecting a necessary edge signal from each detected edge signal and giving an output pulse train, and giving a pseudo pulse train when the required edge signal is not a predetermined signal, A counter for counting the output of the pulse generating means is provided, and the armature winding is applied and driven by the counter output.

In another brushless motor drive circuit of the present invention, in addition to the basic configuration, a comparison is made to compare the terminal potential of each phase or the voltage difference correcting means between each phase with the terminal potential of each phase of the output or the voltage difference between each phase. A commutation circuit for obtaining an armature winding drive signal from the rotor position signal detected by the rotor position signal detecting means, and a trapezoidal drive signal generation circuit for processing the output of the commutation circuit into a trapezoidal drive signal. Further, the trapezoidal drive signal is supplied to the armature winding.

Further, the trapezoidal drive signal generating circuit is provided with a charging / discharging circuit, and the time constant of this charging / discharging circuit is changed by an external control signal to change the trapezoidal gradient.

Further, a phase advance circuit for advancing the phase of the rotor position signal is provided, and the phase advance amount of this phase advance circuit is set to be approximately 1/2 of the gradient time of the trapezoidal drive signal for driving the armature winding. I did it.

[0067]

In the brushless motor drive circuit according to the present invention, the detected winding terminal potential of each phase is corrected by the winding current voltage only during the actual driving period, and the signal of the comparison result of the corrected phase terminal potentials is output. The combination drives the armature.

In the brushless motor drive circuit according to the present invention, the detected winding terminal voltage difference between the phases is corrected by the winding current voltage only during the actual drive period, and the comparison result of the corrected phase difference between the phases is obtained. The armature is driven by the signal combination.

Further, the rising and falling signals of the rotor position signal are regarded as the detected speed signal and feedback control is performed.

Furthermore, the period during which the drive signal to the bridge circuit is in the drive state is set as the actual drive state and is set as the winding terminal potential correction period.

Further, the period during which the drive signal to the bridge circuit is in the drive state is set as the actual drive state, and is set as the correction period of the winding terminal voltage difference between the respective phases.

Further, the current flowing through the resistor connected in series to the bridge circuit is detected as a winding current and used as a correction voltage for the winding terminal potential.

Further, the current flowing through the resistor connected in series to the bridge circuit is detected as a winding current and used as a correction voltage for the winding terminal voltage difference between each phase.

Further, the magnitude comparison signal of each winding potential or the interphase voltage difference is once differentiated, and the comparison signal is latched at the timing when the differentiated signal is obtained to generate a new rotor position signal not affected by noise. It The armature winding is driven from the combination of these position signals.

In the brushless motor drive circuit according to the present invention, the required signal is selected from the rising and falling edges of the rotor position signal, and the armature winding is driven using this selected required signal at startup. It

In the brushless motor drive circuit according to the present invention, the required signal is selected from the rising and falling edges of the rotor position signal, the rotation state of the motor is monitored, and when the rotation is abnormal, the selected required signal is selected. Is used to drive the armature winding.

Further, the drive is switched from the start-up to the steady state, and the start-up period is determined by the set time corresponding to the timer.

Further, the drive is switched from the start-up to the steady-state, and the start-up period is determined by counting up the counter to a predetermined value.

Further, the drive is switched from the start-up to the steady-state, and the start-up period is determined by the fact that the detected speed of the rotor becomes a predetermined speed.

Further, the drive is switched from the startup to the steady state, and the startup period is defined by the detected rotor position signal becoming a predetermined value.

Further, the drive is switched from the startup to the steady state, and the startup period is determined by the drive signal to the armature becoming a predetermined value.

Further, the drive is switched from the start-up to the steady-state, and the start-up period has a plurality of set times, the set speed is reached, a predetermined number of counts, the rotor position signal is steady, and the drive signal to the armature is steady. It is established when the condition of is satisfied.

Further, the operation of the counter is monitored, and if there is no output, it is considered that the rotation is abnormal and the restart state is set.

Furthermore, the combination of the drive signals to the armature at the time of starting or restarting is determined by the position signal for detecting the position away from another predetermined electrical angle.

Further, according to another position signal for detecting a position separated by a predetermined electrical angle, the first drive signal at the time of starting or restarting is this position signal, and is sent to the armature at the time of subsequent starting or restarting. The combination of the drive signals of is determined by this position signal and other conditions.

Further, by latching the magnitude comparison signal of each winding potential or the interphase voltage difference at a predetermined timing for a predetermined time, a waveform-shaped rotor position signal having no fluctuation is obtained, and this rotor position signal is combined. The armature winding is driven from.

Further, the timer time for releasing the latch changes based on the command rotation speed from the outside to the armature.

The drive circuit for a brushless motor according to the present invention is switched to a forced energized phase in which the motor is normally rotated at the time of starting and restarting, and is rotated after a predetermined time has passed after starting or restarting. If it becomes abnormal, it will be restarted.

Further, the drive switching from the start-up to the steady state is set by the timer to ensure the transition.

In the brushless motor drive circuit according to the present invention, the speed error signal from the speed error signal to the armature winding is passed through the first-order lag filter which is arranged in parallel with the proportional-integral (PI) filter and which compresses the low-range disturbance. Converted to current command value.

In the brushless motor drive circuit of the present invention, the speed is passed through the first-order lag filter, which is arranged in parallel with the series circuit of the proportional-integral (PI) filter and the first-order lag filter, for compressing the low-range disturbance. The error signal is converted into a current command value for the armature winding.

In the brushless motor drive circuit according to the present invention, the target rotation speed and the gain of the speed error compensation filter change according to the command rotation speed to the motor, and the current command value from the speed error signal to the armature winding is changed. The resulting reference clock to the speed error detector may be constant.

In the brushless motor drive circuit of the present invention, an instruction to increase / decrease the amount of current to the armature winding is issued after a lapse of a fixed time after switching the energized phase.

In the brushless motor drive circuit of the present invention, the maximum current is applied to the armature at the time of starting and restarting, and the armature is surely started.

In the brushless motor drive circuit according to the present invention, the required signal within the rising and falling edges of the rotor position signal is selected, and the armature winding is driven by the counter value obtained by counting the required signal.

Further, means for processing the rectangular-wave drive signal to generate a trapezoidal drive signal is provided, and the armature winding is driven by this trapezoidal drive signal.

Further, the slope of the trapezoidal wave drive signal is changed by a control signal from the outside.

Further, the phase lead circuit makes the optimum commutation timing coincide with the approximate gradient center of the trapezoidal wave drive signal.

[0099]

【Example】

Example 1. The present invention detects the voltage of each phase armature winding and causes a phase delay if it is left as it is. Therefore, the correction voltage, which is the product of the load resistance and the current, is applied and corrected only in the actual load state, and correct in the actual load state. The terminal voltage in phase is obtained, and the drive voltage of each armature winding is generated by the commutation circuit based on this winding terminal voltage. Further, an example will be described in which an equivalent motor speed is detected from each phase armature winding voltage, and the detected speed is fed back to be used for speed control of the rotor. In this embodiment,
The configuration and operation of the brushless motor drive device based on this idea will be described. FIG. 1 is a block diagram showing the overall configuration of a first embodiment of a brushless motor drive device according to the present invention. In FIG. 1, reference numerals 12, 13, and 14 denote armature windings of a brushless motor in which a neutral-point non-grounded three-phase star is connected. Reference numeral 11 denotes an armature winding 12 by controlling energization of drive transistor groups TR1 to TR6. It is a bridge circuit that supplies a predetermined drive current to 13 and 14. Armature winding 12, 1
For convenience, 3 and 14 will be referred to as U phase, V phase, and W phase. 1 is a corrected terminal potential signal 1 by correcting the terminal potential
The terminal potential correction circuit 2 which outputs a, 1b, 1c compares the magnitudes of the corrected terminal potentials of the respective phases to the logic signal 2a,
Comparing circuit 3 for obtaining 2b, 2c, 3 is for logic signals 2a, 2b,
2c is a waveform shaping circuit that waveform-shapes rotor position signals 3a, 3b, and 3c, and a rotor position signal generation circuit 4 is configured by including the above-described members 1, 2, and 3. Reference numeral 5 is a terminal for inputting a motor rotation signal for enabling rotation of the motor, 6 is a pulse generation circuit, 7 is a counter circuit, 8 is a switching signal generation circuit, and a commutation circuit 9 is a rotor position signal generation circuit 4 , Drive signals 9a-9 depending on the states of signals input from the terminals 5, the counter circuit 7, and the switching signal generating circuit 8.
f is output to control the switching of the drive transistor groups TR1 to TR6.

FIG. 2 shows a specific configuration example of the terminal potential correction circuit 1. 2, 20 to 34 are npn transistors, 35 is a pnp transistor, 36 to 56 are resistors, 57 to 60 are constant current sources, the U-phase terminal potential is at the base of the npn transistor 20, and the base of the npn transistor 25. Is connected to the V-phase terminal potential, the base of the npn transistor 30 is input to the W-phase terminal potential, and the base of the pnp transistor 35 is connected to the terminal 61 to which the voltage related to the armature winding resistance drop is input. . Also, 62
Reference numerals 67 to 67 are terminals to which a correction switching signal for switching the correction of the terminal potential is input. The corrected terminal potential of each phase is output as 1a, 1b, 1c.

FIG. 3 shows a specific configuration example of the comparison circuit 2. In FIG. 3, 70 to 81 are resistors, 82 to 84 are differential amplifier circuits, and 85 to 87 are comparators, and resistors are provided at the non-inverting input terminal of the differential amplifier circuit 82 and the inverting input terminal of the differential amplifier circuit 83, respectively. The U-phase terminal potential 1a corrected via 70 and 75 is applied to the non-inverting input terminal of the differential amplifier circuit 83 and the inverting input terminal of the differential amplifier circuit 84 by resistors 74 and 79, respectively.
The V-phase terminal potential 1b corrected through V is corrected to the non-inverting input terminal of the differential amplifying circuit 84 and the inverting input terminal of the differential amplifying circuit 82 through the resistors 78 and 71, respectively. 1c has been entered. Differential amplifier circuits 82, 83,
The inverting input terminal of 84 is also connected to the output terminals of the differential amplifier circuits 82, 83, 84 via resistors 73, 77, 81.
Each output terminal is connected to the non-inverting input terminal of the comparator 85, 86, 87. Furthermore, the differential amplifier circuit 8
2, 83, 84 non-inverting input terminals and comparator 85,
The reference voltage Vref is input to the inverting input terminals of 86 and 87. The differential amplifier circuit 82 outputs the differential amplified signals 1a and 1c with Vref as the center voltage. The differential amplified signal and Vref are compared by the comparator 85 to obtain the logic signal 2a. Logic signals 2b and 2c are obtained in the same procedure.

FIG. 4 shows the relationship between the terminal potential waveform of each phase when the terminal potential is not corrected and no load, the logic signals 2a, 2b and 2c output from the comparison circuit 2, and the energized phase. It is a thing. Although a spike-like voltage fluctuation occurs in the actual terminal potential waveform during commutation, it is omitted here for simplification of description. When there is no load, the amount of current flowing is small, so the resistance drop in the armature winding can be almost ignored, and the terminal potential waveform becomes symmetrical as shown in Fig. 4 and has a predetermined phase relationship with the rotor. A logic signal can be obtained. On the other hand, FIG. 5 shows the relationship between the terminal potential waveform of each phase when the terminal potential is not corrected, the logic signals 2a, 2b and 2c output from the comparison circuit 2, and the energized phase when the load is applied. is there. When there is a load, the effect of resistance drop in the armature winding cannot be ignored because of the current flow. Of the two terminal potentials to be compared, one becomes a conducting phase and the other becomes a non-conducting phase. For example,
When switching the energization from V → W to U → W, V phase and U
Although the terminal potentials of the phases are compared, the V phase becomes the energized phase and the U phase becomes the non-energized phase. The voltage corresponding to the resistance drop is superimposed on the terminal potential waveform of the V phase, which is the energized phase. On the other hand, since no current flows in the U phase, only the counter electromotive voltage is generated at the terminal potential (the power supply voltage of the bridge circuit is fixed at V _cc , and the neutral point is ungrounded, so neutral). The potential at the point drops by the amount of resistance drop, and the terminal potential waveform actually observed is a form in which the terminal potential of the U phase, which is the non-conducting phase, is leveled down). Therefore, a shift occurs at the position where the potential levels of the V-phase terminal potential and the U-phase terminal potential match, and the phase of the obtained logic signal is delayed as compared with the case of no load, as shown by 2b in FIG. 5, for example. Will end up.

In order to solve the problem of the occurrence of this phase delay, the voltage of the resistance drop is added or subtracted from the terminal potential of the phase being energized, and then the terminal potentials are compared to determine the logical signal. The configuration may be such that 2a, 2b, and 2c are obtained. For example, for the U phase, the voltage for the resistance drop is subtracted when the U phase is energized to the V phase or the W phase, and the voltage for the resistance drop is added when the U phase is energized for the V phase or the W phase. It may be configured to do so.

The specific operation of the terminal potential correction circuit 1 will be described below with reference to the drawings. In FIG. 2, U,
Although the terminal potential correction circuits for V and W3 phases are shown, the description will be given here focusing on the terminal potential correction circuit for the U phase. First, consider the case where the terminals 62 and 63 are at the high level. At this time, since the collector potentials of the npn transistor 22 and the npn transistor 24 become 0, the emitter potentials of the npn transistor 21 and the npn transistor 23 also become 0, and no current flows through the resistors 37 and 40.
Therefore, the current flowing through the resistor 36 (resistance value R ₁ ) is only i ₁ supplied from the constant current source 57, and the potential observed at the output terminal of the U-phase terminal potential correction circuit is the input of the terminal potential correction circuit. The value is the value obtained by subtracting the base-emitter voltage (V _be ) of the transistor 20 and the resistance drop voltage at the resistor 36 from the value. 1a = U−V _be −R ₁ · i ₁ (1)

Next, consider the case where the terminals 62 and 63 are at the low level. It is assumed that a potential V _ir is input to the terminal 61. At this time, the collector potentials of the npn transistor 22 and the npn transistor 24 are V _ir.
+ V _be (V), the npn transistors 21 and n
The emitter potential of the pn transistor 23 becomes V _ir , and a current of V _ir / R ₂ flows through the resistor 37 (resistance value R ₂ ) and the resistor 40 (resistance value R ₂ ). Therefore, the current flowing through the resistor 36 is equal to i ₁ supplied from the constant current source 57 and the resistor 3
7, the current flowing through the resistor 40 is added, and the potential observed at the output terminal of the U-phase terminal potential correction circuit is as shown in equation (2). When the terminal 62 is at a high level and the terminal 63 is at a low level, or when the terminal 62 is at a low level and the terminal 63 is at a high level, only one of the resistor 37 and the resistor 40 has V _ir / R ₂ Since no current flows in, the potential observed at the output terminal of the U-phase terminal potential correction circuit is as shown in equation (3).

After all, when it is desired to add the voltage of the resistance drop (when V → U and W → U are energized), the terminals 62 and 63 are set to the high level, and the voltage of the resistance drop is subtracted ( The terminal potential can be corrected by setting the terminals 62 and 63 to a low level during (U → V, U → W energization). When it is not necessary to correct the U phase in the non-energized phase (V → W, W → V energized), the terminal 62 is set to the high level and the terminal 63 is set to the low level, or the terminal 62 is set to the low level. Should be set to a low level and the terminal 63 should be set to a high level. Similarly, for the V phase, when it is desired to add the voltage due to the resistance drop (when U → V and W → V are energized), the terminals 64 and 65 are set to the high level and the voltage due to the resistance drop is set. When it is necessary to subtract (when V → U and V → W are energized), the terminals 64 and 65 are set to a low level, and when it is not necessary to correct (when U → W and W → U are energized), the terminals are 64 is set to high level and terminal 65 is set to low level,
Alternatively, the terminal 64 may be set to low level and the terminal 65 may be set to high level. Furthermore, for the W phase, if you want to add the voltage due to the resistance drop (when U → W, V → W is energized), set terminals 66 and 67 to high level and subtract the voltage due to the resistance drop. If you want to (W → U, W → V energization)
Set terminals 66 and 67 to low level, and when there is no need for correction (when U → V, V → U is energized), set terminal 66 to high level and terminal 67 to low level. Alternatively, the terminal 66 may be set to the low level and the terminal 67 may be set to the high level. The energized phase and the terminal 62
FIG. 6B shows a timing chart in which the relationship of the correction switching signals input to .about.

FIG. 6A is a detailed circuit diagram of the specific correction switching signal generation circuit 16 for correcting the detected winding terminal potential for the product of resistance and current only during the actual driving period. In this embodiment, the rotor position signals 3a and 3 are used as inputs.
The switching signals shown in FIG. 6B are sent to the terminals 62 to 67 of the terminal potential correction circuit 1 by combining the logic elements by using b and 3c. Further, in this embodiment, as shown in FIG. 1, the current control circuit 211 and its buffer amplifier 21 are provided.
Since the winding current flowing through the armature is controlled by the resistor 2, the resistor 213, and the driving transistor 214, the correction circuit 1
The output of the current control circuit 211 is used for the terminal 61 of the.
The current control circuit 211 detects an error between the actual rotation speed and the command rotation speed from the logic pulse signal 201, and controls the amount of current supplied to the armature winding so that the detected error becomes zero. In addition, in this embodiment, the example applied to the three-phase brushless motor has been described, but it is obvious that the present invention can be applied to not only three-phase brushless motors but also multiple-phase brushless motors. Further, the means constituted by the transistor circuit in this embodiment may be constituted by an OP amplifier or a digital IC.

Example 2. In this embodiment, the armature winding voltage of each phase is detected, and the phase delay occurs as it is.Therefore, the correction voltage, which is the product of the load resistance and the current, is applied to the voltage difference of each phase only in the actual load state to correct The terminal voltage at the correct phase in the actual load state is obtained, and the commutation circuit is used to generate the drive voltage for each armature winding based on this winding terminal voltage. In the present embodiment, the configuration and operation of a brushless motor drive device based on this idea will be described. FIG. 8 is a block diagram showing the overall configuration of a second embodiment of the brushless motor drive device according to the present invention. In FIG. 8, the same members as in Example 1 are indicated by the same numbers. An inter-terminal voltage correction circuit 100 that corrects the inter-terminal voltage and outputs the corrected inter-terminal voltage signals 100a to 100f, compares the corrected inter-terminal voltage, and outputs the logical signal 1
A rotor position signal generation circuit 102 is configured including a comparison circuit 101 for obtaining 01a, 101b, 101c and a waveform shaping circuit 3.

FIG. 9 shows a specific configuration example of the inter-terminal voltage correction circuit 100. In FIG. 9, 110 to 127 are n
pn transistor, 128 is a pnp transistor, 12
9 to 155 are resistors, 156 to 162 are constant current sources,
The U-phase terminal potential is at the bases of the npn transistors 110 and 117, and the V-phase terminal potential is at the bases of the npn transistors 116 and 123.
The W-phase terminal potential is input to the base of 2, and the terminal 163 to which the voltage related to the armature winding resistance drop is input is connected to the base of the pnp transistor 128. Also, 1
Reference numerals 64 to 169 are terminals to which a correction switching signal for switching the correction of the terminal voltage is input. The corrected inter-terminal voltage is output as 100a to 100f.

A specific operation of the inter-terminal voltage correction circuit will be described with reference to the drawings. In FIG. 9, the power supply voltage is V _cc , the resistors 129, 131, 138, 140, 147,
The resistance value of 149 is R ₃ , the resistance values of the resistors 130, 139 and 148 are R ₄ , and the resistance values of the resistors 134, 135, 143 and 144,
The resistance values of 152 and 153 are R ₅ , and the constant current sources 156 and 15 are
7, the current value supplied from 159 to 162 is i ₂ , np
The base current of the n-transistor is i _b , and the voltage input to the terminal 163 is V _ir .

First, consider the case where the terminal 164 is at a high level. At this time, the emitter potential of the npn transistor 113 becomes 0, and no current flows through the resistor 134.
A current (U−W) / R ₄ flows through the resistor 130 in the direction from the emitter terminal of the npn transistor 110 to the emitter terminal of the npn transistor 111. Therefore, the current flowing through the resistor 129 is i ₂ + (U−W) / R
_4- i _b , and 100a output from the inter-terminal voltage correction circuit 100 is as shown in equation (4). On the other hand, when the terminal 164 is at a low level, a current of V _ir / R ₅ also flows through the resistor 134, and the inter-terminal voltage correction circuit 10
100a output from 0 is as shown in Expression (5). Considering the same procedure for other terminal voltages, the logic levels of terminals 164-169 and 100a-100
The relationship of f is as shown in FIG.

FIG. 11 shows a concrete configuration example of the comparison circuit 101. In FIG. 11, 170 to 172 are comparators. Comparators 170 are 100b and 100a
To output the logic signal 101a, and the comparator 1
71 compares 100d and 100c to obtain a logical signal 101b
And the comparator 172 compares 100f with 100e and outputs the logic signal 101c. Comparison circuit 101
Consider the concrete operation of. Terminal 164 and terminal 1
When 65 is at the high level, the comparator 170 outputs the logic signal 101a of U> W. Terminal 164
There When pin 165 at the low level is high _{is, {U + (R 4 ·} V ir) / (2 · R 5)}> W becomes logic signal 101a is output. Conversely, if the terminal 164 is at high level and the terminal 165 is at low level, {U
-(R ₄ · V _ir ) / (2 · R ₅ )}> W logical signal 1
01a is output.

As shown in FIG. 5, when the U-phase and W-phase terminal potentials match, the rotor position is detected by U
→ V to W → V when energizing is switched and V → U to V
→ It is the time to switch the energization to W. In either case, the U phase is the energized phase and the W phase is the deenergized phase at the time of comparison, so a voltage corresponding to the resistance drop is superimposed on the U phase terminal potential. . Therefore, it is necessary to correct the voltage corresponding to the resistance drop from the U-phase terminal potential at the time of comparison. U → V to W →
When switching the energization to V, it is necessary to subtract the voltage of the resistance drop from the U-phase terminal potential, and when switching the energization from V → U to V → W, add the voltage of the resistance drop to the U-phase terminal potential. There is a need. Therefore, (R ₄ · V _ir ) / (2
- R ₅₎ to set the manner R4, R5 becomes the voltage of the armature winding ohmic drop, high level of terminal 164 at the time of U → V current supply, the terminal 165 to the low level, at the time of V → U current supply Terminal 164 is low level and terminal 165 is high level.
If the level is set, the U-phase terminal potential and the W-phase terminal potential corrected for the voltage due to the resistance drop are compared to obtain the logic signal 101a, so that the same effect as that of the first embodiment can be obtained. is there.

The same procedure can be applied to other inter-terminal voltages, and when V → W is applied, the terminal 166 goes high.
Level, terminal 167 is low level, when W → V is energized, terminal 166 is low level, terminal 167 is high level, when W → U is energized, terminal 168 is high level, terminal 169 is low level, Terminal 16 when energizing U → W
If 8 is set to a low level and terminal 169 is set to a high level, the same effect as that of the first embodiment can be obtained.
FIG. 12 shows the relationship between the energized phase and the correction switching signals input to the terminals 164-169.

Example 3. In the present embodiment, each phase armature winding voltage described in the first embodiment is detected, and a correction voltage that is a product of load resistance and current is applied and corrected only in the actual load state, and then in the actual load state. The commutation circuit generates a drive signal for each armature winding based on the terminal voltage at the correct phase of the above, and the drive signal is used as the correction switching signal at this time. In the present embodiment, the configuration and operation of a brushless motor drive device based on this idea will be described. FIG. 13 is a block diagram showing the overall configuration of the third embodiment of the brushless motor drive device according to the present invention. Example 1 in FIG.
The same members as those shown in FIG. In this embodiment, the drive signals 9a, 9b, 9c, 9d, 9e, 9f are the terminal 63, the terminal 65, the terminal 67, and the terminal 6 of the terminal potential correction circuit 1, respectively.
2, input to the terminals 64 and 66.

The correction switching signal shown in FIG. 6 of the first embodiment is a signal synchronized with commutation. Therefore, the drive signal for sequentially switching the drive transistors TR1 to TR6 can be used as the correction switching signal. FIG. 7 shows the relationship between the energized phase and the drive signals 9a to 9f when the bridge circuit 11 is configured as shown in FIG. Correction switching signals and drive signals 9d and 9a for the terminals 62, 63, 64, 65, 66, and 67 of FIG.
9e, 9b, 9f and 9c match each other. Therefore, an embodiment of the brushless motor drive device according to the present invention can be configured as shown in FIG.

Example 4. The present embodiment is an example in which the second embodiment and the third embodiment are combined. That is, the armature winding voltage of each phase is detected, and the correction voltage, which is the product of the load resistance and the current, is applied to the voltage difference of each phase only in the actual load state to correct it, and based on the terminal voltage at the correct phase. The commutation circuit generates the drive signal for each armature winding, and the correction switching signal at this time is obtained from the drive signal. FIG. 14 is a block diagram showing the overall construction of the fourth embodiment of the brushless motor driving device of the present invention. 14, the same members as those in the second embodiment are designated by the same reference numerals. In the present embodiment, the drive signal 9a is applied to the terminals 165 and 168 of the inter-terminal voltage correction circuit 100 and the drive signal 9b is applied.
Are terminals 164 and 167 of the inter-terminal voltage correction circuit 100.
In addition, the drive signal 9c is applied to the terminal 1 of the inter-terminal voltage correction circuit 100.
66, and input to the terminal 169.

In the case of correcting the inter-terminal voltage, it is possible to use a drive signal for sequentially switching the drive transistors TR1 to TR6 as the correction switching signal, as in the third embodiment. For example, the correction switching signal input to the terminal 164 may be high level when U → V is energized and low level when V → U is energized.
Can be used. Similarly, the driving signals 9a and 9d are input to the correction switching signal input to the terminal 165, and the driving signals 9c and 9c are input to the correction switching signal input to the terminal 166.
9f, drive signals 9b and 9e for the correction switching signal input to the terminal 167, drive signals 9a and 9d for the correction switching signal input to the terminal 168, and drive signal 9c for the correction switching signal input to the terminal 169. , 9f can be used. Therefore, one embodiment of the brushless motor drive device according to the present invention can be configured as shown in FIG.

Example 5. In this embodiment, a sense resistor for detecting a load current is provided as a load current value when a correction voltage, which is a product of a load resistance and a current, is applied only in an actual load state, and an actual load current is obtained with this detected voltage. I chose In the present embodiment, the configuration and operation of a brushless motor drive device based on this idea will be described. In FIG. 15, the same members as in Example 1 are indicated by the same numbers. In this embodiment, TR4 to T
Common emitter terminal of R6 and terminal 6 of terminal potential correction circuit 1
1 is connected.

In FIG. 15, since the resistor 10 is connected to the common emitter terminals of the drive transistors TR4 to TR6, the current flowing through the armature winding also flows through the resistor 10. Therefore, it is possible to detect the amount of current flowing through the armature winding as the voltage drop across the resistor 10. The current flowing through the armature winding is I _L , the resistance value of the armature winding resistance for one phase is r, and the resistance value of the resistor 10 is R _s
Then, the resistance drop in the armature winding is I _L · r, terminal 6
The potential input to 1 is I _L · R _s . Since the voltage corrected by the terminal potential correction circuit is R ₁ · I _L · R _s / R ₂ , set R ₁ , R ₂ , and R _s so that this value is equal to I _L · r. good.

Example 6. An example in which the idea of the fifth embodiment is applied to the second embodiment will be described. FIG. 16 is a block diagram showing the overall configuration of a sixth embodiment of the brushless motor driving device of the present invention. In FIG. 16, the same members as those in the second embodiment are indicated by the same numbers. In this embodiment, the common emitter terminals of TR4 to TR6 and the terminal 163 of the inter-terminal voltage correction circuit 100 are connected.

Even when the terminal voltage is corrected, the amount of voltage related to the armature winding resistance drop is TR4 as in the fifth embodiment.
It is possible to detect from the common emitter terminal of TR6 to TR6, and one embodiment of the brushless motor driving device of the present invention can be configured as shown in FIG.

Example 7. In the above embodiments, the operation has been described assuming that the waveform is an ideal waveform with no disturbance. However, in reality, noise is added to the waveform, chattering occurs in the operation, and spike-like noise described in FIG. 18 and subsequent figures is mixed. An example in which normal operation is performed even with such a waveform will be described. In the present embodiment, such consideration is taken into consideration, and the detection signal waveform is once restored to a correct and stable shape by the waveform shaping circuit, and then the correction and driving described in the above embodiment are attempted. FIG. 17 shows a specific configuration example of the waveform shaping circuit 3. In FIG. 17, 180
Is a latch circuit, 181-186 are D flip-flops,
187 to 189 are EOR circuits, 190 is an OR circuit, 19
1 is a monostable multivibrator. FIG. 18 shows the terminal potential waveform and the signal waveform of each part of the waveform shaping circuit in the steady rotation state, and FIG. 19 is an enlarged view of the time T0 to T1 in FIG.

The specific operation of the waveform shaping circuit will be described with reference to FIGS. The input signal to the waveform shaping circuit is the logic signal 2a, 2b, 2c or 101a, 1 output from the comparison circuit 2 or the comparison circuit 101.
01b and 101c. In the first and second embodiments, the spike-like voltage fluctuation generated in the terminal potential waveform due to the switching of the driving transistor has been ignored, but in reality, the spike-like voltage fluctuation occurs in the terminal potential waveform. appear. Naturally, the voltage fluctuation remains in the terminal potential waveform in which the armature winding resistance drop is corrected. Therefore, the logic signals 2a, 2b, 2 obtained by comparing the terminal potentials with each other.
c includes spike-like noise as shown in FIG.

This logic signal is first sent to the latch circuit 180.
Is input to The latch circuit 180 has an enable terminal 1
It is a circuit that performs a latch operation according to the state of 80a, and outputs the input data as it is when the enable terminal 180a is at the high level. When the enable terminal 180a goes low, the input data is latched and the enable terminal 1
While 80a is low level, it continues to output the latched data. In the initial state, the enable terminal 180a of the latch circuit 180 is at high level, and the logic signal 2a,
2b and 2c are respectively the D flip-flops 181 and
183 and 185. D flip-flop 18
1 to 186 and EOR circuits 187 to 189 form a double-edge differentiating circuit, and the EOR circuits 187 to 189 output differential pulses at the rising and falling edges of the logic signals 2a, 2b, and 2c. At time T2, when the corrected potential levels of the terminal potentials 1a and 1c match and the polarity of 2a changes, an edge is detected by the both-edge differentiating circuit, and a differential pulse 203 is generated. EOR
The output signals of the circuits 187 to 189 are combined by the OR circuit 190 to become the logic pulse signal 201, which is input to the monostable multivibrator 191. The monostable multivibrator 191 triggers the rising edge of the logic pulse signal 201 and outputs a low-level pulse 204 for a fixed time T3. The pulse 204 is input to the enable terminal 180a of the latch circuit. Enable terminal 18
Since 0a becomes low level, the latch circuit 180 latches the logic signals 2a, 2b, 2c, and continues to output the latched data while the pulse 204 is low level. D
Output signal 1 of flip-flops 182, 184, 186
95, 196, and 197 become waveform-shaped rotor position signals 3a, 3b, and 3c, which are input to the next-stage commutation circuit 9 to perform commutation operation. When the commutation operation is performed, the drive transistor is switched, so that a spike-like voltage fluctuation occurs in the U-phase terminal potential waveform, and as a result, spike-like noise 205 is generated in 2b at an undesired position. However, at the time when the spike noise 205 occurs, the data input to the latch circuit is disabled by the pulse 204 from the monostable multivibrator 191. Therefore, the spike noise 205
Is masked by the latch circuit 180, and spike-shaped noise does not occur in the rotor-shaped signals 3a, 3b, 3c whose waveform has been shaped.

In the waveform shaping circuit 3 described above,
Logic pulse signal 201 output from OR circuit 190
Is a signal obtained at constant time intervals during steady rotation. Therefore, this logic pulse signal 201 can be used as a speed signal for controlling the rotation speed. Although the example of the three-phase brushless motor has been described in the present embodiment, the present invention is not limited to the three-phase brushless motor and can be applied to general brushless motors having a plurality of phases.

Example 8. Next, the configuration and operation of the device that is stably started in a short time without being affected by the load at the start will be described. That is, at the time of start-up, driving is started so that possible combinations of signals can be obtained from the detected voltages for each phase. Specifically, the position signal of the rotor is detected from the winding potential of each phase of the brushless motor, and the rising and falling edges of this rotor position signal are detected and selected to obtain the required edge signal. The edge signal was counted and used as the applied drive signal for the armature winding of each phase at startup. Furthermore, when this input cannot be obtained for a certain period of time, the applied drive signal is forcibly given. FIG. 20 shows an overall configuration diagram of an embodiment of a drive unit for a three-phase brushless motor based on the above idea. 9 is a drive signal 9a, 9b, 9c, 9
A commutation circuit for outputting d, 9e, 9f, a bridge circuit 11 for energizing a predetermined phase of the brushless motor, and a rotor position signal generation circuit for generating position signals 3a, 3b, 3c from respective terminal potentials of the brushless motor. , 7 are position signals 3a,
Detects rising and falling edges of 3b and 3c
A counter circuit 6 which selects and obtains a necessary edge signal and counts the necessary edge signal, and 6 represents a pulse generation circuit which outputs a pseudo pulse 6a.

Details will be described below. Motor rotation signal 5a
Is a signal input from the outside. When enabled, it indicates rotation, and when disabled, it indicates stop. In this embodiment, enable is high and disable is low.

In FIG. 20, the motor rotation signal 5a is connected to the commutation circuit 9 and the counter circuit 7. Drive signals 9a, 9b, 9c, 9d, 9 output from the commutation circuit 9
e and 9f are transistors TR1, TR2, TR3,
It is connected to the bases of TR4, TR5, and TR6. In this embodiment, the transistors TR1, TR2 and TR3 are pnp.
Type transistors, transistors TR4, TR5, TR
Reference numeral 6 is an npn-type transistor. In addition, the emitters of the transistors TR1, TR2, and TR3 serve as power sources,
The collector is connected to the collectors of the transistors TR4, TR5, TR6, and the transistors TR4, TR5, TR6 are connected.
The emitter of is connected to the ground via the resistor 10. The bridge circuit 11 is configured by these transistor groups. Further, the transistors TR1, TR2, TR3, T
The collectors of R4, TR5, and TR6 are connected to the terminals of the U-phase, V-phase, and W-phase armature windings that are star-connected in the three-phase brushless motor. Therefore, each armature winding is energized by turning on / off each transistor. Figure 2
Drive signals 9a, 9b, 9c, 9 in the present embodiment.
The relational table of d, 9e, 9f and the energized phase is shown. FIG. 21 shows FIG.
Is shown in the table. If the energized phases are switched in the order indicated by the arrows in FIG. 21, the rotor will rotate normally.

The terminals of each armature winding connected to the bridge circuit 11 are also connected to the rotor position signal generating circuit 4. In the rotor position signal generation circuit 4, the U phase, V phase,
3-bit position signal 3 from W-phase terminal voltages U, V, W
a, 3b, 3c are generated. FIG. 22 shows an example of the logical relationship between the drive signals 9a, 9b, 9c, 9d, 9e, 9f and the position signals 3a, 3b, 3c in this embodiment. Position signals 3a, 3b, 3c output from the rotor position signal generation circuit 4
Is input to the counter circuit 7.

FIG. 2 is a block diagram of the counter circuit 7 of this embodiment.
3 shows. The position signals 3a, 3b, 3c are input to the rising edge detection circuits 250, 252, 254 and the falling edge detection circuits 251, 253, 255, respectively.
Rising edge detection circuits 250, 252, 254 generate rising edge pulses 250a, 252a, 254a.
However, the falling edge detection circuit outputs falling edge pulses 251a, 253a, 255a. Detected edge pulses 250a, 252a, 254a, 25
1a, 253a, 255a are input to the pulse selection circuit 256. Further, the pseudo pulse 6a output from the pulse generation circuit 6 shown in FIG. 20 is also input to the pulse selection circuit 256. Pulse train 7 output from the pulse selection circuit 256
d is input to the counter. In this embodiment, the pulse train 7
A hexadecimal counter 257 is used as a counter for counting d. FIG. 24 shows an example of the logical relationship between the number of pulses input and the output value of the hexadecimal counter 257 used in this embodiment. When the number of input pulses is 6 or more in the figure, the counter values 7a, 7
b and 7c are counted again from low-low-low. The pulse train 7d is also input to the pulse generation circuit 6 in FIG. 20, and thus is output from the counter circuit 7. The counter values 7a, 7b output from the hexadecimal counter 257,
7c is input to the pulse selection circuit 256 in the counter circuit 7 and the commutation circuit 9 in FIG. Pulse selection circuit 25
6 refers to the current counter values 7a, 7b, 7c,
The edge pulse or the pseudo pulse 6a of the theoretical position signal to be detected next is output at the time of forward rotation. In this embodiment, the counter values 7a, 7b, 7c and theoretical edge pulses 250a, 252a, which should be detected next at the time of normal rotation, are detected.
FIG. 25 shows an example of the logical relationship between 254a, 251a, 253a and 255a. From FIG. 25, for example, the counter value 7
When a, 7b, and 7c are low-low-low, the edge pulse 253a is output, and another edge pulse 250a is output.
Is not output even if is input. However, the pseudo pulse 6a is
When input, it is output regardless of the counter values 7a, 7b, 7c.

FIG. 26 shows a block diagram of the pulse generation circuit 6 of this embodiment. In this embodiment, the pulse generation circuit 6 is provided with a retriggerable one shot 260 and a rising edge detection circuit 2.
61. The pulse train 7d output from the pulse selection circuit 256 is input to the retriggerable one-shot 260. Output 260a of retriggerable one shot 260
Is input to the rising edge detection circuit 261 and the rising edge detection circuit 25 provided in the counter circuit 7
Similarly to 0, 252, 254, the rising edge of the output 260a of the retriggerable one shot 260 is detected,
The pseudo pulse 6a is output. In such a configuration,
When the pulse of the pulse train 7d is input within the time set in the retriggerable one shot 260, the retriggerable one shot 260 is cleared, the output 260a does not change, and therefore the pseudo pulse 6a is not output. However, when the pulse train 7d is not input within the set time, the output 260a of the retriggerable one shot 260 is output.
Changes from low to high, its rising is detected and the pseudo pulse 6a is output.

In the present embodiment, the output 260a is low when the retriggerable one-shot 260 is cleared, and changes to high when the pulse train 7d is not input within a predetermined time. A similar pseudo pulse 6a can be obtained even if the detection circuit is used and the output 260a is high when the retriggerable one shot 260 is cleared and changes to low when the pulse train 7d is not input within a predetermined time.

The commutation circuit 9 sets the drive signals 9a, 9b, 9c to high and the drive signal 9 when the motor rotation signal 5a is low.
By setting d, 9e, and 9f to low, the transistor group of the bridge circuit 11 is turned off, and the brushless motor is turned off. Next, in the start-up mode immediately after the motor rotation signal 5a becomes high, the drive signals 9a, 9b, 9b,
9c, 9d, 9e and 9f are output. FIG. 27 shows an example of a logical relationship combination of the drive signals 9a, 9b, 9c, 9d, 9e, 9f set in this embodiment and the output values 7a, 7b, 7c of the counter circuit 7. Drive signals 9a, 9 are shown in the direction of the arrow in the figure.
Rotating the rotor normally by switching b, 9c, 9d, 9e and 9f.

Next, the operation of the brushless motor in this embodiment will be described. Immediately after the motor rotation signal 5a becomes high, the counter values 7a, 7b, 7c become low-low-low, so that the drive signal 9b becomes low from FIG.
9f becomes high, and the VW phase is energized from FIG.
At this time, the rotor of the brushless motor may rotate in the normal direction to change the position signal, may rotate in the reverse direction to change the position signal, or may stop at the energization stable point and not change the position signal.

First, the case where the rotor rotates normally will be described. FIG. 28 shows an example of signal waveforms at various parts when the rotor rotates in the normal direction. When the VW phase is energized, the position signals 3a, 3b, 3c become high / high / low according to FIGS. 21 and 22. At this time, the counter values 7a, 7b, 7c are low
Since it is low, the hexadecimal counter 2 is used unless the edge pulse 253a or the pseudo pulse 6a is detected from FIG.
57 is not counted. When the rotor further rotates in the forward direction due to the inertia, the terminal voltages U, V, W change due to the counter electromotive force generated in the armature winding, and the position signals 3a, 3b, 3c change to high / low / low. 28,
The edge pulse 253a is detected as shown in (A). Therefore, the hexadecimal counter 257 counts up and the counter values 7a, 7b, 7c become high / low / low, and the commutation circuit 9 drives the U-W phase from FIG. 21 and FIG. 9a, 9b, 9c, 9d, 9e, 9
Set f to low-high-high-low-low-high.
Then, after that, the counter values 7a, 7
The brushless motor is started by sequentially switching the energized phases according to the relationship shown in FIG. 27 with reference to the combination of b and 7c.

Next, the case where the rotor reversely rotates and the position signal changes will be described with reference to FIG. FIG. 29 shows an example of signal waveforms at various parts when the rotor is reversed. When the rotor rotates in the reverse direction, the position signal 3a changes and the edge pulse 251a shown in (B) of FIG. 29 is detected, but since the edge pulse 253a is not detected as described above, the hexadecimal counter 257 counts. I won't up. Then, because it can not detect the edge pulse 253a within a predetermined time t _1, the pseudo pulse 6a from the pulse generating circuit 6 as shown in (C) in FIG. 29 is output. The hexadecimal counter 257 counts up with the pseudo pulse 6a, and the counter values 7a, 7b, 7c change from high to low. 21 and 27, the drive signals 9a, 9b, 9c, 9d and 9 are applied so that the U-W phases are energized in the commutation circuit 9.
Set e and 9f to low-high-high-low-low-high. As a result, the rotor rotates in the normal direction, and thereafter the counter values 7a, 7b,
The brushless motor is started by sequentially switching the energized phases according to the relationship shown in FIG. 27 with reference to the combination of 7c.

Further, even when the rotor does not move and the position signal does not change, the edge pulse 253a cannot be detected within the predetermined time t ₁ as in the case of the reverse rotation, so the pulse generation circuit 6 outputs the pseudo pulse 6a. Then, the hexadecimal counter 257 counts the pseudo pulse 6a as in the case of the reverse rotation, and the energized phase is switched to the UW phase from FIGS.
The brushless motor is started by sequentially switching the energized phases according to the relationship shown in FIG. 27 with reference to the combination of b and 7c.

Example 9. Next, the configuration and operation of a device that stably restarts in a short time even if the motor is stopped for some reason during operation and restart is required will be described. Specifically, at restart, the rotor position signal is detected from each phase winding potential of the brushless motor, and the rising and falling edges of this rotor position signal are detected and selected to obtain the required edge signal. Further, a steady rotation detection circuit for monitoring the rotation of the motor in combination with this signal is provided. The edge signal was counted at the time of abnormality detection and used as the forced application drive signal for the armature winding of each phase at restart. FIG. 30 shows an overall configuration diagram of a ninth embodiment of a drive unit for a three-phase brushless motor based on the above idea. Since the bridge circuit 11, the rotor position signal generation circuit 4, the counter circuit 7, and the pulse generation circuit 6 are the same as those in the eighth embodiment, their description will be omitted. Reference numeral 265 is a steady rotation detection circuit for comparing the counter values 7a, 7b, 7c with the position signals 3a, 3b, 3c.

In this embodiment, the position signals 3a, 3b,
3c is also input to the commutation circuit 9. In the start-up mode, the commutation circuit 9 has counter values 7a and 7b, as in the eighth embodiment.
Drive signals 9a, 9b, 9c, 9 depending on the combination of 7c
d, 9e, 9f are output and the position signal 3 is output during steady rotation.
drive signals 9a, 9b, depending on the combination of a, 3b, 3c,
It is configured to output 9c, 9d, 9e and 9f. Also, the position signals 3a, 3b, 3c and the counter value 7
The signals a, 7b and 7c are also input to the steady rotation detection circuit 265. During steady rotation, the steady rotation detection circuit 265 detects the position signals 3a, 3b, 3 after a predetermined time after the counter value has changed.
c and the counter values 7a, 7b, 7c are compared. The position signals 3a, 3b, 3c and the counter value 7a in the present embodiment,
FIG. 31 shows an example of a theoretical logical relationship combination of 7b and 7c. If the combination is not the one shown in FIG. 31, the restart pulse 265a is output. The restart pulse 265a is input to the commutation circuit 9.

An example of a case where the rotor stops due to some load during steady rotation in such a configuration will be described with reference to FIG. In FIG. 32, it is assumed that the rotor stops after (D). In this case, the pseudo pulse (p2) is output from the pulse generation circuit 6 after the time t ₁ set in the pulse generation circuit 6 has elapsed from the pulse (o1). The pseudo pulse (p2) is output from the pulse selection circuit 256 to the pulse train 7
is output as a pulse (o2) of d, and the counter value 7a,
7b and 7c change from low-high-low to low-low-high according to the logical relationship example of FIG. During steady rotation, as described above, the drive signals 9a, 9b, 9c, 9d, 9e, 9f are output according to the combination of the position signals 3a, 3b, 3c, so the counter values 7a, 7b, 7c change. Does not switch the energized phase. Then, the counter values 7a, 7
After a predetermined time t ₂ from the change of b and 7c, the steady rotation detection circuit 265 detects the position signals 3a, 3b and 3c and the counter value 7
Comparison of a, 7b, and 7c is performed. In this case, from FIG. 31, since the combination is not theoretical, the steady rotation detection circuit 2
A restart pulse (q3) is output from 65, and the mode shifts to the start mode. In the start-up mode, as described above, the start-up signals 9a, 9a are generated by the combination of the counter values 7a, 7b, 7c.
Since b, 9c, 9d, 9e, and 9f are output, drive signals 9a, 9b, 9c, 9d, 9e, and 9f from FIG.
Becomes high / high / low / low / high / low and the energization is switched to rotate forward. After that, as described in the eighth embodiment, the energization is sequentially switched by the combination of the counter values 7a, 7b, 7c according to the relationship shown in FIG. 27 until the steady rotation.

Example 10. Next, a motor drive circuit provided with a switching device from startup or restart to steady operation will be described. In this embodiment, this switching is set as a time, and after a certain time, the operation is switched to the steady operation. FIG. 33 shows an overall configuration diagram of a tenth embodiment of a driving apparatus for a three-phase brushless motor according to the present invention. The bridge circuit 11, the rotor position signal generation circuit 4, the counter circuit 7, the pulse generation circuit 6, and the steady rotation detection circuit 265 are the same as those in the eighth and ninth embodiments. Reference numeral 8 is a commutation circuit 9 for driving signals 9a and 9a.
A switching signal generation circuit for outputting a switching signal 8a for switching which of the counter values 7a, 7b, 7c and the position signals 3a, 3b, 3c is referred to when outputting b, 9c, 9d, 9e, 9f. Is. Hereinafter, the switching signal generation circuit 8
Will be explained.

In this embodiment, the motor rotation signal 5a and the restart pulse 265a are input to the switching signal generation circuit 8. The switching signal 8a is input to the commutation circuit 9. FIG. 34 shows a block diagram of the switching signal generating circuit 8 of this embodiment. In this embodiment, the switching signal generating circuit 8 is composed of the timer 270.

Next, the operation of the switching signal generating circuit 8 of this embodiment will be described with reference to FIG. In this embodiment, the timer 270
27, the timer 270 is turned on, and the commutation circuit 9 drives the drive signals 9a, 9b, 9c, 9d by the combination of the counter values 7a, 7b, 7c according to the relationship shown in FIG. 9e and 9f are output. Then, after the elapse of the predetermined time t ₀ , the switching signal 8a changes from low to high, and the commutation circuit 9 causes the position signals 3a, 3
Drive signals 9a, 9b, 9c, 9d, 9e, and 9f are output as shown in FIG. 22 using the combination of b and 3c.

Further, the commutation circuit 9 uses the position signals 3a, 3b,
Drive signals 9a, 9b, 9c, 9 depending on the combination of 3c
When outputting d, 9e and 9f, the steady rotation detection circuit 2
When the restart pulse 265a of 65 output is input, the timer 270 is reset and the switching signal 8a changes from high to low. As a result, the commutation circuit 9 causes the counter value 7
drive signals 9a, 9b, 9c, 9 using a, 7b, 7c.
It outputs d, 9e and 9f. Then, again, the predetermined time t ₀
After that, the switching signal 8a changes from low to high, and the commutation circuit 9 uses the combination of the position signals 3a, 3b and 3c.
Drive signals 9a, 9b, 9c, 9d, 9e,
9f is output.

In this embodiment, the switching signal 8a is set to low when referring to the counter values 7a, 7b and 7c, and set to high when referring to the position signals 3a, 3b and 3c. Good.

Example 11. In this embodiment, during the switching operation, the counter counts a constant value and then switches to the steady operation. By doing so, the motor can be reliably rotated. FIG. 36 shows an overall configuration diagram of an eleventh embodiment of a drive device for a three-phase brushless motor according to the present invention. 8C is
In the commutation circuit 9, drive signals 9a, 9b, 9c, 9d, 9e,
When outputting 9f, the switching signal generation circuit outputs a switching signal 8a for switching which of the counter values 7a, 7b, 7c and the position signals 3a, 3b, 3c is referred to. The switching signal generating circuit 8C will be described below.

In the present embodiment, the pulse train 7d, the motor rotation signal 5a and the restart pulse 265a are the switching signal generating circuit 8C.
Is input to The switching signal 8a is input to the commutation circuit 9. FIG. 37 shows a block diagram of the switching signal generating circuit 8C of this embodiment. In this embodiment, the switching signal generating circuit 8C is composed of the mode switching counter 271.

Next, the operation of the switching signal generating circuit 8C of this embodiment will be described with reference to FIG. Mode switching counter 27
1 is the pulse train 7 when the motor rotation signal 5a becomes high.
The counting of d is started, and the commutation circuit 9 outputs drive signals 9a, 9b, 9c, 9d, 9e and 9f according to the combination of the counter values 7a, 7b and 7c according to the relationship shown in FIG. Then, the mode switching counter 271 displays the pulse train 7d.
After counting X times a predetermined number of times, the switching signal 8a changes from low to high, and the commutation circuit 9 uses the combination of the position signals 3a, 3b, 3c as shown in FIG.
9b, 9c, 9d, 9e and 9f are output.

Further, the commutation circuit 9 uses the position signals 3a, 3b,
Drive signals 9a, 9b, 9c, 9 depending on the combination of 3c
When outputting d, 9e and 9f, the steady rotation detection circuit 2
When the restart pulse 265a having 65 outputs is input, the mode switching counter 271 is reset and the switching signal 8a changes from high to low. As a result, the commutation circuit 9 becomes
Drive signals 9a, 9b, 9c, 9d, 9e, 9f are output using the counter values 7a, 7b, 7c according to the relationship shown in FIG. Then, the mode switching counter 271 starts counting the pulse train 7d again, and after counting X times a predetermined number of times, the switching signal 8a changes from low to high, and the commutation circuit 9 causes the commutation circuit 9 to combine the position signals 3a, 3b, 3c. Drive signals 9a, 9b, 9c, 9d, as shown in FIG.
9e and 9f are output.

Example 12. In this embodiment, switching is performed by a combination of time and position signal detection, that is, switching is performed when both conditions are satisfied. FIG. 39 shows an overall configuration diagram of a twelfth embodiment of the drive device for the three-phase brushless motor according to the present invention. 8D is the counter value 7a, 7b, 7c
And a position signal 3a, 3b, 3c, a switching signal generating circuit for outputting a switching signal 8a for switching. The switching signal generation circuit 8D will be described below. In this embodiment, the motor rotation signal 5a, the restart pulse 265a, and the position signals 3a, 3b, 3c are input to the switching signal generation circuit 8D. The switching signal 8a is input to the commutation circuit 9.

FIG. 40 shows the switching signal generating circuit 8D of this embodiment.
FIG. In this embodiment, the switching signal generating circuit 8D is composed of a position signal combination discriminating circuit 272 and a timer 270. The timer 270 has the same configuration as that of the tenth embodiment. The position signals 3a, 3b, 3c are input to the position signal combination determination circuit 272, and the position signals 3a, 3b,
When 3c has a predetermined combination, the output becomes high. In this embodiment, when the position signals 3a, 3b and 3c are in a combination of high, low and low, they change to high. The outputs of the position signal combination determination circuit 272 and the timer 270 are A
The AND circuit output 273a, the motor rotation signal 5a, and the restart pulse 265a are input to the ND circuit 273 and are input to the latch circuit 274. The latch circuit 274 is cleared by the motor rotation signal 5a and the restart pulse 265a,
Once the input signal goes high, it is a circuit that holds the output high until it is cleared.

Next, the operation of the switching signal generating circuit 8D of this embodiment will be described with reference to FIG. When the motor rotation signal 5a becomes high, the timer 270 is turned on, and the commutation circuit 9 drives the drive signals 9a, 9b, 9c, 9d according to the combination of the counter values 7a, 7b, 7c according to the relationship shown in FIG.
9e and 9f are output. Then, after a predetermined time t _{0 has} elapsed,
The timer output 270a changes to high. When the timer output 270a is high and the position signals 3a, 3b, 3c are in a combination of high / low / low, the AND circuit output 2
73a changes to high. The latch circuit 274 operates at the first rising edge of the AND circuit output 273a after the motor rotation signal 5a changes to high, and the switching signal 8a is held high. As a result, the commutation circuit 9 outputs drive signals 9a, 9b, 9c, 9d, 9e, 9f according to the combination of the position signals 3a, 3b, 3c as shown in FIG.

Further, the commutation circuit 9 causes the position signals 3a, 3b,
Drive signals 9a, 9b, 9c,
When outputting 9d, 9e, 9f, restart pulse 26
5a is input, the timer 270 and the latch circuit 274 are input.
Are reset and the switching signal 8a changes from high to low. As a result, the commutation circuit 9 causes the counter values 7a, 7
drive signals 9a, 9b, 9c, 9d, 9 using b, 7c.
e, 9f are output. Then, as described above, when the position signals 3a, 3b, 3c become a combination of high / low / low after the predetermined time t ₀ , the switching signal 8a changes from low to high, and the commutation circuit 9 is again the position signals 3a, 3b,
Drive signals 9a, 9b, 9c, 9 using combinations of 3c
It outputs d, 9e and 9f.

Example 13 In the present embodiment, switching is performed by both the fact that the counter has reached a constant value and the fact that the position signal has been detected normally.
FIG. 42 shows an overall configuration diagram of a thirteenth embodiment of a driving apparatus for a three-phase brushless motor according to the present invention. The switching signal generation circuit 8E of this embodiment will be described below. In this embodiment, the position signals 3a, 3b and 3c, the pulse train 7d and the motor rotation signal 5a are used.
And the restart pulse 265a is input to the switching signal generation circuit 8E. The switching signal 8a is input to the commutation circuit 9.

FIG. 43 shows the switching signal generating circuit 8E of this embodiment.
FIG. The switching signal generation circuit 8E of this embodiment is
It is composed of the position signal combination discriminating circuit 272 and the mode switching counter 271 described in the previous embodiment. Next, the operation of the switching signal generating circuit 8E of this embodiment will be described with reference to FIG. When the motor rotation signal 5a becomes high, the mode switching counter 271 starts counting the pulse train 7d, and the commutation circuit 9 uses the combination of the counter values 7a, 7b, 7c according to the relationship shown in FIG.
9b, 9c, 9d, 9e and 9f are output. When the predetermined number of times X is counted, the mode switching counter 271
Output 271a goes high, and the position signal
It becomes a combination of low and low, and the output 2 of the AND circuit 273
73a goes high. The latch circuit 274 operates at the first rising edge of the AND circuit output 273a after the motor rotation signal 5a changes to high, and the switching signal 8a changes from low to high and is held high. Thus, the commutation circuit 9 outputs the drive signals 9a, 9b, 9c, 9d, 9e, 9f by combining the position signals 3a, 3b, 3c.

Further, the commutation circuit 9 uses the position signals 3a, 3b,
Drive signals 9a, 9b, 9c,
When outputting 9d, 9e, 9f, restart pulse 26
When 5a is input, the mode switching counter 271 and the latch circuit 274 are reset, the switching signal 8a changes from high to low, and the commutation circuit 9 receives the counter values 7a, 7b, 7.
The drive signal is output using the combination of c. The mode switching counter 271 counts the pulse train 7d a predetermined number of times X times, and when the position signal becomes a predetermined combination of high / low / low, the switching signal 8a changes from low to high, and again,
The drive signals 9a, 9b, 9c, 9d, 9e, 9f are output using the combination of the position signals 3a, 3b, 3c.

Example 14 In the present embodiment, the switching is performed when the set time has elapsed and the drive signal is normal at the same time. FIG. 45 shows an overall configuration diagram of a fourteenth embodiment brushless motor driving apparatus according to the present invention. The switching signal generation circuit 8F of this embodiment will be described below. In this embodiment, the drive signals 9a, 9b, 9c, 9
d, 9e, 9f, motor rotation signal 5a, and restart pulse 2
65a is input to the switching signal generation circuit 8F.

FIG. 46 shows the switching signal generating circuit 8F of this embodiment.
FIG. The switching signal generation circuit 8F of this embodiment is
The drive signal combination determination circuit 275 and the timer 27 described above
It is composed of 0s. Drive signal combination discrimination circuit 2
75 includes drive signals 9a, 9b, 9c, 9d, 9e, 9f.
Is entered. The drive signal combination determination circuit 275 is configured so that the output 275a becomes high when the drive signals 9a, 9b, 9c, 9d, 9e, 9f are in a predetermined combination. In this embodiment, the drive signals 9a, 9b, 9c, 9d, 9e,
The output 275a goes high when 9f is a combination of low-high-high-low-high-low. The outputs of the drive signal combination determination circuit 275 and the timer 270 are AND circuits 273.
AND circuit output 273a, motor rotation signal 5a, and restart pulse 265a are input to the latch circuit 274 described in the previous embodiment.

FIG. 47 shows the switching signal generating circuit 8 of this embodiment.
It is explanatory drawing of operation | movement of F. When the motor rotation signal 5a becomes high, the timer 270 is turned on and the commutation circuit 9 outputs the drive signal using the combination of the counter values. Then, after the elapse of the predetermined time t ₀ , the timer output 270a changes to high, and the drive signals 9a, 9b, 9c, 9d, 9e, 9f.
Becomes a combination of low-high-high-low-high-low, the output 273a of the AND circuit 273 changes to high. After that, the same changes as described in the previous embodiment,
The commutation circuit 9 again uses the combination of the position signals 3a, 3b, 3c to drive signals 9a, 9b, 9c, 9d, 9e, 9
Output f. Further, as shown in FIG. 47, the operation when the restart pulse 265a is input is also the same as that described in the previous embodiment, and the commutation circuit 9 again returns to the position signal 3a, t ₀ after t ₀ . The drive signals 9a, 9b, 9c, 9d, 9e and 9f are output using the combination of 3b and 3c.

Example 15. In the present embodiment, the switching is performed under the condition that both the driving signal becomes normal after the counter counts a constant value. FIG. 48 shows a first embodiment of a driving device for a three-phase brushless motor according to the present invention.
5 shows an overall configuration diagram of No. 5. The switching signal generation circuit 8G of this embodiment will be described below. In this embodiment, the drive signals 9a and 9
b, 9c, 9d, 9e, 9f, the pulse train 7d, the motor rotation signal 5a, and the restart pulse 265a are input to the switching signal generation circuit 8G.

FIG. 49 shows the switching signal generating circuit 8G of this embodiment.
FIG. The switching signal generation circuit 8G of this embodiment is
Drive signal combination determination circuit 275 and mode switching counter 2
It is composed of 71. FIG. 50 is a diagram for explaining the operation of the switching signal generating circuit 8G of this embodiment. The operation at the time of startup and at the time of restart is the same as the operation described in the above-described embodiments, and thus the description thereof will be omitted.

Example 16. In the present embodiment, an example in which switching is performed by speed detection will be described. FIG. 51 shows an overall configuration diagram of a sixteenth embodiment of a driving apparatus for a three-phase brushless motor according to the present invention. The switching signal generation circuit 8H of this embodiment will be described below. In this embodiment, the logic pulse 201 output from the waveform shaping circuit 3 in the rotor position signal generation circuit 4, the motor rotation signal 5a, and the restart pulse 265a are input to the switching signal generation circuit 8H.

FIG. 52 shows the switching signal generating circuit 8H of this embodiment.
FIG. The switching signal generation circuit 8H of this embodiment is
Speed signal generation circuit 277 and reference speed generation circuit 276
And a comparison circuit 278. The logic pulse 201 and CLK are input to the speed signal generation circuit 277. As described in the first or seventh embodiment, since the logic pulse 201 is a signal obtained at a certain time interval, it is possible to detect the rotation speed of the brushless motor from the logic pulse 201. FIG. 53 shows the speed signal 277.
The timing chart of the generation method of a is shown. The speed signal generation circuit 277 outputs CL when the motor rotation signal 5a is high.
It counts up at the timing of the edge of K and is cleared at the timing of the rising edge of the logic pulse input from the waveform shaping circuit 3, and the value of the arrow in the figure indicates the speed signal 27.
It is output as 7a. The reference speed generation circuit 276 changes the reference speed signal 2 for switching from the starting mode to the steady rotation mode.
76a is output. The comparison circuit 278 receives the speed signal 277a at the timing of the rising edge of the logic pulse.
The reference speed signal 276a is compared with the reference speed signal 276a by, for example, the voltage level or the number of bits, and the speed signal 277a is compared with the reference speed signal 27.
When it reaches 6a, the switching signal 8a is output.

Next, the operation of the switching signal generating circuit 8H of this embodiment will be described with reference to FIG. When the motor rotation signal 5a becomes high at startup, the comparison circuit 278 starts comparing the speed signal 277a with the reference speed signal 276a. When the speed signal 277a reaches the reference speed signal 276a, the switching signal 8a output from the comparison circuit 278 changes to high. When the restart pulse 265a is input, the comparison circuit 278 is reset and the switching signal 8a changes from high to low. Then, when the speed signal 277a reaches the reference speed signal 276a, the switching signal 8a changes from low to high again.

Example 17 In this embodiment, the switching is performed under the condition that the time setting, the counter value and the normal detection of the position signal are simultaneously satisfied. FIG. 55 shows a first embodiment of a drive unit for a three-phase brushless motor according to the present invention.
7 shows an overall configuration diagram of 7. The switching signal generating circuit 8I of this embodiment will be described below. In this embodiment, the counter values 7a, 7
b, 7c, position signals 3a, 3b, 3c, motor rotation signal 5a, and restart pulse 265a are input to the switching signal generation circuit 8I.

FIG. 56 shows the switching signal generating circuit 8I of this embodiment.
FIG. The switching signal generation circuit 8I of this embodiment is
The position signal counter value determination circuit 280 and the timer 270 are configured. FIG. 57 is a diagram for explaining the operation of the switching signal generating circuit 8I of this embodiment. The operation based on this figure is the same as that already described in the above embodiment, and therefore its explanation is omitted.

Example 18. This embodiment is an example in which switching is performed by satisfying both speed detection and normal detection of a position signal. FIG. 58 shows an overall configuration diagram of a drive system for a three-phase brushless motor according to the eighteenth embodiment of the present invention. Less than,
The switching signal generation circuit 8J of this embodiment will be described.

FIG. 59 shows a switching signal generating circuit 8J of this embodiment.
FIG. The switching signal generation circuit 8J of this embodiment is
A reference speed generation circuit 276, a speed signal generation circuit 277,
It is composed of a comparison circuit 278 and a position signal combination determination circuit 272. Next, FIG. 60 is a diagram for explaining the operation of the switching signal generating circuit 8J of the present embodiment. Since the operation based on this figure is the same as that already described in the above embodiment, the description is omitted.

Example 19. This embodiment is an example in which switching is performed by a logical product of speed detection and normal detection of a drive signal.
FIG. 61 shows an overall configuration diagram of a nineteenth embodiment of a drive device for a three-phase brushless motor according to the present invention. The switching signal generating circuit 8K of this embodiment will be described below.

FIG. 62 shows the switching signal generating circuit 8K of this embodiment.
FIG. The switching signal generation circuit 8K of this embodiment is
Reference speed generation circuit 276 and speed signal generation circuit 277
, Comparison circuit 278, and drive signal combination determination circuit 275
It consists of FIG. 63 is a diagram for explaining the operation of the switching signal generating circuit 8K of this embodiment. The operation based on this figure is the same as that of the above-mentioned embodiment, and therefore its explanation is omitted.

Example 20. The present embodiment is an example in which switching is performed by three logical products of speed detection, normal position signal detection, and counter value. FIG. 64 shows an overall configuration diagram of a twentieth embodiment of the driving apparatus for the three-phase brushless motor according to the present invention. The switching signal generation circuit 8L of this embodiment will be described below.

FIG. 65 shows the switching signal generating circuit 8L of this embodiment.
FIG. The switching signal generation circuit 8L of this embodiment is
Reference speed generation circuit 276 and speed signal generation circuit 277
And a comparison circuit 278 and a position signal counter value determination circuit 2
It consists of 80. FIG. 66 is a diagram for explaining the operation of the switching signal generating circuit 8L of this embodiment. The operation based on this figure is the same as that of the above-mentioned embodiment, and therefore its explanation is omitted.

Example 21. In the present embodiment, an example will be described in which the steady rotation detection circuit at the time of restart is not provided independently, and the forced start mode is set by the pseudo pulse from the pulse generation circuit or the like at the time of restart. FIG. 67 shows an overall configuration diagram of a twenty-first embodiment of a three-phase brushless motor drive device according to the present invention. In this embodiment, the position signals 3a, 3b, 3c, the counter values 7a, 7b, 7c and the pseudo pulse 6a output from the pulse generation circuit 6 are input to the commutation circuit 9. The commutation circuit 9 is
It is configured to be reset by the pseudo pulse 6a and shift to the start-up mode.

In the above structure, during steady rotation,
When the rotor stops due to some load, the pulse generation circuit 6 outputs the pseudo pulse 6a, and the pseudo pulse 6a is input to the commutation circuit 9. The commutation circuit 9 is reset by the pseudo pulse 6a and shifts to the start-up mode. Therefore, the counter values 7a, 7
drive signals 9a, 9b, 9c, depending on the combination of b and 7c,
9d, 9e and 9f are output.

Example 22. In the present embodiment, one position detecting element independent of the winding voltage detection is used, and by combining this signal and the position detection by the winding voltage, it is possible to surely obtain the drive signal in the correct direction. did. FIG. 68 shows an overall configuration diagram of a twenty-second embodiment of a three-phase brushless motor drive device according to the present invention. A position detector 300 detects the position of the rotor and outputs a pulsed position signal 300a.
Reference numeral 01 is a hold circuit that holds the output from the rising edge of the input signal. In FIG. 68, the position signal 300
a is input to the hold circuit 301. In this embodiment,
The position signal 300a corresponds to the position signal 3b as shown in FIG.
And the electrical angle is shifted by π / 6. Further, each energization stable point of the brushless motor is at the position of the broken line in the figure, and the position signal 300
It coincides with the positions of the rising edge and the falling edge of a.

The hold circuit 301 in FIG. 68 holds the value of the position signal 300a immediately after the motor rotation signal 5a goes high until the motor rotation signal 5a goes low. For example, if the position signal 300a is high immediately after the motor rotation signal 5a goes high, the hold circuit output 301a is held high until the motor rotation signal 5a goes low. The output 301a of the hold circuit 301 is the commutation circuit 9
And the pulse selection circuit 2 in the counter circuit 7 shown in FIG.
56 is input. The commutation circuit 9 is configured to output drive signals 9a, 9b, 9c, 9d, 9e, 9f by referring to the hold circuit output value 301a and the counter values 7a, 7b, 7c. FIG. 70 shows an example of the logical relationship between the hold circuit output 301a, the counter values 7a, 7b and 7c and the drive signals 9a, 9b, 9c, 9d, 9e and 9f in this embodiment.

FIG. 71 shows a counter circuit 7 in this embodiment.
Shows the configuration of. Rising edge detection circuit 250, 25
2, 254, falling edge detection circuits 251, 25
The 3, 255 and hexadecimal counters 257 are the same as in the above embodiment. The pulse selection circuit 256 has position signals 3a, 3
b, 3c rising edge pulses 250a, 252
a, 254a and falling edge pulses 251a, 25
3a, 255a, pseudo pulse 6a, and hold circuit output 3
01a is input. The pulse selection circuit 256 uses the current counter values 7a, 7b, 7c and the hold circuit output 301.
With reference to a, the edge pulse or the pseudo pulse 6a of the theoretical position signal to be detected next at the time of forward rotation is output. Counter values 7a and 7 in this embodiment
b, 7c, the hold circuit output 301a, and theoretical edge pulses 250a, 252 to be detected next at the time of forward rotation.
72 shows an example of the relationship between a, 254a, 251a, 253a, and 255a. From FIG. 72, for example, the counter value 7
When a, 7b, and 7c are low / low / low and the hold circuit output 301a is high, the edge pulse 253a or the pseudo pulse 6a is output, and another edge pulse 25
It does not output even if 0a is input.

Next, the operation of the brushless motor in this embodiment will be described. First, a case where the hold circuit output 301a is high immediately after the motor rotation signal 5a becomes high will be described with reference to FIG. Since the hold circuit output 301a is high, the commutation circuit 9 outputs the drive signals 9a, 9b, 9c, 9d, 9e, and 9f to high / low from FIG.
Set to high / low / low / high. Then, the rotor of the brushless motor rotates in the forward direction, and the energization is sequentially switched to start.

A case where the hold circuit output 301a is low immediately after the motor rotation signal 5a becomes high will be described with reference to FIG. Since the hold circuit output 301a is low, the commutation circuit 9 in FIG.
b, 9c, 9d, 9e and 9f are set to high-high-low-low-high-low. Then, the rotor of the brushless motor rotates in the forward direction, and the energization is sequentially switched to start.

Example 23. The present embodiment is an example in which driving at the time of startup or restart is further ensured. FIG. 75 shows the overall configuration of a twenty-third embodiment of the drive unit for a three-phase brushless motor according to the present invention. An edge detection circuit 302 detects a rising edge or a falling edge of the input signal.

The commutation circuit 9 conducts electricity immediately after the motor rotation signal 5a becomes high based on the hold circuit output 301a. V when the hold circuit output 301a is high
The -W phase is energized, and the W-V phase is energized when low. The first commutation is the output pulse 30 of the edge detection circuit 302.
Commutation is performed based on 2a and the hold circuit output 301a. When the hold circuit output 301a is high, the UW phase is energized, and when it is low, the WU phase is energized. The commutation thereafter is configured to output the drive signals 9a, 9b, 9c, 9d, 9e, 9f with reference to the position signals 3a, 3b, 3c. Position signals 3a, 3b, 3c and drive signal 9
An example of the logical relationship of a, 9b, 9c, 9d, 9e and 9f is shown in FIG.
Same as 2.

Next, the operation of the brushless motor in this embodiment will be described. First, a case where the hold circuit output 301a is high immediately after the motor rotation signal 5a becomes high will be described with reference to FIG. Since the hold circuit output 301a is high, the VW phase should be energized as shown in FIG.
The drive signals 9a, 9b, 9c, 9d, 9e and 9f from 1 are set to high-low-high-low-low-high. Then, when the rotor rotates in the normal direction and the output pulse 302a of the edge detection circuit 302 is detected, the first commutation is performed. Since the hold circuit output 301a is high, U-
Drive signals 9a, 9b from FIG. 21 to energize the W phase,
9c, 9d, 9e and 9f are set to low-high-high-low-low-high. Then, for the subsequent commutation, the energization is sequentially switched by referring to the position signals 3a, 3b, 3c, and the rotor is normally rotated.

A case where the hold circuit output 301a is low immediately after the motor rotation signal 5a becomes high will be described with reference to FIG. Since the hold circuit output 301a is low, the drive signals 9a, 9b, 9c, 9d, 9e, 9f are set to high-high-low-low-high-low from FIG. 21 so as to energize the WV phase. Then, the rotor rotates in the normal direction, and the output pulse 302a of the edge detection circuit 302 is output.
When is detected, the first commutation is performed. Since the hold circuit output 301a is low, the drive signals 9a, 9b, 9c, 9d from FIG.
9e and 9f are set to high-high-low-high-low-low. Then, the commutation thereafter is performed by the position signals 3a, 3
The rotor is normally rotated by sequentially switching energization with reference to b and 3c.

In the present specification, claims 1 to 19 are
However, it is clear that a sufficient effect can be obtained by combining these embodiments.

Example 24. FIG. 78 is a block diagram showing the overall structure of the brushless motor drive circuit of this embodiment. 78, the same components as those in FIG. 1 are indicated by the same numbers. In FIG. 78, 406 is a starting circuit, 409 is a speed error detection circuit that measures the cycle of the actually measured speed signal 3d with a counter and outputs a cycle error that is the difference between the command value and the measured value as a speed error signal 409a. Is. Reference numeral 410 is a speed error compensation filter that outputs a current command value 410a to the current supply circuit 411 so that the speed error signal 409a becomes zero. Current supply circuit 411
Is the resistor 10, the bridge circuit 11, the buffer amplifier 212, the resistor 213, and the drive transistor 214 shown in FIG.
And supplies a predetermined drive current to the armature windings 12, 13 and 14 based on the drive signals 9a to 9f.

The configuration and operation of the terminal potential correction circuit 1, the comparison circuit 2 and the waveform shaping circuit 3 which form the rotor position signal detection circuit 4 which is an important means in the present invention are as follows.
It has already been described in Example 1. FIG. 79 is a diagram showing signal waveforms of respective parts of the terminal potential correction circuit 1 in the steady rotation state. The specific operation of the terminal potential correction circuit 1 is also described in the first embodiment, and the correction operation is described using equations (1) to (3).

The spike-shaped voltage fluctuation that occurs when switching from the energized state to the non-energized state causes erroneous detection of the rotor position and noise, so the waveform shaping circuit 3 is required. This example is shown in FIG. 17 in Example 7. Figure 80
Another example of the configuration of the waveform shaping circuit 3 is shown in FIG. In the figure, 1
80 is a latch circuit, 181 to 186 are D flip-flops, 187 to 189 are EOR circuits, and 190 is an OR circuit. Reference numeral 421 is a mask signal generation circuit and 422 is a timer. 81 shows the terminal potential waveform in the steady rotation state and the signal waveform of each part of the waveform shaping circuit, and FIG. 82 is an enlarged view of time T0 to T1 in FIG.

The specific operation of the waveform shaping circuit of this embodiment will be described with reference to the drawings. The input signal to the waveform shaping circuit is the logical signals 2a, 2b, 2 output from the comparison circuit 2.
c. Since the logic signals 2a, 2b, and 2c are obtained by comparing the corrected terminal potentials, chattering occurs as shown in FIG. Logic signal 2a,
2b and 2c are first input to the latch circuit 180.
The latch circuit 180 is a circuit that performs a latch operation according to the state of the enable terminal 180a. In the initial state, the mask signal 421a output from the mask signal generation circuit 421 is at high level, and the logic signals 2a and 2
b and 2c are the D flip-flops 181, 1 respectively.
83 and 185. D flip-flop 181
˜186 and EOR circuits 187 to 189 constitute a double-edge differentiating circuit, and the EOR circuit 1 is arranged at the rising and falling edges of the logic signals 2a, 2b, 2c.
87 to 189 output differential pulses 198, 199 and 200.

At time T2, the corrected terminal potential 1
When the potential levels of a and 1c match and the polarity of 2a changes, an edge is detected by the both-edge differentiating circuit, and a differential pulse 198b is generated. The output signals of the EOR circuits 187 to 189 are combined by the OR circuit 190 to obtain the logical pulse signal 3
d, the mask signal generating circuit 421 and the timer 42
Entered in 2. The mask signal generation circuit 421 sets the mask signal 421a to the low level by using the rising edge of the logic pulse signal 3d as a trigger. The timer 422 is initialized at the rising edge of the logic pulse signal 3d, and the timer value 422a becomes 0. After that, the timer 422
The count-up operation is performed in synchronization with the input clock. Since the enable terminal 180a becomes low level, the latch circuit 180 latches the logic signals 2a, 2b, 2c. After that, the mask signal generation circuit 421 monitors the timer value 422a of the timer 422, and the timer value 422a
When becomes a predetermined value, the mask signal 421a is set to the high level. The latch circuit 180 has an enable terminal 180a
Becomes high level, so release the latch.

D flip-flops 182, 184, 18
The output signal of 6 is the waveform-shaped rotor position signals 3a, 3
b, 3c, which are input to the commutation circuit 9 in the next stage, and the commutation operation is performed. When the commutation operation is performed, the driving transistor is switched, so that a spike-like voltage fluctuation occurs in the U-phase terminal potential waveform, and as a result, spike-like noise 2d is generated in 2b at an undesired position. However, when the spike noise 2d is generated,
The data input to the latch circuit is the mask signal generation circuit 421.
It is disabled by the mask signal 421a output from. Therefore, the spike noise 2d is masked by the latch circuit 180, and the spike shaped noise is not generated in the waveform-shaped rotor position signals 3a, 3b, 3c. In this way, stable rotor position signals 3a, 3
b and 3c are obtained, the armature winding is applied and driven based on this rotor position signal, and the rotor rotates.

In this embodiment, the example applied to the three-phase brushless motor has been described, but it is obvious that the present invention can be applied to not only three-phase brushless motors but also multiple-phase brushless motors.

Example 25. In the present embodiment, the time T3 during which the mask signal 421a is kept at the low level described in the first embodiment is changed in proportion to the command rotation speed when the command rotation speed for the motor is changed. I chose The overall configuration of the brushless motor drive circuit of the present embodiment is the same as that of the twenty-fourth embodiment. However, as described below, the command rotation speed (CLK) to the timer is changed.

Operations of the mask signal generation circuit 421 and the timer 422 of this embodiment will be described with reference to FIGS. 83, 84 and 85. As described in Embodiment 24, when the rising edge or the falling edge of the logic signals 2a, 2b, 2c is detected and the logic pulse signal 3d is generated,
The mask signal generation circuit 421 sets the mask signal 421a to the low level by using the rising edge of the logic pulse signal 3d as a trigger. The timer 422 is a logical pulse signal 3d
The timer value 422a is initialized to 0 at the rising edge of. After that, the timer 422 counts up in synchronization with the rising edge of the input clock. After that, the mask signal generation circuit 421 causes the timer 42 to
2 timer value 422a is monitored, and timer value 422a is N
When (N = 10 is set in FIG. 83), the mask signal 4
21a is set to a high level. Assuming that the clock cycle is T4, the mask signal 421a maintains a low level for T4 × 10.

Next, from the state of FIG. 83, the command rotation speed is 2
The case where the number is doubled will be described. As shown in FIG. 84, the cycle of CLK (input from outside the brushless motor drive circuit) is set to T4 / 2. As a result, the time during which the mask signal 421a maintains the low level is T
It becomes 4 × 5. Alternatively, as shown in FIG. 85, the period of the clock input to the timer remains T4 and the value of N is 5
Change to This causes the mask signal 421a to go low.
The time during which the level is maintained is T4 × 5 as in the case where the clock cycle is changed. In this way, the time during which the mask signal maintains the low level is changed based on the command rotation speed.

Example 26. In this embodiment, a brushless motor that is not affected by the load at the time of start and is started in a short time, and is stably restarted in a short time even when the rotation is abnormal due to some cause during operation and restart is required. The configuration and operation of the drive circuit for use in a vehicle will be described. The main purpose is Example 8
However, as described above, in the present embodiment, the operation at the time of starting or restarting will be mainly described. The overall structure of the brushless motor drive circuit of this embodiment is the same as that of FIG. Here, the configuration and operation of the starting circuit, which is an important means for realizing the present invention, will be described below. The new components in this embodiment are the pseudo pulse generation circuit 431 and the restart pulse generation circuit 432. The other components are the same as those shown in FIG. 23 of the eighth embodiment.

The motor rotation signal 5a shown in FIG. 78 is a signal input from the outside of the brushless motor drive circuit, and represents rotation when enabled and stop when disabled. In this embodiment, enable is set to high level and disable is set to low level.

FIG. 86 shows a specific configuration example of the starting circuit 406. The rotor position signals 3a, 3b, 3c are respectively
The rising edge detection circuits 250, 252, 254, the falling edge detection circuits 251, 253, 255, and the steady rotation detection circuit 265 are input to the rising edge detection circuits 250, 252, 254 and the falling edge detection circuits 251, 253, 255. Output rising and falling edge pulses 250a to 255a, respectively. These detected edge pulses are output to the pulse selection circuit 256.
And the selection pulse 256a output from the pulse selection circuit 256 is input to the pseudo pulse generation circuit 431. The pulse train 431 a output from the pseudo pulse generation circuit 431 is input to the hexadecimal counter 257. An example of the logical relationship between the number of pulses input to the hexadecimal counter 257 and the output value is the same as that shown in FIG. In the figure, when the number of input pulses is 6 or more, the counter values 7a, 7b, 7c are
Count from low-low-low again. The counter value output from the hexadecimal counter 257 is the pulse selection circuit 2
56, the steady rotation detection circuit 265, and the commutation circuit 9 shown in FIG. The abnormal rotation signal 265b output from the steady rotation detection circuit 265 is the restart pulse generation circuit 4
32 is input. Further, the motor rotation signal 5a is input to the restart pulse generation circuit. The restart pulse 7e output from the restart pulse generation circuit 432 is input to the commutation circuit 9 shown in FIG.

The pulse selection circuit 256 receives the input edge pulse 2 when the rotor is rotating normally according to the logic of FIG.
50a to 255a are directly output as a pulse train.
That is, the type of the input edge pulse and the counter value 7
When the relationship of a, 7b, and 7c satisfies the relationship of FIG. 25, the input edge pulse is output as it is, and otherwise the input edge pulse is masked. Therefore, since the relationship between the counter values 7a, 7b and 7c and the edge pulse is different in the reverse rotation from that in the normal rotation, the input edge pulse is masked. The pseudo pulse generation circuit 431 receives the selection pulse train 256a from the pulse selection circuit 256 within a predetermined time.
When is sequentially input, the pulse train is output as it is,
It is a circuit that generates a pseudo pulse when a pulse train is not input for a predetermined time. FIG. 87 shows the pseudo pulse generation circuit 431.
88 shows a specific configuration example of the pseudo pulse generation circuit 4 in FIG.
An example of a timing chart showing the operation of 31 is shown.

In FIG. 87, 433 is a counter and 43
4 is a gate circuit, 435 is a rising edge detection circuit,
Reference numeral 436 is a delay circuit, and 437 is an OR circuit. The counter 433 is initialized by the pulse train 431a and counts up in synchronization with the input clock. Gate circuit 43
Reference numeral 4 decodes the counter value 433a, and outputs a low level signal when the decoded value is smaller than the set value, and outputs a high level signal when the decoded value is larger than the set value.
Therefore, the pulse selection circuit 256 outputs the selection pulse 25
When 6a is not input for a predetermined time, the output signal 434a of the gate circuit becomes high level, the rising edge is detected by the rising edge detection circuit 435, and the detected edge pulse is delayed by the delay circuit 436, which is shown in FIG. The pseudo pulse 436b is output.

The steady rotation detection circuit 265 is a circuit for monitoring whether the rotor described in the ninth embodiment is normally rotating normally. The restart pulse generation circuit 432 outputs the abnormal rotation signal 256b after the startup or until a predetermined time has elapsed after the restart.
Is a circuit for detecting a rising edge of the rotation abnormality signal after a predetermined time has elapsed and outputting it as a restart pulse. FIG. 89 shows a configuration example of the restart pulse generation circuit 432. In the figure, 440 and 444 are rising edge detection circuits, 441 and 446 are OR circuits, and 442.
Is a counter, 443 is a gate circuit, and 445 is an AND circuit. The counter 442 is initialized by the rising edge of the motor rotation signal 5a or the restart pulse 7e and counts up in synchronization with the output of the OR circuit 446. The gate circuit 443 decodes the counter value 442a, and when the decoded value is smaller than the set value,
A high level signal is output when the level signal is larger than the set value. Therefore, the rotation abnormality signal 265b is masked until a predetermined time elapses after activation or after the restart, and after the predetermined time has elapsed, the rising edge of the rotation abnormality signal is output as a restart pulse.

The starting operation of the brushless motor in this embodiment will be described. Hereinafter, the low level may be described as L and the high level may be described as H. Motor rotation signal 5
Immediately after a becomes high level, the counter values 7a, 7
Since b and 7c become LLL, the drive signal 9b is obtained from FIG.
Goes to L and 9f goes to H, and the VW phase is energized from FIG. At this time, the rotor of the brushless motor may rotate normally to change the rotor position signal, may rotate in the reverse direction to change the rotor position signal, or may stop at the stable energization point and the position signal may not change. .

First, the case where the rotor rotates normally will be described. In this case, the signal waveform example of each part shown in FIG. As described in the corresponding portion of the eighth embodiment, the hexadecimal counter 257 counts only when the edge pulse 253a is detected or when the pseudo pulse 436b is generated by the pseudo pulse generation circuit. When the rotor rotates in the forward direction, the terminal potentials U, V, W change due to the back electromotive force generated in the armature winding, and the rotor position signals 3a, 3b, 3
c becomes HLL, and edge pulse 2 as shown in FIG.
53a is detected. Therefore, the hexadecimal counter 257
Counts up, and the counter values 7a, 7b, 7c are H
7 and 27, the commutation circuit 9 sets the drive signals 9a to 9f to LHHLLH so that the UW phase is energized. Then, the pseudo pulse generation circuit 431 continues to output the waveform shown in 7d of FIG. 28 as its output 431a,
After that, counter values 7a, 7b, 7c until steady rotation
27, the energized phases are sequentially switched in the relationship shown in FIG. 27 to start the brushless motor.

Next, the case where the rotor is reversed will be described. Also in this case, the signal waveform example of each part shown in FIG. As described in the eighth embodiment, when the rotor rotates in the reverse direction, the rotor position signal 3a changes, and the edge pulse 251a shown in FIG. However, it is masked by the pulse selection circuit 256 because of the counter value. If the edge pulse 253a cannot be detected within the predetermined time t1 set by the gate circuit 434 in the pseudo pulse generation circuit 431, as shown in FIG. 431a is output. The hexadecimal counter 257 uses the pseudo pulse 431.
The counter value is incremented by a and the counter values 7a, 7b,
7c changes to HLL. Then, the commutation circuit 9 sets the drive signals 9a to 9f to LHHLLH so as to energize the U-W phases according to the counter values 7a, 7b, and 7c. As a result, the rotor rotates in the normal direction, and thereafter the brushless motor is started by sequentially switching the energized phases in the relationship shown in FIG.

Next, the case where the rotor does not move and the rotor position signal does not change will be described. Similar to the case of reverse rotation, since the edge pulse 253a cannot be detected within the predetermined time t1, the pseudo pulse generation circuit 431 outputs a pseudo pulse (equivalent to 6a). And 6 as in reverse
The advance counter 257 counts the pseudo pulse, and the commutation circuit switches the energized phase to the UW phase, and thereafter, according to the combination of the counter values 7a, 7b, and 7c until the steady rotation is performed.
The brushless motor is started by sequentially switching the energized phases according to the relationship shown in FIG.

An example in which the rotor is stopped due to some load during steady rotation in such a configuration will be described with reference to FIG. In FIG. 90, it is assumed that the rotor stops after (D). In this case, the pseudo pulse 436b is output from the delay circuit 436 in the pseudo pulse generating circuit 431 after the time t1 set by the gate circuit 434 in the pseudo pulse generating circuit 431 has elapsed after detecting the pulse 431c. Then, the pseudo pulse 436b is output as a pulse of the pulse train 431a output from the pseudo pulse generation circuit 431, and the counter values 7a, 7b, and 7c are from LHL to L.
Change to LH. During the steady rotation, the drive signal 9a is generated by the combination of the rotor position signals 3a, 3b and 3c as described above.
Since 9f are output, the counter values 7a, 7b, 7
Even if c changes, the energized phase is not switched. Therefore, the counter values 7a, 7b, 7c and the rotor position signal 3
The relations of a, 3b, and 3c no longer satisfy the relation of FIG. 31, and the abnormal rotation signal 265b is output from the steady rotation detection circuit 265.
Becomes high level.

At this time, if a predetermined time has elapsed after the start-up and restart, the rising edge of the rotation abnormality signal is detected by the restart-pulse generating circuit 432 and output as the restart pulse 7e. The restart pulse is input to the commutation circuit 9, and the commutation circuit shifts to the start mode. Since the commutation circuit in the start-up mode outputs the drive signals 9a to 9f according to the combination of the counter values 7a, 7b, 7c, FIG.
From FIG. 27, the drive signals 9a to 9f become HHLLHL and W
-The V phase is energized. When the W-V phases are energized, the rotor rotates in the normal direction, and the rotor position signals 3a, 3b, 3c become L.
When it changes to LH, the relationship between the counter values 7a, 7b, 7c and the rotor position signals 3a, 3b, 3c satisfies the relationship shown in FIG. 31, so that the rotation abnormality signal 265b becomes low level. After that, as described with reference to FIGS. 28 and 29, the energized phases are sequentially switched according to the combination of the counter values 7a, 7b, and 7c in accordance with the combination of the counter values 7a, 7b, and 7c to start the brushless motor until the steady rotation is performed.

Example 27. In the present embodiment, the configuration and operation of a brushless motor drive circuit provided with a switching means for switching from the startup mode to the steady rotation mode will be described. FIG. 91 shows a specific configuration example of the starting circuit 406B provided with the switching means. Rising edge detection circuit,
The falling edge detection circuit, the pulse selection circuit, the pseudo pulse generation circuit, the hexadecimal counter, the steady rotation detection circuit, and the restart pulse generation circuit are the same as those in the twenty-sixth embodiment. The new component 450 is the drive signal 9 in the commutation circuit 9.
When outputting a to 9f, counter values 7a, 7b, 7c
And a rotor position signal 3a, 3b, 3c, a switching signal generating circuit for outputting a switching signal 450a for switching. The commutation circuit 9 of the present embodiment refers to the counter values 7a, 7b, 7c when the switching signal 450a is at the low level, and switches the switching signal 45.
When 0a is high level, rotor position signals 3a, 3
See b, 3c. Hereinafter, the switching signal generation circuit 45
0 will be described.

In this embodiment, the motor rotation signal 5a and the restart pulse 432a are input to the switching signal generation circuit 450. The switching signal 450a is input to the commutation circuit 9. FIG. 92 shows a specific configuration example of the switching signal generation circuit 450. In the figure, 451 is a rising edge detection circuit, 452 and 455 are OR circuits, 453 is a counter, and 454 is a gate circuit. FIG. 93 is an example of signal waveforms of respective parts showing the operation of the switching signal generating circuit 450. The counter 453 is initialized by the rising edge of the motor rotation signal 5a or the restart pulse 432a and counts up in synchronization with the output 455a of the OR circuit 455. The gate circuit 454 has a counter value 453a.
When the decoded value is smaller than the set value, a low level signal is output, and when the decoded value is larger than the set value, a high level signal is output. Therefore, the switching signal 450a is at the low level until a predetermined time has elapsed after the activation or the restart, and thereafter it is at the high level. The switching signal 450a is input to the commutation circuit 9, and the commutation circuit 9 switches the reference means according to the switching signal 450a.

Example 28. In the present embodiment, a configuration of a brushless motor drive circuit having a speed error compensation filter having an improved low-frequency gain characteristic as compared with a conventional speed error compensation filter will be described. The overall configuration of the brushless motor drive circuit according to the present embodiment is the same as that shown in FIG. 1 or FIG. The structure of the velocity error compensation filter, which is an important means for realizing the present invention, will be described below.

FIG. 94 is a transmission block diagram in the case where the speed error compensating filter is constituted by the analog filter.
In the figure, 460 is a proportional / integral (PI) filter, 4
Reference numeral 61 is a first-order lag filter, 462 is a gain element or coefficient multiplier, 463 is an adder, and 464 is a first-order lag filter. A speed error signal 409a output from the speed error detection circuit 409 is input to the input terminal X of the speed error compensation filter.
Is entered. The filter output output from the output terminal Y is given to the current supply circuit 411 as a current command value 410a for the armature winding. The difference from the filter configuration of FIG. 123 shown in the prior art is that the input speed error signal 4
09a via the new first-order lag filter 461 to P
This is a point configured to add to the output of the I filter 460. At this time, the transfer function G of the velocity error compensation filter
_C (s) becomes like Formula (6).

In FIG. 95, K _P = 1 and T _I = 1 / (2π ×
10), _Kw = 1, T _A = 1 / (2π × 5), T _L = 1
It is a simulation result of the open loop characteristic of the speed error compensation filter when / (2π × 60). Further, in the conventional filter configuration, K _P = 1 and T _I = 1 / (2
The broken line in FIG. 95 shows the simulation result when π × 10) and T _L = 1 / (2π × 60). The filter configuration proposed by the present invention improves the low-frequency gain characteristic.

FIG. 94 shows an example in which the filter is composed of an analog filter, but it is of course possible to form it with a digital filter. 96 is a digital
FIG. 7 is a transmission block diagram in the case where a velocity error compensation filter is configured by a filter. In the figure, 470 to 472 are delay elements that delay the signal by one sampling time, and 473 to 47.
Reference numeral 9 is a gain element, and 480 to 483 are adders. Delay element 471, gain elements 476, 477, adder 48
The PI filter 484 is composed of 1 and 482, and the delay element 4
70, the gain elements 473 to 475, and the adder 480 configure a first-order lag filter 485, and the delay element 472, the gain elements 478 and 479, and the adder 483 configure a first-order lag filter 486. At this time, the transfer function G _C (z) of the speed error compensating filter becomes as shown in Expression (7).

Example 29. In this embodiment, another embodiment of the speed error compensation filter in which the low-pass gain characteristic is improved as compared with the conventional speed error compensation filter will be described.

FIG. 97 is a transmission block diagram in the case where the speed error compensating filter is composed of the analog filter.
In the figure, the same members as in Example 28 are designated by the same reference numerals. The difference from the speed error compensation filter configuration shown in the prior art is that the output of the new first-order lag filter 461 that receives the speed error signal 409a as input is added to the series circuit output of the PI filter and the first-order lag filter. This is the point of composition. At this time, the transfer function G _C of the velocity error compensation filter
(S) becomes like the formula (8).

In FIG. 98, K _P = 1 and T _I = 1 / (2π ×
10), _Kw = 1, T _A = 1 / (2π × 5), T _L = 1
It is a simulation result of the open loop characteristic of the speed error compensation filter when / (2π × 60). Further, in the conventional filter configuration, K _P = 1 and T _I = 1 / (2
The results of simulation when π × 10) and T _L = 1 / (2π × 60) are shown by the broken lines in FIG. The filter configuration proposed by the present invention improves the low-frequency gain characteristic.

Although FIG. 97 shows an example in which the filter is constituted by an analog filter, it is of course possible to constitute by a digital filter. FIG. 99 shows digital
FIG. 7 is a transmission block diagram in the case where a velocity error compensation filter is configured by a filter. In FIG. 99, the same members as those in Example 28 are shown by the same numbers. 487 and 488 are adders. At this time, the transfer function G of the velocity error compensation filter
_C (z) becomes like Formula (9).

Example 30. In the present embodiment, when the command rotation speed changes, the target rotation speed of the speed error detection circuit,
A brushless motor drive circuit configured to switch the gain of the gain element of the speed error compensation filter will be described. FIG. 100 is a block diagram showing the overall configuration of a brushless motor drive circuit according to a thirtieth embodiment of the present invention. In FIG. 100, the same components as those in FIG. 78 are indicated by the same numbers. Reference numeral 490 is an input terminal to which the mode switching signal 490a is input. The mode switching signal 490a is a signal input from the outside of the brushless motor drive circuit, and is a binary signal for switching the rotation speed of the motor.

In the waveform shaping circuit 3 described in the previous embodiment, the logical pulse signal 3d output from the OR circuit is
This is a signal obtained at constant time intervals during steady rotation. Therefore, this logic pulse signal 3d can be used as a speed signal for controlling the rotation speed. FIG. 101 shows a specific configuration example of the speed error detection circuit 409. In the figure, 491 and 492 are initial value registers, 493 is a selector, and 494 is a counter. The initial value registers 491 and 492 are registers that store the target rotation speed, and in this embodiment, there are two initial value registers in order to correspond to two types of command rotation speeds. The selector 493 uses the mode switching signal 490a.
Two types of initial value registers 49 according to the logical level of
1, 492 is switched. The counter 494 loads the initial value selected by the selector 493 at the timing of the rising edge of the logic pulse signal 3d and counts up the clock.

For example, during steady rotation, the period of the logic pulse signal 3d is 1 (msec) and 0.5 (mse).
A case will be described in which two types of command rotational speeds (c) (corresponding to command rotational speed A and command rotational speed B, respectively) are supported. The frequency of the clock is 1 (MHz), and when the mode switching signal 490a is at high level, the command rotation speed A
In addition, when the mode switching signal 490a is at a low level, the command rotational speed B is made to correspond. The initial value register 491 is set to -1000, and the initial value register 492 is set to -500. In such a configuration, when the mode switching signal 490a is at the high level, the selector 493 selects the initial value register 491, and the counter 494 loads the initial value -1000 at the timing of the rising edge of the logic pulse signal 3d. After that, the counter 494 counts up the clock and outputs a negative value when the period of the logic pulse signal 3d is shorter than 1 (msec), and a positive value when the period of the logic pulse signal 3d is longer than 1 (msec). It is output as the signal 409a. On the other hand, when the mode switching signal 490a is low level, the selector 493 selects the initial value register 492, and the counter 49
4 loads the initial value -500 at the timing of the rising edge of the logic pulse signal 3d. Then counter 4
Reference numeral 94 counts up in synchronization with the clock, and when the period of the logic pulse signal 3d is shorter than 0.5 (msec), a negative value is given, and the period of the logic pulse signal 3d is 0.5 (mse).
When it is longer than c), a positive value is output as the speed error signal 409a.

Example 31. In the above embodiment, the operation of the speed error detection circuit 409 when changing the command rotation speed has been described. However, since the target rotation speed is switched and dealt with, the detection sensitivity changes depending on the difference in the command rotation speed. In this embodiment, in order to deal with this problem, the gain element of the speed error compensation filter is also switched.

FIG. 102 shows a block diagram of the PI filter 484A when the gain element of the speed error compensation filter is switched. In FIG. 102, the same components as those of FIG. 96 shown in the twenty-eighth embodiment are denoted by the same reference numerals. 495, 4
96 is a gain element newly provided in order to correspond to another commanded rotation speed. 497 and 498 are selectors,
The selectors 497 and 498 have mode switching signals 490.
Gain elements 476 and 4 respectively depending on the logic level of a.
95 or gain element 477, 496 output is selected. Similarly, the first-order lag filter 48
The gain elements of 5, 486 are also mode switching signals 490a.
Configure to switch with. Of course, other general methods of switching the gain may be used.

In the present embodiment, the example in which the command rotation speed is switched by the 1-bit binarization signal has been described. However, when a plurality of command rotation speeds are supported, the command rotation speed is switched by the N-bit binarization signal. It can also be configured as follows.

Example 32. In the present embodiment, the relationship between the timing of switching the energized phases and the timing of increasing or decreasing the amount of current supplied to the armature winding in the brushless motor drive circuit of the present invention will be described. The overall structure of the brushless motor drive circuit of this embodiment is similar to that of FIG. FIG. 103 is a timing chart showing the operation of the brushless motor drive circuit of the present invention during steady rotation.
This will be described with reference to FIG. In the figure, 3a,
3b and 3c are rotor position signals, 9a to 9f are drive signals,
3d is a logic pulse signal representing speed, 409a is a speed error signal, and 410a is a current command value. During steady rotation, the drive signals 9a to 9f are the rotor position signals 3a, 3b,
3c based on 3c. Therefore, during steady rotation, switching of the energized phase is performed at the timing shown in the figure.

The logic pulse signal 3d is the rotor position signal 3
a, 3b, 3c both edge differential pulse. The speed error detection circuit 409 measures the cycle of the speed signal 3d, and detects the cycle error, which is the difference between the target value and the measured value, as the speed error signal 409.
It is output as a at the timing shown in FIG. The speed error signal 409a is input to the speed error compensation filter 410. The speed error compensation filter 410 performs a filter operation so that the speed error signal 409a becomes zero. Since the filter calculation requires a predetermined calculation time, the current command value 4
10a changes after the calculation time has elapsed since the speed error signal 409a changed. Current supply circuit 411
Adjusts the amount of current supplied to the armature winding based on the current command value 410a.

As described above, in the brushless motor drive circuit of the present invention, the switching timing of the energized phase and the timing of increasing / decreasing the armature winding current are synchronized, and the increase / decrease of the armature winding current is increased. Is performed after a commutation time has elapsed after commutation.

Example 33. In the present embodiment, a brushless motor drive circuit configured to supply the maximum current to the armature winding during the startup and restart periods will be described. FIG. 104 is a block diagram showing the overall configuration of the brushless motor drive circuit of this embodiment. That is, in this configuration, the switching signal 450a described in the twenty-seventh embodiment is input to the speed error compensation filter 410.

FIG. 105 shows an example of the structure of the velocity error compensation filter. In the figure, 600 is a microcontroller, 601 is a D / A converter, and 602 is a register group composed of registers 0 to N in the microcontroller 600. The microcontroller 600 uses the speed error signal 409 output from the speed error detection circuit 409.
When a is input, the filter operation as shown in the twenty-eighth embodiment and the twenty-ninth embodiment is performed, and the operation result is stored in the register N. Further, the microcontroller 600 sets the value stored in the register N to D / at a predetermined timing.
Output to the A converter 601. The digital value stored in the register N is converted into an analog value by the D / A converter 601, and the current supply circuit 411 is used as the current command value 410a.
Is input to

The switching signal 450a for switching between the starting mode and the steady rotation mode is the microcontroller 600.
Is input to As described in the twenty-seventh embodiment, the switching signal 450a is a signal that is at a low level until a predetermined time has elapsed after activation or after rebooting, and is at a high level thereafter. When the switching signal 450a goes low, the microcontroller 600 initializes the register N and sets the value of the register N to the maximum value. Therefore, while the switching signal 450a is at the low level, the current command value 410a is set to the maximum set value, and the maximum current is supplied to the armature winding during the start-up and restart.
In the present specification, different embodiments are shown for claims 1 to 28, but it is clear that sufficient effects can be obtained even if they are combined.

Example 34. FIG. 106 is a block diagram showing the overall structure of the brushless motor drive circuit of this embodiment. 106, the same components as those of FIG. 78 are indicated by the same numbers. The commutation circuit 9 described in Embodiment 27 is
In the startup mode, refer to the counter values 7a, 7b, 7c,
In the steady rotation mode, the drive signals 9a to 9f are output with reference to the rotor position signals 3a, 3b and 3c. The commutation circuit 610 of the present embodiment has counter values 7a, 7b, 7 both in the startup mode and in the steady rotation mode.
The drive signals 9a to 9f are output with reference to c. The logical relationship between the counter values 7a, 7b, 7c and the drive signals 9a-9f is the same as in FIG.

In this embodiment, another configuration example of the pulse selection circuit will be described. FIG. 107 shows a specific configuration example of the pulse selection circuit 609 having a different configuration from the pulse selection circuit 256. In the figure, 611 to 613 are inverting circuits, 614 to 625 are 3-input AND circuits, and 626 is 6
It is an input OR circuit.

Pulse selection circuit 2 shown in the eighth and 26th embodiments
56 and the operation of the pulse selection circuit 609 shown in this embodiment are compared. FIG. 108 shows rotor position signals 3a, 3b, 3c, rising / falling edge pulses 250a to 255a, counter value 7a, when the motor rotates at a constant speed and reverse rotation.
7b, 7c, output signal 256 of pulse selection circuit 256
3A shows a timing chart of the output signal 431a of the pseudo pulse generation circuit 431. On the other hand, FIG.
Is the rotor position signal 3 when the motor rotates at constant speed in reverse.
a, 3b, 3c, rising / falling edge pulses 250a to 255a, counter values 7a, 7b, 7c, an output signal 609a of the pulse selection circuit 609, and an output signal 431a of the pseudo pulse generation circuit 431. is there.

Pulse selection circuit 2 shown in the eighth and 26th embodiments
56 outputs the input edge pulse as it is when the relationship between the types of the input edge pulses 250a to 255a and the counter values 7a, 7b, 7c satisfies the relationship of FIG. 25, and otherwise inputs it. It was a circuit that masked the edge pulse. Hereinafter, description will be given with reference to FIGS. The initial value of the counter value is assumed to be LLL. Edge pulses 255a, 252a, and 251a are sequentially detected at (E), (F), and (G) in FIGS. Since the counter value is LLL, the pulse selection circuit 256 masks edge pulses other than 253a. Therefore, the edge pulses 255a, 252a, 251a detected at (E), (F), and (G) in the figure are masked.

Similarly, the pulse selection circuit 609 also masks these edge pulses. Pseudo pulse generation circuit 4
Since there is no input to the pseudo pulse generation circuit 431 even after the predetermined time t1 set in 31 has elapsed, the pseudo pulse generation circuit 431 generates a pseudo pulse at (H) in the figure. This pseudo pulse causes the hexadecimal counter 257 to count up, and the counter value becomes HLL. Then, the edge pulse 254a is detected at (I) in the figure. Since the counter value is HLL, the edge pulse 254a detected in (I) in the figure is not masked by the pulse selection circuit 256 and is output as it is. In this way, the pulse selection circuit 256 causes the edge pulses 250a to 255a during reverse rotation.
Could not be completely masked. On the other hand, in the pulse selection circuit 609, the rotor position signal 3
Since a is L, the edge pulse 254a detected in (I) in the figure is masked. As described above, the pulse selection circuit 609 of this embodiment selects the edge pulse by combining the counter value and the type of the input edge pulse, and further by combining the logics of the rotor position signals 3a, 3b, 3c. With this configuration, as shown in FIG. 109, the edge pulses 250a to 255a during reverse rotation can be completely masked.

Example 35. Next, an example of reducing the noise by making the rotor drive signal a trapezoidal wave will be described. FIG. 110 is a block diagram showing the overall structure of the brushless motor drive circuit of this embodiment. In the figure, the same components as those in FIG. 106 are denoted by the same reference numerals. 6 as a new element
Reference numeral 30 denotes a logic circuit for outputting a plurality of logic signals 630a to 630g necessary for synthesizing the trapezoidal wave drive signal, 6
Reference numeral 31 denotes a charge / discharge circuit for charging / discharging the capacitor based on the output signal 630g from the logic circuit, and 632 denotes an output signal 631a of the charge / discharge circuit and output signals 630a-6 of the logic circuit.
It is a trapezoidal wave synthesizing circuit for synthesizing trapezoidal wave-shaped drive signals 632a to 632f from 30f. A trapezoidal drive signal generation circuit 633 is constituted by including the logic circuit 630, the charge / discharge circuit 631, and the trapezoidal wave synthesis circuit 632.

FIG. 111 shows a specific configuration example of the logic circuit 630. In the figure, 635 to 643 are AND circuits, and 644 is a 3-input OR circuit. The operation waveforms of the output signals 630a to 630g of the logic circuit 630 are as shown in FIG. FIG. 112 shows a specific configuration example of the charge / discharge circuit 631. In the figure, 645 and 646 are constant current sources,
Reference numeral 647 is a capacitor. SW1 is turned on when the output signal 630g of the logic circuit 630 is at high level, and is low.
Turn off at level. The operation of the charge / discharge circuit 631 will be described. When the output signal 630g of the logic circuit is at the low level, SW1 is turned off and the capacitor 647 keeps the constant current I.
Charged at 3. On the other hand, the output signal 63 of the logic circuit 630
When 0g is at high level, SW1 is turned on and the capacitor 647 is discharged by the constant current I3. The output signal 631a of the charging / discharging circuit 631 becomes a trapezoidal wave-shaped signal as shown in FIG.

The output signal 631a of the charge / discharge circuit 631 and the output signals 630a to 630f of the logic circuit 630 are input to the trapezoidal wave synthesis circuit 632. FIG. 114 shows a specific configuration example of the trapezoidal wave synthesis circuit 632. In the figure, 648
To 651 are inverting amplifier circuits, and 652 to 657 are NAND
Circuit. It is assumed that the output voltage 631a of the charge / discharge circuit 631 and the output signals 630a to 630f of the logic circuit 630 have the same operating voltage range, and Vref is the center potential of the operating voltage range. The output signal 631a of the charging / discharging circuit 631 is input to the inverting input terminal of the inverting amplifier circuit 648, and the reference potential Vref is input to the non-inverting input terminal of the inverting amplifier circuit 648, so that a trapezoidal wave obtained by inverting 631a with reference to Vref is obtained. Similarly,
In the inverting amplifier circuits 649, 650, 651, Vref
The signals obtained by inverting 630a, 630c, and 630e are obtained with reference to.

The specific operation of trapezoidal wave synthesizing circuit 632 will be described below with reference to the drawings. Here, a description will be given focusing on a portion where the trapezoidal drive signal 632a is combined.
SW2, SW3, and SW4 are 630d, 630f, and 6 respectively.
It turns on when 52a is at a high level, and turns off when it is at a low level. 652a is an output signal of the NAND circuit 652. In the period Ta shown in FIG. 113, 630d is at a high level, 630f is at a low level, and 652a is at a low level, so only SW2 is turned on, and the trapezoidal drive signal 632a becomes the output signal 631a of the charge / discharge circuit 631. Become. In the period Tb, 630d is low level, 630f
Is low level and 652a is high level,
Only SW4 is turned on and the trapezoidal drive signal 632a is Vref.
It becomes a signal obtained by inverting 630e with reference to. In the period Tc, 630d is low level, 630f is high level, and 652a is low level, so only SW3 is turned on, and the trapezoidal drive signal 632a is 63 based on Vref.
It becomes a trapezoidal wave with 1a inverted. 630d in the period Td
Is a low level, 630f is a low level, and 652a is a high level. Therefore, only SW4 is turned on, and the trapezoidal drive signal 632a becomes a trapezoidal wave obtained by inverting 630e with reference to Vref. As described above, the trapezoidal drive signal 632
a is synthesized. The trapezoidal drive signals 632b to 632f are also combined in the same procedure. In this way, the trapezoidal drive signal generation circuit 633 causes the drive signals 9a to 9f to rise.
Trapezoidal drive signals 632a-63 in which the rising slope portion and the falling slope portion start from the time of the falling edge
2f is generated.

Example 36. In the present embodiment, the trapezoidal drive signals 632a to 632a corresponding to the command rotation speed input from the outside.
A brushless motor drive circuit configured to change the inclination time of 32f will be described. FIG. 115 is a block diagram showing the overall configuration of the brushless motor drive circuit of this embodiment. In the figure, the same components as those in FIG. 110 are denoted by the same reference numerals. In FIG. 115,
660 is a terminal to which the mode switching signal 660a is input, and 661 is a charging / discharging circuit having a configuration different from that of the charging / discharging circuit 631. The mode switching signal 660a is a signal input from the outside of the brushless motor drive circuit, and is a binarized signal whose polarity changes according to the command rotation speed.

FIG. 116 shows a specific structural example of the charge / discharge circuit 661. In the figure, 662 is an inverting circuit, and 66
3, 664 are constant current sources. SW5 and SW7 turn on when the mode switching signal 660a is at a high level, and turn off when the mode switching signal 660a is at a low level. SW6 and SW8 are turned on when the mode switching signal 660a is at a low level, and turned off when the mode switching signal 660a is at a high level.

The operation of the charge / discharge circuit 661 when the mode switching signal 660a is at high level will be described.
When the output signal 630g of the logic circuit is low level, SW
1 is turned off, and the capacitor 647 is charged with the constant current I3. On the other hand, the output signal 630g of the logic circuit 630 is high.
At the level, SW1 is turned on, and the capacitor 647 is discharged with the constant current I3. Output signal 630 of logic circuit 630
The relationship between g and the output signal 661a of the charge / discharge circuit 661 is shown in FIG.
At 17, 632a becomes as shown by H.

When the mode switching signal 660a is low level, the capacitor 647 is charged by the constant current I4 when the output signal 630g of the logic circuit is low level,
When the output signal 630g of the logic circuit 630 is high level, the capacitor 647 is discharged with the constant current I4.

When I4 = 0.5 × I3 is set, the output signal 661a of the charging / discharging circuit 661 becomes 632a indicated by L in FIG. 117, and the trapezoidal wave inclination time is
Double. The output signal 661a of the charge / discharge circuit 661 is input to the trapezoidal wave synthesis circuit 632, and the trapezoidal drive signals 632a to 632f are generated by the procedure described in the 35th embodiment. In this way, the mode switching signal 6
By switching 60a, the trapezoidal drive signals 632a to 632f corresponding to the commanded rotation speed input from the outside.
It is possible to change the slope time of.

Example 37. Trapezoidal drive signal generation circuit 633
The rising slope portion and the falling slope portion of the trapezoidal drive signals 632a to 632f generated by
It starts from the rising and falling edges of a to 9f. Therefore, the switching point of the drive current is delayed from the ideal commutation timing, and the torque generation efficiency is reduced. In the present embodiment, the configuration of the brushless motor drive circuit is configured so that the phase of the rotor position signal detected from each phase terminal potential or each inter-phase voltage difference is set to the lead phase corresponding to the tilt time of the trapezoidal drive signal. The operation will be described.

FIG. 118 is a block diagram showing the overall structure of the brushless motor drive circuit of this embodiment. In the figure, the same components as those in FIG. 110 are denoted by the same reference numerals. In FIG. 118, a new element 670 is a comparison circuit having a configuration different from that of the comparison circuit 2. Also,
FIG. 119 shows a specific configuration example of the comparison circuit 670.
In the figure, 671 to 685 are resistors, and 686 to 688 are differential amplifier circuits.

The specific operation of the comparison circuit 670 will be described below. As an example, resistors 671 to 685 are shown in FIG.
Consider the case where the value is set to the value shown in FIG. At this time, the output signal 686a of the differential amplifier circuit 686 is 1a +
1b-2 × 1c, the output signal 68 of the differential amplifier circuit 687
7a becomes 1b + 1c-2 × 1a, and the output signal 688a of the differential amplifier circuit 688 becomes 1c + 1a-2 × 1b. now,
Assuming that 1a, 1b, and 1c are three-phase signals that are out of phase by 2π / 3 as shown in Expression (10), output signals 686a and 687 of the differential amplifier circuits 686, 687, and 688.
a and 688a are expressed by equations (11), (12), and (13). The output signals 686a, 687a, 688a of the differential amplifier circuits 686, 687, 688 are the comparator 8 respectively.
5, 86 and 87 are compared with Vref and logic signal 670
a, 670b, 670c are obtained. 1a = sin θ 1b = sin (θ + 2π / 3) 1c = sin (θ−2π / 3) (10) 686a = sin θ + sin (θ + 2π / 3) −2 × sin (θ−2π / 3) = 3 × sin (θ + π /) 3) (11) 687a = sin (θ + 2π / 3) + sin (θ-2π / 3) −2 × sin θ = 3 × sin (θ + π) (12) 688a = sin (θ−2π / 3) + sin θ−2 × sin (Θ + 2π / 3) = 3 × sin (θ−π / 3) (13)

Here, the specific operation of the comparison circuit 2 will be described again. Consider a case where the resistors 70 to 81 are all set to 10 KΩ. At this time, the output signal of the differential amplifier circuit 82 is 1a-1c, the output signal of the differential amplifier circuit 83 is 1b-1a, and the output signal of the differential amplifier circuit 84 is 1c.
−1b, which are as in equations (14), (15), and (16), respectively. The output signals of the differential amplifier circuits 82, 83, 84 are 82a, 83a, 84a. A differential amplifier circuit 82,
Output signals 82a, 83a, 84a of 83, 84 are respectively compared with Vref by comparators 85, 86, 87 to obtain logic signals 2a, 2b, 2c. 82a = sin θ−sin (θ−2π / 3) = √3 × sin (θ + π / 6) (14) 83a = sin (θ + 2π / 3) −sin θ = √3 × sin (θ + 5π / 6) (15) 84a = sin (θ-2π / 3) -sin (θ + 2π / 3) = √3 × sin (θ−π / 2) (16)

The output signals 686a, 687a, 688a of the differential amplifier circuits 686, 687, 688 are advanced in π / 6 phase with respect to the output signals 82a, 83a, 84a of the differential amplifier circuits 82, 83, 84. . Therefore, in the comparison circuit 670, the logic signal 2a output from the comparison circuit 2 is
A logic signal 670a with a π / 6 phase advanced from 2b and 2c,
670b and 670c can be obtained. Although the values of the resistors 671 to 685 are set to the values shown in FIG. 119 in the present embodiment, it is possible to set a different phase lead amount by changing the resistors 671 to 685. In this way, the phase of the rotor position signal is advanced so that the switching point of the drive current matches the ideal commutation timing. It should be noted that although the configuration example using the charging / discharging circuit 631 is shown in this embodiment, the charging / discharging circuit 661 may of course be used.

[0249]

Since the present invention is constructed as described above, the following effects can be obtained.

Since the neutral point is not used and the position signal is obtained by correcting the correction value determined by the armature winding current only during the actual driving period, the lead lines are small and the correct driving timing without phase delay is obtained. Is effective.

Since the neutral point is not used and the correction value determined by the armature winding current is corrected only for the actual driving period to obtain the position signal from the voltage difference between the phases, the number of lead lines is small and the phase delay is small. There is the effect that the correct drive timing can be determined.

Further, since the velocity equivalent signal is obtained from the position signal, there is an effect that the velocity can be controlled by a simple device in addition to the above.

Furthermore, since the actual driving period is the period during which the driving signal is in the driving state, there is an effect that the phase delay can be corrected more accurately.

Furthermore, since the actual drive period for correcting the inter-phase voltage difference is set to the period in which the drive signal is in the drive state, there is an effect that the phase delay can be corrected more accurately.

Further, since the correction voltage is obtained from the resistance for detecting the current flowing through the armature winding, there is an effect that the phase delay can be corrected more accurately.

Furthermore, since the correction voltage is obtained from the resistance for detecting the current flowing through the armature winding, there is an effect that the phase delay of the voltage difference between the phases can be corrected more accurately.

Further, since the position signal is latched to be a new position signal, there is an effect that the correct position signal can be detected even if the detection signal has noise.

The rising and falling edge signals of the position signal are selected, counted and combined into a drive signal, and forcibly counted when there is no input, so that there is an effect that stable startup is possible.

[0259] Edge signals at the rising and falling edges of the position signal are selected, counted and combined as a drive signal, forcibly counted when there is no input, and restarted when there is a rotation error. It has the effect of being able to restart even in the event of abnormalities.

Since the switching between the start / restart and the steady state is switched at a predetermined time, there is an effect that the steady operation can be surely started.

Since switching between the start-up / restart and the steady state is switched by the counter value of the counter, there is an effect that the steady operation can be surely performed.

Since the switching between the start / restart and the steady state is switched when the rotor reaches a certain speed, there is an effect that the steady operation can be surely started.

Since the switching between the start-up / restart and the steady state is switched by the predetermined combination of the detected position signals, there is an effect that the steady operation can be surely started.

Since the switching between the start-up / restart and the steady state is switched by the predetermined combination of the drive signals to the armature winding, there is an effect that the steady operation can be surely started.

Switching between the start / restart and the steady state is performed in a predetermined combination for a predetermined time, a count-up value, reaching a predetermined speed, a detected position signal and a drive signal to the armature winding. Since the switching is performed when a plurality of conditions are satisfied, there is an effect that the steady operation can be more reliably performed.

Since the position signal to the counter is monitored and forcedly counted when there is no input and restarted when the rotation is abnormal, it is possible to restart even when the rotation is abnormal.

Since the position signal from another position detector set at a certain electrical angle is used as the drive signal for starting / restarting,
It has an effect that a correct start can be surely obtained at the time of start.

Since the position signal from another position detector set at a certain electrical angle is used as the drive signal for starting / restarting,
It has an effect that a correct start can be surely obtained at the time of start.

Since the logic signal obtained by comparing the terminal potentials is differentiated and latched and the latch is released after a predetermined time, the correct rotor position signal can be obtained even if the detection signal has noise.

Further, since the timer time length is made variable, there is an effect that stable commutation control can be performed by masking noise with an appropriate time as a transition time.

At the time of startup, restart or abnormal rotation,
Since the forced energized phase in which the motor is normally rotated is switched for a predetermined time, there is an effect that the motor can be reliably started in a short time without being affected by the load condition.

Since the switching from the starting mode to the steady rotation mode is set by the timer, there is an effect that the steady rotation mode can be surely shifted.

Since the speed error compensating filter is configured by connecting the PI filter and the first-order lag filter in parallel and further connecting the first-order lag filter in series, there is an effect that a good low-range disturbance compression characteristic can be obtained. .

Since the velocity error compensating filter has a structure in which the first-order lag filter is connected in series to the PI filter and the first-order lag filter is connected in parallel, there is an effect that excellent low-range disturbance compression characteristics can be obtained.

Since the target value of the speed error detector or the gain of the speed error compensating filter is switched according to the command rotation speed to the motor, it is possible to change the cycle of the reference clock input to the speed error detector. It has the effect of being good.

Since the increase / decrease in the amount of current supplied to the armature winding is performed in order within a predetermined time after switching the energized phase, the current value is fed back to correct the terminal potential. There is an effect that can be easily done.

Since the maximum current is supplied to the armature winding during the starting and restarting, there is an effect that the starting can be surely started in a short time.

Since the required signal within the rising and falling edges of the rotor position signal is selected and the armature winding is driven by the counter value that counts this required signal, it can be started reliably in a short time. In addition, there is an effect that it is possible to reliably shift to steady operation.

Since the armature winding is applied and driven by the trapezoidal wave drive signal, there is an effect that noise during commutation can be reduced.

Since the gradient of the trapezoidal wave drive signal is changed by the control signal from the outside, there is an effect that the commutation noise can be surely reduced even if the rotation speed of the motor changes.

Since the phase of the rotor position signal is advanced so that the substantially gradient center of the trapezoidal wave drive signal coincides with the optimum commutation timing, noise can be reduced without lowering torque generation efficiency. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a brushless motor drive device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration example of a terminal potential correction circuit.

FIG. 3 is a diagram illustrating a specific configuration example of a comparison circuit according to the first exemplary embodiment.

FIG. 4 is a signal waveform diagram for explaining the operation of the first and second embodiments.

FIG. 5 is a signal waveform diagram for explaining the operation of the first and second embodiments.

FIG. 6 is a configuration diagram of a correction switching signal generation circuit and a signal waveform diagram of a terminal potential circuit.

FIG. 7 is a diagram showing a relationship between an energized phase and a drive signal.

FIG. 8 is a block diagram showing an overall configuration of a brushless motor drive device according to a second embodiment of the present invention.

FIG. 9 is a diagram showing a specific configuration example of a terminal voltage correction circuit.

FIG. 10 is a table diagram for explaining the operation of the terminal voltage correction circuit.

FIG. 11 is a diagram illustrating a specific configuration example of a comparison circuit according to the second embodiment.

FIG. 12 is a table diagram for explaining the operation of the terminal voltage correction circuit.

FIG. 13 is a block diagram showing an overall configuration of a brushless motor drive device according to a third embodiment of the present invention.

FIG. 14 is a block diagram showing an overall configuration of a brushless motor drive device according to a fourth embodiment of the present invention.

FIG. 15 is a block diagram showing an overall configuration of a brushless motor drive device according to a fifth embodiment of the present invention.

FIG. 16 is a block diagram showing an overall configuration of a brushless motor drive device according to a sixth embodiment of the present invention.

FIG. 17 is a diagram showing a specific configuration example of a waveform shaping circuit.

FIG. 18 is a signal waveform diagram for explaining the operation of the waveform shaping circuit.

FIG. 19 is a signal waveform diagram for explaining the operation of the waveform shaping circuit.

FIG. 20 is a block diagram showing the overall configuration of an eighth embodiment of the brushless motor drive device of the present invention.

FIG. 21 is a table diagram showing the relationship between drive signals and energized phases according to the eighth embodiment.

FIG. 22 is a table diagram showing a relationship between a drive signal and a rotor position signal according to the eighth embodiment.

FIG. 23 is a diagram illustrating a specific configuration example of a counter circuit according to an eighth embodiment.

FIG. 24 is a table diagram for explaining the operation of the counter circuit according to the eighth embodiment.

FIG. 25 is a table diagram for explaining the operation of the counter circuit according to the eighth embodiment.

FIG. 26 is a diagram showing a specific configuration example of the pulse generation circuit of the eighth embodiment.

FIG. 27 is a table diagram showing the relationship between the drive signal and the output value of the counter circuit of the eighth embodiment.

FIG. 28 is a timing chart diagram for explaining the operation of the eighth embodiment.

FIG. 29 is a timing chart for explaining the operation of the eighth embodiment.

FIG. 30 is a block diagram showing the overall configuration of a ninth embodiment of the brushless motor drive device of the present invention.

FIG. 31 is a table diagram showing a relationship between a rotor position signal and a counter value.

FIG. 32 is a timing chart diagram for explaining the operation of the ninth embodiment.

FIG. 33 is a block diagram showing an overall configuration of a brushless motor drive device according to a tenth embodiment of the present invention.

FIG. 34 is a diagram showing a specific configuration example of the switching signal generation circuit of the tenth embodiment.

FIG. 35 is a timing chart diagram for explaining the operation of the switching signal generating circuit of the tenth embodiment.

FIG. 36 is a block diagram showing the overall structure of an eleventh embodiment of the brushless motor drive device of the present invention.

FIG. 37 is a diagram showing a specific configuration example of the switching signal generation circuit of the eleventh embodiment.

FIG. 38 is a timing chart diagram for explaining the operation of the switching signal generating circuit of the eleventh embodiment.

FIG. 39 is a block diagram showing the overall structure of a twelfth embodiment of the brushless motor drive device of the present invention.

FIG. 40 is a diagram showing a specific configuration example of the switching signal generation circuit of the twelfth embodiment.

FIG. 41 is a timing chart diagram for explaining the operation of the switching signal generation circuit of the twelfth embodiment.

[Fig. 42] Fig. 42 is a block diagram showing the overall structure of a thirteenth embodiment of the brushless motor drive device of the present invention.

FIG. 43 is a diagram showing a specific configuration example of the switching signal generation circuit of the thirteenth embodiment.

FIG. 44 is a timing chart diagram for explaining the operation of the switching signal generating circuit of the thirteenth embodiment.

FIG. 45 is a block diagram showing the overall structure of a fourteenth embodiment of the brushless motor drive device of the present invention.

FIG. 46 is a diagram showing a specific configuration example of the switching signal generation circuit of the fourteenth embodiment.

FIG. 47 is a timing chart diagram for explaining the operation of the switching signal generating circuit of the fourteenth embodiment.

[Fig. 48] Fig. 48 is a block diagram showing the overall structure of a fifteenth embodiment of the brushless motor drive device of the present invention.

FIG. 49 is a diagram showing a specific configuration example of the switching signal generation circuit of the fifteenth embodiment.

FIG. 50 is a timing chart diagram for explaining the operation of the switching signal generation circuit of the fifteenth embodiment.

FIG. 51 is a block diagram showing the overall structure of a sixteenth embodiment of the brushless motor drive device of the present invention.

FIG. 52 is a diagram showing a specific configuration example of the switching signal generation circuit of the sixteenth embodiment.

FIG. 53 is a timing chart diagram for explaining the operation of the speed signal generation circuit.

FIG. 54 is a timing chart diagram for explaining the operation of the switching signal generating circuit of the sixteenth embodiment.

FIG. 55 is a block diagram showing the overall structure of a seventeenth embodiment of the brushless motor drive device of the present invention.

FIG. 56 is a diagram showing a specific configuration example of the switching signal generation circuit of the seventeenth embodiment.

FIG. 57 is a timing chart diagram for explaining the operation of the switching signal generating circuit of the seventeenth embodiment.

FIG. 58 is a block diagram showing the overall structure of an eighteenth embodiment of the brushless motor drive device of the present invention.

FIG. 59 is a diagram showing a specific configuration example of the switching signal generation circuit of the eighteenth embodiment.

FIG. 60 is a timing chart diagram for explaining the operation of the switching signal generating circuit of the eighteenth embodiment.

FIG. 61 is a block diagram showing the overall configuration of a nineteenth embodiment of the brushless motor drive device of the present invention.

FIG. 62 is a diagram showing a specific configuration example of a switching signal generation circuit of the nineteenth embodiment.

FIG. 63 is a timing chart diagram for explaining the operation of the switching signal generating circuit of the nineteenth embodiment.

[Fig. 64] Fig. 64 is a block diagram showing the overall structure of a twentieth embodiment of the brushless motor drive device of the present invention.

FIG. 65 is a diagram showing a specific configuration example of the switching signal generation circuit of the twentieth embodiment.

FIG. 66 is a timing chart diagram for explaining the operation of the switching signal generating circuit of the twentieth embodiment.

FIG. 67 is a block diagram showing the overall structure of a twenty-first embodiment.

FIG. 68 is a block diagram showing the overall structure of a twenty-second embodiment of the brushless motor drive device of the present invention.

FIG. 69 is a timing chart illustrating the operation of the twenty-second embodiment.

FIG. 70 is a table diagram for explaining the operation of the twenty-second embodiment.

FIG. 71 is a diagram showing a specific configuration example of the counter circuit according to the twenty-second embodiment.

72 is a table diagram for explaining the operation of Example 22. FIG.

FIG. 73 is a timing chart illustrating the operation of the twenty-second embodiment.

FIG. 74 is a timing chart illustrating the operation of the twenty-second embodiment.

FIG. 75 is a block diagram showing the overall structure of a brushless motor drive device according to a twenty third embodiment of the present invention.

FIG. 76 is a timing chart illustrating the operation of the twenty-third embodiment.

77 is a timing chart illustrating the operation of the twenty-third embodiment. FIG.

[Fig. 78] Fig. 78 is a block diagram showing the overall structure of a twenty-fourth embodiment of the brushless motor drive device of the present invention.

FIG. 79 is a diagram showing signal waveforms of respective parts of the terminal potential correction circuit in a steady rotation state of the brushless motor drive device of the present invention.

80 is a diagram showing a configuration example of the waveform shaping circuit in FIG. 78. FIG.

FIG. 81 is a diagram showing a terminal potential waveform and a waveform of each part of the waveform shaping circuit in steady rotation.

82 is a signal waveform diagram for explaining the operation of the waveform shaping circuit in FIG. 80. FIG.

83 is a signal waveform diagram for explaining operations of the mask signal generation circuit and the timer according to the twenty-fifth embodiment. FIG.

FIG. 84 is a signal waveform diagram for explaining the operations of the mask signal generation circuit and the timer according to the twenty-fifth embodiment.

FIG. 85 is a signal waveform diagram for explaining operations of the mask signal generation circuit and the timer according to the twenty-fifth embodiment.

FIG. 86 is a diagram showing the configuration of the starting circuit of the twenty-sixth embodiment.

FIG. 87 is a diagram showing the configuration of the pseudo pulse generation circuit of the twenty-sixth embodiment.

88 is a signal waveform diagram for explaining the operation of the pseudo pulse generation circuit of the twenty-sixth embodiment. FIG.

FIG. 89 is a diagram showing a configuration example of a restart pulse generation circuit of the twenty-sixth embodiment.

FIG. 90 is a signal waveform diagram for explaining the operation of the twenty-sixth embodiment.

FIG. 91 is a diagram showing the configuration of the starting circuit of the twenty-seventh embodiment.

FIG. 92 is a diagram showing the configuration of the switching signal generation circuit of the twenty-seventh embodiment.

FIG. 93 is a signal waveform diagram representing an operation of the switching signal generation circuit.

FIG. 94 is a block diagram of a velocity error compensation filter according to a twenty-eighth embodiment.

FIG. 95 is a diagram showing frequency characteristics of the velocity error compensation filter according to the twenty-eighth embodiment.

FIG. 96 is a block diagram of a digital velocity error compensation filter according to a twenty-eighth embodiment.

FIG. 97 is a block diagram of a velocity error compensation filter according to a twenty ninth embodiment.

FIG. 98 is a diagram showing frequency characteristics of the velocity error compensation filter according to the twenty ninth embodiment.

FIG. 99 is a block diagram of a digital speed error compensation filter according to a twenty ninth embodiment.

FIG. 100 is a block diagram showing the overall configuration of a brushless motor drive circuit according to a thirtieth embodiment of the present invention.

FIG. 101 is a diagram showing the structure of the speed error detection circuit according to the thirtieth embodiment.

FIG. 102 is a block diagram of a PI filter according to a thirty-first embodiment.

103 is a signal waveform diagram for explaining the operation of the brushless motor drive circuit according to the thirty-second embodiment. FIG.

FIG. 104 is a block diagram showing an overall structure of a brushless motor drive circuit according to a working example 33 of the invention.

FIG. 105 is a diagram showing a configuration of a velocity error compensation filter according to a thirty-third embodiment.

FIG. 106 is a block diagram showing an overall structure of a brushless motor drive circuit according to a working example 34 of the invention.

FIG. 107 is a diagram showing the configuration of the pulse selection circuit of the thirty-fourth embodiment.

FIG. 108 is a timing chart diagram illustrating an operation of the drive circuit of the thirty-fourth embodiment.

FIG. 109 is a timing chart illustrating the operation of the drive circuit according to the thirty-fourth embodiment.

FIG. 110 is a block diagram showing an overall structure of a brushless motor drive circuit according to a working example 35 of the invention.

FIG. 111 is a diagram showing a configuration of a logic circuit in the trapezoidal drive signal generation circuit.

FIG. 112 is a diagram showing the configuration of the charging / discharging circuit of the thirty-fifth embodiment.

113 is a timing chart diagram for explaining the operation of the drive circuit in the embodiment 35. FIG.

FIG. 114 is a diagram showing a configuration of a trapezoidal wave synthesis circuit in the trapezoidal drive signal generation circuit.

FIG. 115 is a block diagram showing the overall structure of a brushless motor drive circuit according to a thirty-sixth embodiment of the present invention.

FIG. 116 is a diagram showing the configuration of the charging / discharging circuit of the thirty-sixth embodiment.

117 is a signal waveform diagram for explaining the operation of the drive circuit in the thirty-sixth embodiment. FIG.

FIG. 118 is a block diagram showing the overall structure of a brushless motor drive circuit according to Example 37 of the present invention.

FIG. 119 is a diagram showing the configuration of the comparison circuit of the thirty-seventh embodiment.

FIG. 120 is a block diagram showing an overall configuration of a conventional brushless motor drive device.

FIG. 121 is a diagram showing another overall configuration and operation timing of a conventional brushless motor drive device.

FIG. 122 is a block diagram showing a configuration of a speed control system of a conventional brushless motor drive circuit.

FIG. 123 is a block diagram of a speed error compensation filter of a conventional brushless motor drive circuit.

[Explanation of symbols]

1 terminal potential correction circuit, 2 comparison circuit, 3 waveform shaping circuit, 4 rotor position signal generation circuit, 5 terminals, 6 pulse generation circuit, 7 counter circuit, 8, 8C, 8D, 8
E, 8F, 8G, 8H, 8I, 8J, 8K, 8L switching signal generation circuit, 9 commutation circuit, 10 resistance, 11 bridge circuit, 12, 13, 14 armature winding, 16 correction switching signal generation circuit, 20 ~ 34 npn transistor, 3
5 pnp transistor, 36-56 resistor, 57-6
0 constant current source, 61-67 terminals, 70-81 resistance,
82-84 differential amplifier, 85-87 comparator,
100 terminal voltage correction circuit, 101 comparison circuit, 10
2 rotor position signal generation circuit, 110-127 npn
Transistor, 128 pnp transistor, 129-
155 resistance, 156-162 constant current source, 163-1
69 terminal, 170-172 comparator, 180
Latch circuit, 181-186 D flip-flop, 1
87-189 EOR circuit, 190 OR circuit, 191
Monostable multivibrator, 210 commutation control circuit,
211 current control circuit, 212 buffer amplifier, 21
3 resistors, 214 transistors, 250, 252, 2
54 rising edge detection circuit, 251, 253, 25
5 Falling edge detection circuit, 256 pulse selection circuit, 257 hexadecimal counter, 260 retriggerable
One shot, 261 rising edge detection circuit, 2
65 steady rotation detection circuit, 270 timer, 271 mode switching counter, 272 position signal combination determination circuit, 273 AND circuit, 274 latch circuit, 275
Drive signal combination determination circuit, 276 reference speed generation circuit, 277 speed signal generation circuit, 278 comparison circuit,
280 position signal counter value determination circuit, 300 position detector, 301 hold circuit, 302 edge detection circuit, 406, 406B start-up circuit, 409 speed error detection circuit, 410 speed error compensation filter, 411 current supply circuit, 421 mask signal generation circuit 422 timer, 431 pseudo pulse generation circuit, 432 restart pulse generation circuit, 433 counter, 434 gate circuit,
435 rising edge detection circuit, 436 delay circuit, 437 OR circuit, 440 rising edge detection circuit, 441 OR circuit, 442 counter, 443
Gate circuit, 444 Rising edge detection circuit, 4
45 AND circuit, 446 OR circuit, 450 switching signal generation circuit, 451 rising edge detection circuit,
452 OR circuit, 453 counter, 454 gate circuit, 455 OR circuit, 460 PI filter, 46
1 1st-order lag filter, 462 gain element, 463 adder, 464 1st-order lag filter, 470, 471, 4
72 delay elements, 473, 474, 475, 476, 4
77, 478, 479 gain element, 481, 482, 4
83 adder, 484 PI filter, 485, 486
First-order lag filter, 487, 488 adder, 490
Terminal, 491, 492 initial value register, 493 selector, 494 counter, 495, 496 gain element, 497, 498 selector, 600 microcontroller, 601 D / A converter, 602 register group, 609 pulse selection circuit, 610 commutation circuit , 61
1-613 inverting circuit, 614-625 3-input AND
Circuit, 626 6-input OR circuit, 630 logic circuit, 6
31 charge / discharge circuit, 632 trapezoidal wave synthesis circuit, 633 trapezoidal drive signal generation circuit, 635-643 AND circuit, 6
44 3-input OR circuit, 645, 646 Constant voltage power supply, 6
47 capacitors, 648 to 651 inverting amplifier circuit, 6
52-657 NAND circuit, 660 terminal, 661
Charge / discharge circuit, 662 inversion circuit, 663, 664 constant current source, 670 comparison circuit, 671-685 resistance, 686
~ 688 differential amplifier circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Atsuo Onoda 5-1-1 Ofuna, Kamakura-shi Personal Information Equipment Development Laboratory, Mitsubishi Electric Corporation (72) Inventor Keiichi Nishikawa 5-1-1 Ofuna, Kamakura-shi Mitsubishi Electric Co., Ltd. Personal Information Equipment Development Laboratory (72) Inventor Ryocho Suzuki 2-25 Sakaemachi, Koriyama City Mitsubishi Electric Co., Ltd. Koriyama Factory (72) Inventor Seisei Hoshisei 2-25 Sakaemachi, Koriyama City Mitsubishi Electric Corporation Company Koriyama Factory

Claims (32)

[Claims] 1. A winding terminal potential detecting means for each phase of a brushless motor that drives a rotor by a plurality of phases of armature windings, and a correction value determined by the resistance and winding current of the armature windings for each phase. Each phase terminal potential correction means for adding / subtracting the actual winding period to the detection winding terminal potential and comparison means for comparing the magnitude of each phase terminal potential after the above correction are provided, and each of the rotor position signals detected by the comparison means is used. A drive circuit for a brushless motor that drives the phase armature winding. 2. A phaseless winding terminal potential detecting means of a brushless motor for driving a rotor with a plurality of phases of armature windings, and a correction value determined by the resistance of the armature windings and winding currents between phases. Each phase voltage difference correction means for adding / subtracting the actual drive period to the winding terminal voltage difference of (4) and comparison means for comparing the magnitude of each phase voltage difference after the correction are provided, and each of the rotor position signals detected by the comparison means is used. A drive circuit for a brushless motor that drives the phase armature winding. 3. The brushless according to claim 1, wherein the rotor position signal rising / falling signal detecting means is provided, and the speed feedback control is performed by regarding the detection result as a detected speed signal. Motor drive circuit. 4. The phase terminal potential correcting means is provided as a real drive period signal with a period during which a drive signal to a bridge circuit for exciting and driving each phase armature winding is in a drive state. The drive circuit for the brushless motor according to 1. 5. The voltage difference correcting means for each phase is provided with a period during which a drive signal to a bridge circuit for exciting and driving the armature winding of each phase is in a drive state as an actual drive period signal. 2. The drive circuit for a brushless motor according to 2. 6. A real current detection resistor connected in series to a bridge circuit for exciting and driving an armature winding, and a current flowing through the detection resistor is given to each phase terminal potential correcting means as a winding current. The brushless motor drive circuit according to claim 1. 7. An actual current detection resistor connected in series to a bridge circuit for exciting and driving an armature winding, and a current flowing through the detection resistor is applied as a winding current to the inter-phase voltage difference correction means. The brushless motor drive circuit according to claim 2. 8. A differential circuit for detecting rising / falling edges of a comparison signal having a large / small potential of each phase terminal or a large / small voltage difference between respective phases, and latching the comparison signal at a timing when the edge is detected by the differential circuit. 3. A brushless motor drive according to claim 1, further comprising a latch circuit for driving the armature winding of each phase as a rotor position signal by combining the outputs of the respective latch circuits. circuit. 9. A rotor position signal generating means for detecting a position signal of the rotor from a terminal potential of each phase or a voltage difference between the phases of a brushless motor for driving the rotor by armature windings of a plurality of phases, The rising and falling edges of the rotor position signal are detected, the required edge signal is selected from the detected edge signals and used as one output, and the required edge signal is counted and the armature winding of each phase at start-up And a pulse generation means for inputting one of the outputs of the counter and not counting the input when the input is not obtained for a predetermined time. A drive circuit for a brushless motor that drives the windings. 10. A rotor position signal generating means for detecting a position signal of the rotor from a terminal potential of each phase or a voltage difference between the phases of a brushless motor for driving the rotor with armature windings of a plurality of phases, The rising and falling edges of the rotor position signal are detected, the required edge signal is selected from the detected edge signals and used as one output, and the required edge signal is counted and the armature winding of each phase at start-up And a pulse generating means for counting up the counter when the output of one of the counters is input and the input is not obtained for a predetermined time, the rotor position signal and the counter output. It is equipped with a steady rotation detection unit that monitors the rotation of the motor in combination with and outputs a restart pulse to start the motor in the case of abnormal rotation. A drive circuit for a brushless motor that applies force to the armature winding. 11. A switching means and a timer for switching to drive the armature winding of each phase based on the value of the counter at the time of start-up or restart and based on the rotor position signal at the time of subsequent steady state are provided. 10. The restart period is set by the timer and switched.
A drive circuit for a brushless motor according to claim 10. 12. Switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of starting or restarting, and at the time of steady state thereafter, based on the rotor position signal, said counter is set to a predetermined value. 11. The drive circuit for the brushless motor according to claim 9 or 10, wherein the drive circuit is switched when the start or restart period has ended when the value becomes. 13. Switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of start-up or restart and based on the rotor position signal at the subsequent steady state, and a speed signal of the rotor. 11. The brushless motor drive circuit according to claim 9 or 10, wherein detection means is provided and switching is performed when the startup or restart period has ended when the detected speed signal reaches a predetermined value. 14. A detected rotor is provided with switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of starting or restarting, and at the time of steady state thereafter based on the rotor position signal. 11. The brushless motor drive circuit according to claim 9, wherein the drive signal is switched when the start-up or restart-up period has ended when the position signal of the above becomes a predetermined combination value. 15. A switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of start-up or restart, and based on the rotor position signal at the subsequent steady state, the electric machine of each phase is provided. 11. The brushless motor drive circuit according to claim 9 or 10, wherein the drive circuit for the brushless motor is switched when the drive signal to the child winding reaches a predetermined combination value and the start or restart period has ended. 16. Switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of starting or restarting, and based on the rotor position signal at the subsequent steady state, and a timer if necessary. Alternatively, a speed signal detecting means for the rotor is provided, and the timer setting time elapses, the speed signal detection value reaches a predetermined value, the counter reaches a predetermined value, or the detected rotor position signal becomes a predetermined combination value. Or the fact that a plurality of combinations of the drive signals to the armature windings of the respective phases form a predetermined combination are satisfied, and the switching is performed as the start or restart period is over. Item 10
The brushless motor drive circuit described. 17. The counter is a counter that outputs a restart pulse as a rotation abnormality to enter a startup state when the rotor position signal input to the counter does not change for a predetermined time, and forcibly counts up. The brushless motor drive circuit according to claim 9, wherein the brushless motor drive circuit is provided. 18. A position detector for detecting a position deviated from an electric angle π / 6 with respect to a rotor position signal detected from a potential of each phase terminal or a voltage difference between each phase, and an output and a start instruction of the position detector. 10. A holding circuit for outputting a selection signal determined by a signal is provided, and a counter determines a combination of drive signals to the armatures of respective phases by the selection signal at the time of start-up or restart. Drive circuit for brushless motor. 19. A position detector for detecting a position deviated by an electrical angle of π / 6 with respect to a rotor position signal detected from a potential of each phase terminal or a voltage difference between each phase, and an output and a start instruction of the position detector. A hold circuit that outputs a selection signal determined by the signal is provided.The above position detector output is used for the first drive signal to the armature at the time of start-up or restart, and the counter is used for the subsequent drive at start-up or restart. 10. The drive circuit for a brushless motor according to claim 9, wherein the selection signal uses a signal that determines a combination of drive signals to the armatures of the respective phases. 20. A differentiating circuit for detecting rising and falling edges of a comparison signal having a large or small voltage of each phase terminal or a large or small voltage difference between respective phases, and a timer which operates by detecting the edge of the differentiating circuit and stops after a predetermined time. , A latch circuit that latches the comparison signal at the timing when the edge is detected by the differentiating circuit and releases the latch at the timing when the timer stops, and combines the latch circuit outputs to output the rotor position signal of each phase. The drive circuit for a brushless motor according to claim 1 or 2, wherein the armature winding is applied and driven. 21. The timer time length from when the latch circuit latches the comparison signal to when it is unlatched is changed based on a command rotation speed to the armature.
A drive circuit for a brushless motor according to 0. 22. Rotor position signal generating means for detecting a rotor position signal from the phase terminal potentials of the plurality of phases or voltage differences between the phases, and rising and falling edges of the output rotor position signal. A pulse generating means for selecting a necessary edge signal from the detected edge signals to give an output pulse train, and a pseudo pulse train when the necessary edge signal is not obtained for a predetermined time, and a counter for counting the output of the pulse generating means. A steady rotation detecting means for outputting an abnormal rotation signal when the relationship between the rotor position signal and the value of the counter is not in a predetermined relation, and the rotation of the steady rotation detecting means within a set time after starting and restarting. An abnormality signal is masked, and after the set time has elapsed, a restart pulse generating means for outputting a restart pulse based on the rotation abnormality signal is provided. Brushless motor driving circuit within the set time at the time of re-activation by the dynamic pulse that performs application driving of the armature winding at the counter output. 23. A switching means and a timer for switching to drive the armature winding of each phase based on the value of the counter at the time of start-up or restart and at the time of subsequent steady state based on the rotor position signal are provided. The restart period is set by the timer and switched.
2. The drive circuit for a brushless motor according to 2. 24. Speed detection means for detecting the speed at which the rotor is rotating, speed error detection means for outputting a difference between the detected actual rotation speed of the rotor and a target rotation speed as a speed error signal, The detected speed error signal is input, and its configuration is composed of a parallel circuit of a proportional / integral (PI) filter and a first-order lag filter, and a first-order lag filter having an added value of each output of the parallel circuit as an input. A drive circuit for a brushless motor, which is a series circuit and is provided with a speed error compensation filter that uses the added first-order delay output as a current command value to the armature winding. 25. Speed detection means for detecting the speed at which the rotor is rotating, speed error detection means for outputting a difference between the detected actual rotation speed of the rotor and a target rotation speed as a speed error signal, The detected speed error signal is input, and its configuration is a parallel circuit of a series circuit of a proportional / integral (PI) filter and a first-order lag filter, and a first-order lag filter provided separately from the series circuit, A drive circuit for a brushless motor, comprising a speed error compensation filter that uses the added value of each output of the parallel circuit as a current command value to the armature winding. 26. A speed detecting means for detecting a speed at which the rotor is rotating, and a speed error detecting means for outputting a difference between the detected actual rotating speed of the rotor and a target rotating speed as a speed error signal. A speed error compensation filter that obtains a current command value to the armature winding from the detected speed error signal, and a target rotation speed of the speed error detection means according to the command rotation speed to the brushless motor drive circuit, A drive circuit for a brushless motor configured to change the gain of the speed error compensation filter. 27. A rotor position detecting means for detecting a relative position between the armature winding and the rotor, a commutation control means for switching an energized phase at the detected rotor position, and a speed at which the rotor is rotating. A speed error detecting means for detecting the difference between the detected actual rotation speed of the rotor and the target rotation speed as a speed error signal, and a speed error signal from the detected speed error signal to the armature winding. A brushless motor drive circuit, comprising: a speed error compensation filter for obtaining a current command value, wherein the commutation control means switches the conduction phase to increase or decrease the current command value to the armature winding after a fixed time. 28. The drive circuit for a brushless motor according to claim 1, wherein a maximum current is applied to the armature winding during start-up and restart. 29. Rotor position signal generating means for detecting a rotor position signal from the phase terminal potentials of the plurality of phases or voltage differences between the phases, and rising and falling edges of the rotor position signal of the output. A pulse generating means for selecting a necessary edge signal from the detected edge signals to give an output pulse train, and a pseudo pulse train when the necessary edge signal is not obtained for a predetermined time, and a counter for counting the output of the pulse generating means. And a drive circuit for a brushless motor, which drives the armature winding by applying the counter output. 30. A rotor position detected by rotor position signal detecting means including a phase terminal potential or phase difference voltage difference correcting means and a comparing means for comparing the magnitude of the output phase terminal potential or phase difference A commutation circuit that obtains an armature winding drive signal from a signal, and a trapezoidal drive signal generation circuit that processes the commutation circuit output into a trapezoidal drive signal, and supplies the trapezoidal drive signal to the armature winding. The method according to claim 1, wherein
Alternatively, the brushless motor drive circuit according to claim 2. 31. A trapezoidal drive signal generating circuit is provided with a charging / discharging circuit, and the time constant of the charging / discharging circuit is changed by an external control signal to change the slope of the trapezoidal driving signal. The drive circuit for the brushless motor according to claim 30. 32. A phase advance circuit for advancing the phase of the rotor position signal is provided, and the phase advance amount of the phase advance circuit is set to be approximately ½ of the gradient time of the trapezoidal drive signal for driving the armature winding. 31. The brushless motor drive circuit according to claim 30.