JPH08130740A - Picture decoder - Google Patents

Abstract

PURPOSE: To reduce memories required for a decoding processing and to make a picture decoder low in cost. CONSTITUTION: The inputted encoded data of B pictures are supplied to a variable length decoding circuit 2 through a switch 21, also supplied to the memory 22 and stored. By circuits after the variable length decoding circuit 2, the inputted encoded data of the B pictures are decoded first. Decoded data are switched to the memories 27 and 28 for each block line through the switch 26 and stored and the data of odd numbered fields are read from the memories 27 and 28 in a display order in the first half of the display period of one frame. Decoding is performed also to the encoded data of the B pictures stored in the memory 22 and they are switched to the memories 27 and 28 for each block line and stored. The data of even numbered fields among the data stored in the memories 27 and 28 are read in the display order in the second half of the display period of one frame.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding apparatus for decoding coded data including bidirectional predictive coded data.

[0002]

2. Description of the Related Art In recent years, digital processing of images has become popular with the establishment of high-efficiency image coding technology. The high-efficiency coding technique is for coding image data at a low bit rate in order to improve the efficiency of digital transmission and recording. In this high efficiency coding,
Orthogonal transformation such as DCT (discrete cosine transformation) processing is performed in block units of m × n pixels. Orthogonal transformation is to transform an input sample value into an orthogonal component such as a spatial frequency component. This makes it possible to reduce spatial correlation components. The orthogonally transformed components are quantized to reduce the redundancy of the signal of the block.

Further, variable length coding such as Huffman coding is applied to the quantized output to further reduce the data amount. Huffman coding performs coding based on the result calculated from the statistical code amount of the quantized output, assigning short bits to data with a high appearance probability and long bits to data with a low appearance probability. The variable length coding to be assigned reduces the total amount of data.

Further, in a device for performing high efficiency coding, a hybrid system which is being studied by MPEG (Moving Picture experts group) and the like is predominant. In this method, in addition to intraframe compression for DCT processing an image within a frame, interframe compression for reducing redundancy in the time axis direction by utilizing correlation between frames is also adopted. Inter-frame compression further reduces the bit rate by obtaining the difference between the previous and next frames and encoding the difference value (prediction error) by using the property that general moving images are similar to each other. It is what makes me. In particular, motion-compensated interframe predictive coding that reduces the prediction error by predicting the motion of an image and obtaining the interframe difference is effective.

As described above, in the hybrid system, the image data of a predetermined frame and the reference image data of the frames before and after this frame are subjected to the intra-frame coding in which the image data of the predetermined frame is directly DCT processed and coded. Predictive coding in which only difference data is DCT processed and coded is adopted. The predictive coding method includes forward predictive coding for motion-compensating temporally forward reference image data to obtain a prediction error, and backward predictive coding for temporally motion-compensating backward-oriented reference image data to obtain a predictive error. There are predictive coding and bidirectional predictive coding using an average of either forward or backward or both directions in consideration of coding efficiency.

Since a frame coded by intra-frame coding (hereinafter referred to as I picture) is coded only by intra-frame information, it can be decoded only by single coded data. Therefore, in the MPEG standard, one I picture is inserted in a fixed cycle (for example, 12 frames) to prevent error propagation. In the MPEG standard, an inter-frame coded frame (hereinafter referred to as P picture) is obtained by forward predictive coding using this I picture. The P picture can also be obtained by performing forward predictive coding on the forward P picture. Also, a bidirectional predictive adaptive switching frame (hereinafter referred to as a B picture) is obtained by bidirectional predictive coding using either forward or backward I or P pictures in both directions.

FIG. 5 is an explanatory diagram for explaining the compression method of this system. 5A shows an input frame image, FIG. 5B shows encoded data, and FIG. 5C shows decoded data. FIG. 6 is an explanatory diagram for explaining blocking.

The frame image of frame number 0 is intra-frame coded. Using this frame image as a reference image, the frame image of frame number 3 is forward predictively encoded. The arrow in FIG. 5B indicates the prediction direction of such encoding, and the frame image of frame number 6 is also subjected to forward predictive encoding using the frame image of frame number 3 ahead as a reference image. Further, the frame images with frame numbers 1 and 2 are bidirectionally predictively coded using the frame images with frame numbers 0 and 3 as reference images. The frame images with frame numbers 4 and 5 are bidirectionally predictively coded using the frame images with frame numbers 3 and 6 as reference images.

That is, as shown in FIG. 5B, first, the image data of frame number 0 is intra-frame coded to obtain an I picture. In this case, the image data of frame number 0 is framed by a memory or the like, and as shown in FIG. 6, it is divided into blocks of 8 pixels × 8 lines, and DCT processing is performed in block units. In the figure, ODD indicated by a solid line indicates a scan line of an odd field, and E indicated by a broken line.
VEN indicates a scan line of an even field. DCT
The DCT transform coefficient obtained by the processing is quantized by using a predetermined quantized coefficient, and then variable length coding is performed to obtain coded data.

For the frame image with the frame number 1 input next, bidirectional predictive coding using the frame images with the frame numbers 0 and 3 is performed. Therefore, until the frame image with the frame number 3 is coded, it is stored in the memory. Hold. Similarly, the frame image of frame number 2 is also encoded after the frame image of frame number 3 is encoded. For the frame image of frame number 3, forward prediction coding is performed using the frame image of frame number 0 as a reference image to obtain a P picture (FIG. 5B). That is, the image data of frame number 0 is motion-compensated using the motion vector, and the difference (prediction error) between the motion-compensated reference image data and the image data of the current frame (frame of frame number 3) is subjected to DCT processing. The variable length coding after quantizing the DCT transform coefficient is the same as the intraframe coding.

Next, the already encoded frame numbers 0, 3
I and P pictures of frame numbers 1 and 2
Frame images are sequentially bidirectionally predictively encoded. In this way, two B pictures are obtained as shown in FIG. Thereafter, similarly, as shown in FIG. 5B, the frame images of frame numbers 6, 4, 5, ... Are encoded in order to obtain P picture, B picture, B picture ,.

Thus, at the time of encoding, the encoding is performed in a frame order different from the actually input frame order. At the time of decoding, it is necessary to restore the decoding order of the encoded data and output the decoded data in the order of frame numbers 0, 1, 2, .... FIG. 7 is a block diagram showing such a conventional image decoding apparatus. 8A and 8B are explanatory diagrams for explaining framing, FIG. 8A shows framing during non-interlaced scanning, and FIG. 8B shows framing during interlaced scanning.

Encoded data is supplied to the code buffer memory circuit 1. This coded data is variable-length coded after the image data or the prediction error is DCT processed and quantized in the coding order shown in FIG. The code buffer memory circuit 1 holds the input coded data, adjusts the decoding processing time and the output processing time, and outputs them to the variable length decoding circuit 2. The variable length decoding circuit 2 performs variable length decoding on the encoded data and outputs it to the inverse quantization circuit 3 and the buffer control circuit 7. The buffer control circuit 7 controls the code buffer memory circuit 1.

The output of the variable length decoding circuit 2 is an inverse quantization circuit 3
Inverse quantization by the inverse DCT circuit 4
The data is processed and returned to the data before the DCT processing on the encoding side. Now, it is assumed that an I picture which is encoded data of frame number 0 is input. In this case, the output of the inverse DCT circuit 4 is the restored image of frame number 0,
The output of the T circuit 4 is given to the frame memory 6 as it is.

The output of the inverse DCT circuit 4 is pixel data in block units, and the frame memory 6 holds pixel data for one frame. When performing non-interlaced display, as shown in FIG. 8A, the frame memory 6 arranges the outputs of the inverse DCT circuit 4 in frame order and outputs them in raster order. Further, when performing interlaced display, as shown in FIG.
The output of the CT circuit 4 is divided into data of odd fields and data of even fields, arranged, and output in raster order for each field. The output of the frame memory 6 is output as decoded data via the switch 16 (see FIG. 5).
(C)). The restored image data of frame number 0 from the inverse DCT circuit 4 is also supplied to the frame memory 12 for decoding P and B pictures.

If the DCT block is divided into blocks after being framed, assuming that non-interlaced display is performed, it is not necessary to change the pixel array in the line direction, and therefore, as a memory for changing the output order. ,
It suffices if there is a capacity for holding data for 8 lines (1 block line). However, in order to enable the interlaced display, it is necessary to separately output the data into the odd field and the even field, so that more memory is required. For this reason, in general, a frame memory is often used as a memory for changing the display order to perform framing.

Next, the P picture of frame number 3 is decoded. In this case, the output of the inverse DCT circuit 4 is a prediction error. On the other hand, the motion vector extraction circuit 8 extracts the motion vector contained in the output of the variable length decoding circuit 2 and supplies it to the motion compensation circuit 10. The motion compensation circuit 10 extracts the restored image data of the I picture from the frame memory 12. Read and perform motion compensation using the motion vector. The output of the motion compensation circuit 10 is given to the adder 5 via the switch 15. The adder 5 uses the motion-compensated restored image data of frame number 0 and the inverse DC
The restored image data of frame number 3 is obtained by adding the prediction error from the T circuit 4. This data is stored in the frame memory 11
Supply to.

Next, the B picture of frame number 1 is decoded. Also in this case, the output of the inverse DCT circuit 4 is a prediction error. The motion vector extraction circuit 8 extracts the motion vector between the image of frame number 3 and the image of frame number 1 from the variable length decoded output and supplies it to the motion compensation circuit 9, which uses the motion vector. , The restored image data of frame number 3 is motion-compensated from the frame memory 11 and output to the adder 13. The adder 13 adds the outputs of the motion compensation circuits 9 and 10 according to the prediction mode at the time of encoding, and supplies the outputs to the adder 5 via the switch 15. The adder 5 adds the output of the switch 15 to the prediction error to obtain the restored image data of the B picture of frame number 1. This image data is given to the frame memory 6 to be framed, and then output via the switch 16 (FIG. 5 (c)).

Next, the B picture of frame number 2 is decoded. Also in this case, the output of the inverse DCT circuit 4 and the output of the switch 15 are added to obtain the restored image data of the B picture of frame number 2. This image data is given to the frame memory 6 to be framed, and then output via the switch 16 (FIG. 5 (c)). Next, as shown in FIG. 5C, the restored image data of frame number 3 stored in the frame memory 11 is output as decoded data in the display order via the switch 14 and the switch 16.

After that, the same operation is repeated, and FIG.
The image data (decoded data) restored in the decoding order of is output. The decoding process and the output process are controlled in consideration of the memory overlap amount and the operating time in the system.

As described above, the P picture is decoded by using the reference image of the front frame, and the decoding requires a memory for one frame to hold the reference image.
Further, the B picture is decoded using the reference images of the front and rear frames, and a memory for two frames is required to hold these reference images. Furthermore, since the encoding process is performed in DCT block units, as described above, a memory for one frame is required to frame the output of the adder 5 to enable interlaced display or non-interlaced display. . In this case, the decoded data of the I and P pictures is stored in the frame memories 11 and 12 to be used as the reference image of the B picture, and the read from these frame memories 11 and 12 is controlled and output. The frame memories 11 and 12 can also be used for framing. However, since the decoded data of the B picture is not used for the reference image and is not stored in the frame memories 11 and 12, it is necessary to provide the frame memory 6 for framing.

[0022]

As described above, in the above-described conventional image decoding apparatus, a large number of memories are required to decode image coded data including B pictures, and the circuit scale is large. However, there is a problem in that the cost increases as the cost increases.

It is an object of the present invention to provide an image decoding apparatus capable of reducing the memory required for decoding image coded data including B pictures to reduce the circuit scale and cost. To do.

[Constitution of Invention]

According to a first aspect of the present invention, an image decoding device receives coded data including bidirectional predictive coded data using forward and backward reference images,
Decoding means for decoding input coded data in predetermined block units and outputting decoded data, storage means for holding the input bidirectional predictive coded data, and input bidirectional predictive coding Data and the bidirectional predictive coded data stored in the storage means are sequentially given to the decoding means, and control means for performing the decoding process twice for the same bidirectional predictive coded data; and the decoding The decoded data by the first decoding process for the bidirectionally predictive coded data from the means is held for at least one block line, and the decoded data of one field of the held decoded data is output in the display order. The first output means and the decoding data by the second decoding processing for the bidirectionally predictive coded data from the decoding means. Is held for at least one block line, and second output means for outputting the decoded data of the other field of the held decoded data in the display order is provided, and the present invention relates to claim 4 of the present invention. The image decoding apparatus is input with encoded data including bidirectional predictive encoded data using forward and backward reference images, decodes the input encoded data in predetermined block units, and outputs the decoded data. Decoding means, third output means for outputting the decoded data of one field out of the decoded data for the bidirectional predictive coded data from the decoding means in display order, and the bidirectional prediction from the decoding means Of the decoded data for the encoded data, the decoded data of the other field is held, and the output of the decoded data by the third output means is completed. The image decoding apparatus according to claim 6 of the present invention comprises a code including bidirectional predictive coded data using forward and backward reference pictures. Decoding means for receiving the encoded data, decoding the input encoded data in a predetermined block unit and outputting the decoded data, and first storage means for holding the input bidirectional predictive encoded data. , The input bidirectional predictive coded data and the bidirectional predictive coded data stored in the first storage means are sequentially given to the decoding means, and the same bidirectional predictive coded data is decoded twice. A control means for performing a coding process, and a second field for holding one field of the coded data by the first decoding process for the bidirectional predictive coded data from the decoding means.
Storage means, means for outputting one field stored in the second storage means in the reading and displaying order during the second encoding processing time, and second time in the area read from the second storage means. A means for sequentially storing the other field of the decoded data by the decoding processing is provided, and the decoded data of the one or the other field is output in the display order.

[0025]

According to the first aspect of the present invention, the decoding means can decode the encoded data of one image within half the display time of one image. When the bidirectional predictive coded data is input, the storage means stores the bidirectional predictive coded data. The input bidirectional predictive coded data is given to the decoding means to perform the first decoding process. The decoded data from the decoding means is given to the first output means and held for one block line. The first output means outputs the decoded data of one field of the held decoded data in the display order. On the other hand, when the first decoding processing for the bidirectional predictive coded data is completed, the control means gives the bidirectional predictive coded data stored in the storage means to the decoding means for decoding. The second output means holds the decoded data by the second decoding processing for one block line and outputs the decoded data of the other field in the display order.

In claim 4 of the present invention, the decoding means can decode the encoded data of one image within half the display time of one image. The decoded data for the bidirectional predictive coded data from the decoding means is given to the third and fourth output means. The third output means outputs the decoded data of one field of the decoded data for the bidirectional predictive encoded data in the display order. The fourth output means stores the decoded data of the other field of the input decoded data, and when the output of the decoded data by the third output means ends, the stored other field of the decoded data is decoded. Output the data in display order.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an image decoding apparatus according to the present invention. 1, the same components as those in FIG. 7 are designated by the same reference numerals. In the present embodiment, the encoded data is decoded and the decoded data is output in the display order of interlaced display.

The coded data is the code buffer memory circuit 1
Supply to. This coded data is created by DCT processing, quantization processing, and variable length coding processing, and includes I-pictures by intra-frame processing, P-pictures using reference images of forward or backward frames, and bidirectional frames. It has a B picture using a reference image. The encoded data also includes information on the motion vector used when creating the P and B pictures. It should be noted that the DCT processing is performed on a block-by-block basis obtained by dividing the frame into blocks.

The code buffer memory circuit 1 holds the input coded data, and outputs it after adjusting the decoding processing time and the output processing time. In this embodiment,
The output of the code buffer memory circuit 1 is supplied to the terminal a of the switch 21, the memory 22 and the picture detection circuit 23. The picture detection circuit 23 detects the picture type of the input encoded data and outputs a detection signal to the buffer control circuit 24.

The buffer control circuit 24 controls the code buffer memory circuit 1 based on the detection signal. When the detection signal indicates that the B picture is input, the buffer control circuit 24 generates a write address for storing the encoded data of the input B picture in the memory 22. The switch 21 selects the terminal a and supplies the output of the code buffer memory circuit 1 to the variable length decoding circuit 2. When the decoding of the B picture from the code buffer memory circuit 1 is completed, the buffer control circuit 24 gives a read address to the memory 22 and switches it.
B stored in the memory 22 by causing the terminal 21 to select the terminal b
The encoded data of a picture is supplied to the variable length decoding circuit 2. The buffer control circuit 24 causes the switch 21 to select the terminal a when the input coded data is an I or P picture. The memory 22 stores encoded data of B picture.
It should be noted that the code amount of the B picture is sufficiently smaller than the code amount of the I picture, and the capacity of the frame memory for holding the pixel data is about 1/4.

The variable length decoding circuit 2 receives the encoded data through the switch 21 and returns it to the data before the variable length encoding process on the encoding side by the variable length decoding process, and the inverse quantization circuit 3 and Output to the motion vector extraction circuit 8. For the P and B pictures, the motion vector extraction circuit 8 extracts the motion vector included in the variable length decoded output and outputs it to the motion compensation circuits 9 and 10. The inverse quantization circuit 3 inversely quantizes the input data and gives it to the inverse DCT circuit 4,
The T circuit 4 performs inverse DCT processing on the inverse quantized output and outputs it to the adder 5.

The output of the switch 15 is also given to the adder 5.
The switch 15 gives 0 to the adder 5 when the output of the inverse DCT circuit 4 is based on the I picture, and when one of the motion compensation circuits 9 and 10 described later is based on the P picture. The output is given to the adder 5, and when it is based on the B picture, the output of the motion compensation circuits 9 and 10 or the adder 13 described later is given to the adder 5. Adder 5 is inverse D
The image is restored by adding the output of the CT circuit 4 and the output of the switch 15, and the image is output to the frame memories 11 and 12, and at the same time, the memories 27 and 28 are output via the switch 26 of the output unit 25.
Output to.

The outputs of the memories 27 and 28 are output to the switch 16 via the switches 29 and 20. The switches 26 and 29 are interlocked with each other, and when the memory 27 is being written via the switch 26, the data is read from the memory 28 via the switch 29 and the data is written into the memory 28. If it is open, the data is read from the memory 27. The memories 27 and 28 have a capacity for holding pixel data of one block line.

The frame memories 11 and 12 hold restored image data of I and P pictures as reference images. The frame memories 11 and 12 store the reference image data held at the corresponding P and B picture decoding timings in the motion compensation circuits 9 and 10.
Output. The motion compensating circuits 9 and 10 perform motion compensation on the reference image data from the frame memories 11 and 12 based on the motion vector from the motion vector extracting circuit 8 and output the result. The outputs of the motion compensation circuits 9 and 10 are switches
It is supplied to 15 as well as to the adder 13. Adder 13
Is configured to add the outputs of the motion compensation circuits 9 and 10 according to the prediction mode and output the result to the switch 15.

Further, the switch 14 switches in accordance with the image output frame order and outputs the restored image data stored in the frame memories 11 and 12 to the switch 16. switch
Reference numeral 16 switches in accordance with the output frame order of the image, and outputs the restored image data of a series of frames as decoded data.

In this embodiment, the variable length decoding circuit 2,
Inverse quantization circuit 3, inverse DCT circuit 4, adder 5, motion vector extraction circuit 8, motion compensation circuits 9 and 10, frame memory
11, 12 and the adder 13 and the switch 15 can perform the decoding process twice for the B picture within the image display time of one frame. For example, for NTSC images, the sampling frequency is typically 13.5.
It is set to MHz. Therefore, when decoding the encoded data of the NTSC image, the decoding process may be performed by using the clock of 27 MHz. Considering the operation speed of the present integrated circuit, these circuits used for the decoding process are It may be the same as the conventional one.

Next, the operation of the embodiment thus constructed will be described with reference to FIG. FIG. 2 is an explanatory diagram for explaining writing and reading of the memories 27 and 28 in FIG. 2A and 2B show writing and reading at the first decoding, and FIGS. 2C and 2D show writing and reading at the second decoding, respectively. In addition,
In FIG. 2, the odd field data is shown by a solid line,
The data of the even-numbered fields are shown by broken lines.

The encoded data is the code buffer memory circuit 1.
Supply to. The encoded data has I, P, and B pictures, and is input in the frame order of FIG. 5B, for example. The code buffer memory circuit 1 holds the input coded data in consideration of the coding processing time and the output time and outputs the coded data to the terminal a of the switch 21 and the picture detection circuit 23. First, as shown in FIG. 5B, it is assumed that the encoded data of the I picture of frame number 0 is input. The picture detection circuit 23 detects that it is an I picture and outputs a detection signal to the buffer control circuit 24. As a result, the buffer control circuit 24 controls the code buffer memory circuit 1 and causes the switch 21 to select the terminal a.

The coded data of the I picture delayed by the code buffer memory circuit 1 is given to the variable length decoding circuit 2 via the switch 21 to be variable length decoded. Further, the inverse quantization circuit 3 performs inverse quantization, the inverse DCT circuit 4 performs inverse DCT processing, restores the data before DCT processing on the encoding side, and outputs the data to the adder 5. In this case, the inverse DC
The output of the T circuit 4 is a restored image of frame number 0. Note that these processes are performed in block units. The switch 15 gives 0 to the adder 5, and the adder 5 receives the inverse DCT circuit 4
The output of is directly given to the frame memory 12.

The frame memory 12 stores the decoded data of each block for one frame, and at predetermined output timing, the decoded data is read in the display order and output via the switches 14 and 16.

Next, coded data of the P picture of frame number 3 is input to the code buffer memory circuit 1. The picture detection circuit 3 outputs a detection signal indicating that a P picture is input to the buffer control circuit 24, and the buffer control circuit 24 causes the switch 21 to select the terminal a.
The coded data of the P picture delayed by the code buffer memory circuit 1 for a predetermined time is supplied to the variable length decoding circuit 2 via the switch 21 and variable length decoding is performed. The output of the variable length decoding circuit 2 is returned to the data before DCT processing by the inverse quantization circuit 3 and the inverse DCT circuit 4, and is also given to the motion vector extraction circuit 8. By the motion vector extraction circuit 8,
The motion vector included in the encoded data of the P picture is extracted and given to the motion compensation circuit 10.

The frame memory 12 holds the decoded data of the I picture of frame number 0 as a reference image,
The motion compensation circuit 10 reads the data in the frame memory 12 and compensates for motion using the motion vector. This motion-compensated reference image data is added via the switch 15 to the adder 5
Give to. The output of the inverse DCT circuit 4 is the decoded prediction error, and the adder 5 adds the data of the reference image from the switch 15 to this prediction error to obtain the frame number 3
Restore the image data of. This image data is stored in the frame memory 11.

Next, the code buffer memory circuit 1 is supplied with the coded data of the B picture of frame number 1. The picture detection circuit 23 outputs a detection signal indicating that the encoded data of the B picture has been input to the buffer control circuit 24. Then, the buffer control circuit 24 outputs the encoded data of the B picture from the code buffer memory circuit 1 to the variable length decoding circuit 2 via the switch 21 and also supplies it to the memory 22 for storage.

In this embodiment, the decoding process is performed twice for the B picture within the image display period of one frame. The variable length decoding circuit 2 performs variable length decoding on the coded data of the B picture and restores the original pixel data by the inverse quantization circuit 3 and the inverse DCT circuit 4. On the other hand, the motion vector extraction circuit 8 extracts the motion vector corresponding to the reference image of the frame numbers 0 and 3 from the variable length decoding output, and the motion vector extraction circuit 8 respectively extracts the motion vector.
Output to 10 and 9. Depending on the prediction mode, only one of the motion vectors may be extracted.

The frame memories 12 and 11 hold the restored image data of frame numbers 0 and 3 respectively as reference image data, and the motion compensation circuits 9 and 10 read these restored image data and based on the motion vector. The motion is compensated and output to the switch 15 and the adder 13. That is, the motion compensating circuits 9 and 10 correct the blocking position corresponding to the decoded data of the predetermined block output from the inverse DCT circuit 4 by the motion vector, and motion-compensate the block data at the corrected blocking position. Output as reference image data. The adder 13 adds the outputs of the motion compensation circuits 9 and 10 and outputs the result to the switch 15. The switch 15 selects the output of the motion compensation circuit 10 when the prediction direction is forward, selects the output of the motion compensation circuit 9 when the prediction direction is backward, and the output of the adder 13 when the prediction direction is bidirectional. Is output to the adder 5 as motion-compensated reference image data.

In this way, the adder 5 restores the image data of the frame number 1 in each block unit by adding the block data from the inverse DCT circuit 4 and the reference image data of the block unit from the switch 15 to the switch unit. Output to 26. The switches 26 and 29 are switched for each block line.

That is, the block data from the adder 5 is 1
The memories 27 and 28 are switched and recorded for each block line.
Further, reading from the memories 27 and 28 is switched at the same time as writing. For example, as shown in FIG. 2A, when the data of the first block line at the top of the screen is written in the memory 27, the next one block line (second block line) from the adder 5 Each block data is written in the memory 28. Simultaneously with the writing of the block data of the second block line to the memory 28, the data of the odd field of the first block line is read from the memory 27 in the order of display and is output via the switch 29. Similarly, each block data of the third block line from the adder 5 is written into the memory 27, and at the same time, the data of the odd field of the second block line is read out from the memory 28 in the display order and output through the switch 29. .

After that, the same operation is repeated to switch the decoded data of the odd field as shown in FIG. 2 (b).
Outputs in order of display via 29 and 16. As described above, the decoding process of the B picture can be performed within half the display time of one frame, and the decoded data of the odd field is output in one field time. In this way, the image data of the odd field of the interlaced display is obtained.

On the other hand, when the first decoding process for the B picture of frame number 1 is completed, the buffer control circuit 24 causes the switch 21 to select the terminal b and the B of frame number 1 stored in the memory 22. The encoded data of the picture is given to the variable length decoding circuit 2. In this case, the same processing as the first decoding processing is performed, and the adder 5 sequentially outputs the decoded data of the B picture of frame number 1 in block units.

Each block data of the first block line from the adder 5 has a switch 26 as shown in FIG.
Are sequentially written to the memory 27 via. Each block data of the next second block line is sequentially written into the memory 28, and at the same time as this writing, the pixel data of the even field of the first block line from the memory 27 is sequentially read out in the display order. After that, the same operation is repeated to read out the pixel data of the even field in the display order as shown in FIG.
Output through 16. The output of the decoded data of the even field is performed in the half time of the latter half of the display time of one frame. Thus, the decoded data of the even field of the interlaced display is obtained.

Next, with respect to the coded data of the B picture of frame number 2, the coding process is performed twice in the display period of one frame, and the decoded data is output in the odd field and the even field. . Next, the restored image data of frame number 3 stored in the frame memory 11 is read in the order of display and output via the switches 14 and 16. After that, by repeating the same operation, as shown in FIG.
Get the decrypted data of.

As described above, in this embodiment, the decoding process of the B picture is performed twice within the image display time of one frame, and the block data obtained by the first decoding process is memorized for each one block line. Stored in the memory and read only the odd field data in the order of display,
Get the decoded data of the interlaced odd fields,
Similarly, the block data obtained by the second decoding process is stored in the memory one block line at a time, and only the even field data is read in the display order to obtain the interlaced even field decoded data. Therefore, the memories 27 and 28 only need to have a capacity for one block line. That is, the memories 22 and 2
The total capacity of 7, 28 may be relatively small, and the memory capacity required for decoding can be reduced as compared with the conventional one. As a result, the circuit scale can be reduced and the cost can be reduced.

In this embodiment, in order to clarify the operation of decoding the B picture twice, the code buffer memory circuit 1 which holds the input coded data and the coded data of the B picture are stored. Although the memory 22 has been described as another memory, since the input B-picture encoded data is held once in the code buffer memory circuit 1, the present embodiment may be realized by reading this out twice. It is possible.

In this embodiment, the memories 27 and 28 have a capacity for holding pixel data of one block line. Therefore, it is necessary to finish the decoding of the coded image within one block line time.

By the way, since the encoded data has a variable length, there are blocks having a large code amount and blocks having a small code amount.
Therefore, in a block line having a large code amount, depending on the memory used, the decoding end processing time may not be settled within one block line time depending on the memory access time.

Therefore, for example, the memory 27 and the memory 28 are replaced with one field memory, and the B picture 1
During the second decoding process, one field of the decoded data is held in this field memory, and during the second decoding process, the one field that was held during the first decoding is read out and output while being output in the display order. If the method of outputting the decoded data of one and the other fields in the display order by sequentially holding the other field of the decoded data obtained by the second decoding processing in the area It can be secured for a long time.

According to this method, the memory capacity is larger than that described in the embodiment, but it is possible to solve the problem of the decoding processing time due to the memory access speed and reduce the memory capacity as compared with the conventional example. .

FIG. 3 is a block diagram showing another embodiment of the present invention. In FIG. 3, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, the switch 21, the memory 22, the picture detection circuit 23, and the buffer control circuit 24 are deleted to employ the buffer control circuit 7, and the output unit 31 is used instead of the output unit 25. 1 is different from the first embodiment. The output of the code buffer memory circuit 1 is given to the variable length decoding circuit 2, and the output of the variable length decoding circuit 2 is given to the buffer control circuit 7. The buffer control circuit 7 controls the code buffer memory circuit 1 based on the variable length decoded output from the variable length decoding circuit 2.

The output unit 31 includes switches 32 and 33 and memories 34 and 35.
And the field memory 36. When the block data of the odd-numbered horizontal block is output from the adder 5, the switch 32 alternately selects the memory 34 or the field memory 36, and the adder 5 outputs the block data of the even-numbered horizontal block. Memory if
35 or the field memory 36 is selected alternately. switch
In the block data 36, the odd field data of the block data is given to the memories 35 and 36, and the even field data is given to the field memory 36. Memory 34, 35
Is designed to store data for one block line. The field memory 36 is adapted to store even field data. In the odd field, the switch 33 selects the memory 35 when the switch 32 alternately selects the memory 34 or the field memory 36, and when the switch 32 alternately selects the memory 35 or the field memory 36. To select the memory 34. The switch 33 selects the output of the field memory 36 during the display time of even fields.

In the present embodiment, it is necessary to carry out the decoding process for the B picture within half the image display time of one frame as in the embodiment of FIG. Only one treatment is required.

Next, the operation of the embodiment thus constructed will be described with reference to FIG. FIG. 4 is an explanatory diagram for explaining writing and reading of the memories 34 and 35 and the field memory 36 in FIG. FIG. 4A shows writing of block data, and FIGS. 4B and 4C show reading of decoded data in an odd field and an even field, respectively. In FIG. 4, the data in the odd field is shown by a solid line, and the data in the even field is shown by a broken line.

Encoding data similar to that of the embodiment of FIG. 1 is given to the encoding buffer memory circuit 1. The encoding buffer memory circuit 1 is controlled by the buffer control circuit 7, delays the input encoded data by a delay amount based on the encoding processing time and the output time, and outputs the delayed encoded data to the variable length decoding circuit 2. The decoding process after the variable length decoding circuit 2 is the same as that of the embodiment of FIG. Further, the decoding process is performed on the encoded data of the B picture within half the image display time of one frame, as in the embodiment of FIG.

In this embodiment, the decoded data of the B picture is supplied from the adder 5 to the output unit 31. Now, it is assumed that the adder 5 supplies the decoded data of the first block line of the B picture to the switch 32 in block units. In this case, the switch 32, as shown in FIG.
Of each block data, odd field data is written in the memory 34, and even field data is written in the field memory 36. Thus, only the decoded data of the odd field of the first block line is stored in the memory 34. Further, the field memory 36 stores the decoded data of the even field of the first block line.

Next, the adder 5 outputs the encoded data of the second block line in block units. In this case,
The switch 32 writes the odd field data of each block data in the memory 35, and additionally writes the even field data in the field memory 36. Thus, the memory 35 stores only the decoded data of the odd field of the second block line. Further, the field memory 36 stores the decoded data of the even field of the first block line and the decoded data of the even field of the second block line. Also, during this period,
The switch 33 selects the memory 34. As a result, the data of the odd field of the first block line stored in the memory 34 is read out in the display order and output through the switch 16.

Next, the adder 5 outputs the coded data of the third block line in block units. In this case, the switch 32 writes the odd field data of each block data in the memory 34, and additionally writes the even field data in the field memory 36. Further, the switch 33 selects the memory 35, reads the data of the odd field of the second block line stored in the memory 35 in the order of display, and outputs the data from the switch 16. Only the odd field decoded data of the third block line is stored in the memory 34, and the field memory 36 follows the even field decoded data of the first and second block lines and the even block of the third block line. Stores the decrypted data of the field.

Thereafter, the same operation is repeated, and in the first half period of the image display period of one frame, as shown in FIG. 4B, the decoded data of the odd fields is read out and output from the memories 34 and 35. . Further, during this period, the field memory 36 stores all the decoded data of the even field.

In the latter half of the one-frame image display period, the switch 33 selects the field memory 36. As a result, as shown in FIG. 4C, the even field decoded data stored in the field memory 36 is read out in the order of display and output from the switch 16. In this way, interlaced display is possible.

As described above, in this embodiment, in the first half of the display period of one frame, the decoded data of the odd fields of the block data are stored in the memories 34 and 35 and read out to read the decoded data of the odd fields. To get Then, during this period, the decoded data of the even field is stored in the field memory 36. In the even field, the data stored in the field memory 36 is read in the display order to obtain the decoded data of the even field.

The memory capacities of the memories 34, 35 and 36 are relatively small, and in this embodiment as well, it is possible to reduce the memory capacity, reduce the circuit scale, and reduce the cost.

Although a plurality of memories are used in each of the above embodiments, it is obvious that the area of one memory may be divided into a plurality of areas and used instead of the respective memories.

[0072]

As described above, according to the present invention, B
It is possible to reduce the memory required for decoding image coded data including a picture, reduce the circuit scale, and reduce the cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image decoding apparatus according to the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is an explanatory diagram for explaining the operation of the embodiment of FIG.

FIG. 5 is an explanatory diagram for explaining a hybrid compression method.

FIG. 6 is an explanatory diagram for explaining blocking.

FIG. 7 is a block diagram showing a conventional image decoding device.

FIG. 8 is an explanatory diagram for explaining framing.

[Explanation of symbols]

2 ... Variable length decoding circuit, 3 ... Inverse quantization circuit, 4 ... Inverse DCT
Circuits, 5, 13 ... Adder, 8 ... Motion vector extraction circuit,
9, 10 ... Motion compensation circuit, 11, 12 ... Frame memory, 14-
16, 21, 26, 29 ... Switch, 22, 27, 28 ... Memory, 23 ...
Picture detection circuit

Claims (6)

[Claims] 1. Decoding for receiving encoded data including bidirectional predictive encoded data using forward and backward reference images, decoding the input encoded data in predetermined block units, and outputting the decoded data. Encoding means, storage means for holding the inputted bidirectional predictive encoded data, input bidirectional predictive encoded data and the bidirectional predictive encoded data stored in the storing means to the decoding means in order. And a control means for performing the same decoding processing on the same bidirectional predictive encoded data twice, and decoded data by the first decoding processing on the bidirectional predictive encoded data from the decoding means. A first output unit that holds at least one block line and outputs the decoded data of one field of the held decoded data in the display order. And at least one block line of decoded data obtained by the second decoding process for the bidirectionally predictive coded data from the decoding means, and decoding the other field of the held decoded data. An image decoding apparatus comprising: a second output unit that outputs data in a display order. 2. The first and second output means are respectively 1
The image decoding apparatus according to claim 1, wherein the decoded data is output in half the image display time of a frame. 3. The first and second output means have first and second memories that hold decoded data for one block line, and write and read to and from the first and second memories. The image decoding apparatus according to claim 1, wherein the decoded data of one field or the other field is output in the display order by controlling the. 4. Decoding in which encoded data including bidirectional predictive encoded data using forward and backward reference images is input, and the input encoded data is decoded in predetermined block units and decoded data is output. Encoding means, third output means for outputting the decoded data of one field of the decoded data for the bidirectional predictive coded data from the decoding means in display order, and the bidirectional predictive code from the decoding means A fourth output means for holding the decoded data of the other field of the decoded data for the encrypted data and outputting the decoded data by the third output means in the display order after the output of the decoded data by the third output means is completed. Image decoding device. 5. The fourth output means is constituted by a field memory that holds decoded data of the other field of the decoded data for the bidirectional predictive coded data, and the third output means is one block. A third and a fourth memory for holding the decoded data for the line, and the third memory
And controlling the writing and reading of the fourth memory to hold the decoded data of one field of the decoded data for the bidirectional predictive coded data and output the decoded data in the display order. The image decoding device described. 6. Decoding in which coded data including bidirectional predictive coded data using forward and backward reference images is input, the input coded data is decoded in predetermined block units, and the decoded data is output. And a first holding means for holding the input bidirectional predictive encoded data.
And the input bidirectional predictive coded data and the bidirectional predictive coded data stored in the first storage means are sequentially given to the decoding means to obtain the same bidirectional predictive coded data. Control means for performing the decoding process twice, and second storage means for holding one field of the encoded data by the first decoding process for the bidirectionally predictive encoded data from the decoding means. And means for outputting one of the fields stored in the second storage means in the order of reading and displaying during the second encoding processing time, and the second decoding processing for the area read from the second storage means. Means for sequentially storing the other field of the decoded data, and outputting the decoded data of the one or the other field in display order. Image decoding apparatus.