JPH08130519A - Stereo demodulation circuit - Google Patents

Abstract

PURPOSE: To prevent the generation of a DC component in an output signal from a polar modulation type stereo modulation circuit. CONSTITUTION: A subcarrier signal reproduced from a composite signal by a PLL circuit 3 is impressed to a cancel signal generating circuit 9 and a subcarrier canceling signal is generated from the circuit 9. The subcarrier canceling signal is added to the composite signal by a 1st adder circuit 10, and output signal from the 1st adder circuit 10 is stereo-modulated by a stereo decoder 2 based upon the subcarrier signal. Since the subcarrier signal is canceled before the stereo-modulation, a DC component in an output signal from the decoder 2 can be removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a stereo demodulation circuit for stereo demodulating a signal modulated by a polar modulation method.

[0002]

2. Description of the Related Art As one of FM stereo broadcasts, a polar modulation system is known. FM stereo broadcasting by this method is still in practical use in some regions of the world even today. In the polar modulation method, a main channel signal composed of a stereo sum signal (L + R) and 3
Stereo difference signal (LR) with 1.25 kHz subcarrier
The main carrier is FM-modulated and transmitted by a signal (composite signal) obtained by superimposing the sub-channel signal amplitude-modulated in (1). The transmission signal modulated by the polar modulation method is FM
After it is received by the receiver and FM detected, it is applied to a stereo demodulation circuit as shown in FIG. 2 and stereo demodulated.

In FIG. 2, the composite signal detected by the FM detection circuit (not shown) in the preceding stage is applied to the stereo decoder (2) via the buffer circuit (1a). Further, the composite signal is applied to the PLL circuit (3) via the buffer circuit (1b), and the subcarrier frequency included in the composite signal is reproduced. Further, the composite signal is applied to the synchronous detection circuit (4) via the buffer circuit (1c) and is synchronously detected by the subcarrier signal. Since a subcarrier signal exists at the time of receiving a stereo broadcast, an output signal is generated from the synchronous detection circuit (4) and smoothed by the low pass filter (5). The output signal of the low-pass filter (5) is applied to the trigger generation circuit (6), and the trigger generation circuit (6) generates a trigger signal corresponding to the output signal. Then, the switch (7) is turned on by the trigger signal, and the subcarrier signal from the PLL circuit (3) is applied to the stereo decoder (2). After that, the stereo decoder (2) stereo demodulates the composite signal, and the stereo decoder (2) generates a left audio output signal (L signal) and a right audio output signal (R signal).

Further, during monaural broadcasting, since the subcarrier signal does not exist, the synchronous detection circuit (4) does not generate an output signal, and therefore, does not generate a trigger signal. For that reason,
The switch (7) is turned off, the stereo decoder (2) does not perform stereo demodulation of the composite signal, the input composite signal is generated as it is at the output terminal, and monaural reception is performed.

By the way, the polar modulation type composite signal is

[0006]

[Equation 1]

Therefore, the subcarrier signal reproduced from the composite signal in the PLL circuit (3) becomes sinωt. In the stereo decoder (2), when this composite signal and the subcarrier signal are multiplied,

[0008]

[Equation 2]

A signal of ## EQU1 ## is obtained, and further, by decoding (1 + LR) in the equation (2), L and R are obtained.
The signal is obtained.

[0010]

However, in stereo, as a result of multiplication of the composite signal and the subcarrier signal, a DC component is generated in addition to the (LR) signal component as shown in equation (2). On the other hand, since there is no DC component other than the audio signal in monaural, there is a problem that a DC fluctuation occurs in the output signal of the stereo decoder (2) at the time of switching the monaural or stereo operation, and a shock sound is generated.

Further, when the stereo decoder (2) operates in stereo, the composite signal is decoded to obtain L and R signals.
When separated into signals, the DC component in equation (2) gives
There has been a problem that a difference occurs in the bias between the L and R signals and the dynamic range of the L and R signals becomes unbalanced. Further, in order to obtain a signal for stereo broadcast identification and stereo operation switching, it is necessary to synchronously detect and smooth the subcarrier in the composite signal and the reproduced subcarrier signal. However, the synchronous detection circuit (4) Since the output signal of (1) is as shown in equation (2), it is necessary to sufficiently remove the low frequency component and the beat component in the output signal of the synchronous detection circuit (4) so that the stereo operation switching does not malfunction. For that purpose, the cut-off frequency of the low-pass filter (5) must be set to several Hz or less, and the capacitor (8) constituting the low-pass filter has a large capacity, which is particularly unsuitable for IC implementation.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and a PLL circuit for reproducing a subcarrier frequency from a composite signal, and the composite signal according to an output signal of the PLL circuit. A stereo decoder for decoding, a synchronous detection circuit for synchronously detecting the composite signal and the output signal of the PLL circuit, and a low-pass filter for smoothing the output signal of the synchronous detection circuit,
A polar demodulation stereo demodulation circuit comprising a switch for conducting or blocking an output signal of a PLL circuit applied to the stereo decoder according to an output signal of the low-pass filter, wherein a sub-carrier wave is generated according to an output signal of the PLL circuit. A cancel signal generating circuit for generating a cancel signal and a first adding circuit for adding the subcarrier cancel signal to the composite signal are provided.

Further, the present invention is characterized by comprising a removing circuit for removing a low frequency component in the output signal of the synchronous detection circuit according to the output signal of the stereo decoder. Furthermore, an inverting circuit that inverts the left audio output signal of the stereo decoder, a second adding circuit that adds the output signal of the inverting circuit and the right audio output signal of the stereo decoder, the synchronous detection circuit, and a low-pass filter. And a third adder circuit connected between the output signal of the synchronous detection circuit and the output signal of the second adder circuit.

Furthermore, in the stereo decoder, output terminals of left and right audio output signals applied to a circuit subsequent to the stereo demodulation circuit and left and right audio output signals applied to the cancel circuit are generated. It is characterized in that the output terminals of the stereo decoder are different. Furthermore, a comparison circuit for comparing the DC components of the left and right audio output signals of the stereo decoder, and a variable circuit for varying the level of the subcarrier cancellation signal according to the output signal of the comparison circuit are provided. Is characterized by.

[0015]

According to the present invention, the PLL is converted from the composite signal.
The signal having the subcarrier frequency reproduced by the circuit is applied to the cancel signal generating circuit, and the cancel generating circuit generates the subcarrier cancel signal. The sub-carrier cancel signal is added to the composite signal by the first adder circuit, and the output signal of the first adder circuit is stereo-demodulated by the sub-carrier signal by the stereo decoder. By canceling the subcarrier signal before stereo demodulation in this way, it is possible to remove the DC component in the output signal of the stereo decoder.

Further, the left audio signal generated from the stereo decoder is inverted by the inverting circuit, the right audio signal generated from the stereo decoder and the output signal of the inverting circuit are added by the second adding circuit, and further, the synchronous detection circuit. By adding the output signal and the output signal of the second adding circuit, the low frequency component in the output signal of the synchronous detection circuit is removed. Therefore, the cutoff frequency of the low-pass filter can be set to a low frequency band, and the capacity of the capacitor that constitutes the low-pass filter can be reduced.

[0017]

1 is a circuit diagram showing an embodiment of the present invention. (9) is a cancel signal generating circuit for generating a subcarrier cancel signal in response to a subcarrier signal, and (10) is a composite signal and a subsignal. A first adder circuit for adding the carrier cancel signal, (11) a first amplifier for inverting and amplifying the left output signal of the stereo decoder (2), and (12) a first amplifier for amplifying the right output signal of the stereo decoder (2). 2 amps,
(13) is a first amplifier (11) and a second amplifier (12)
Is a second adder circuit for adding the output signals of, and (14) is a third adder circuit for adding the output signals of the second adder circuit (13) and the synchronous detection circuit (4). The same circuits as those of the related art will be denoted by the same reference numerals as those of the related art, and description thereof will be omitted.

In FIG. 1, since the composite signal applied to the input terminal (15) is modulated by the polar modulation method, it is expressed by the equation (1). The composite signal is applied to the PLL circuit (3) via the buffer circuit (1b). The PLL circuit (3) locks to the subcarrier signal in the composite signal, and the subcarrier signal sin
Play ωt. The reproduced sub-carrier signal is applied to the cancel signal generation circuit (9), and a sub-carrier cancel signal (-1 x sinωt) corresponding to the sub-carrier signal is created. The subcarrier cancel signal is sent to the first adder circuit (1
0) is added to the composite signal applied to the first adder circuit (10) via the buffer circuit (1a). Therefore, the output signal of the first addition circuit (10) is

[0019]

(Equation 3)

And is applied to the stereo decoder (2). In addition, the composite signal is a buffer circuit (1
Since it is applied to the synchronous detection circuit (4) via c) and is synchronously detected by the subcarrier signal from the PLL circuit (3), the output signal of the synchronous detection circuit (4) is as in equation (2). . The output signal of the synchronous detection circuit (4) is added to the output signal of the second addition circuit (13) described later in the third addition circuit (14) and applied to the low pass filter (5). Then, a trigger signal is generated from the trigger generation circuit (6) in response to the output signal of the low pass filter (5), and the switch (7) is turned on by the trigger signal, that is, the illustrated state. Therefore, the subcarrier signal generated from the PLL circuit (3) is applied to the stereo decoder (2) via the switch (7).

In the stereo decoder (2), the output signal of the first adder circuit (10) represented by the equation (3) and P
The output signal of the LL circuit (3) is multiplied,

[0022]

[Equation 4]

The following signal is generated. Then, the formula (4)
By decoding (LR) / 2 of
Separated into signals. The L and R signals generated from the stereo decoder (2) are stored in capacitors (16) and (17).
Then de-emphasis is applied. Here, in the first adder circuit (10), the subcarrier signal component sin
Since ωt is not included, no DC component appears in the L and R signals.

Further, the condensers (16) and (17)
The L and R signals are applied to the first and second amplifiers (11) and (12) from the other output end of the stereo decoder (2) different from the output end that generates the L and R signals applied to the. . The L signal is amplified by the first amplifier (11) with an amplification factor of -1/2 and then applied to the second addition circuit (13), and the R signal is amplified by the second amplifier (12) with a gain factor of 1/2. After being amplified by, it is applied to the second adder circuit (13). Therefore, the output signal of the second addition circuit (13) is
(-L + R) / 2, which is applied to the third adder circuit (14). In the third adder circuit (14), the output signal of the synchronous detection circuit (4) and the output signal of the second adder circuit (13) are added, and the added signal is given by the equation (2):

[0025]

(Equation 5)

[0026] From the equation (5), the third addition circuit (1
The output signal of 4) is only DC component and beat component,
The cutoff frequency of the low pass filter (5) can be set to the audio signal component band. Therefore, the capacity of the capacitor (18) that constitutes the low pass filter (5) can be reduced. In addition, stereo decoder (2)
Since the left and right output signals of are not de-emphasized, they have the same frequency characteristics as the left and right audio signal components in the composite signal, and the DC component in the output signal of the stereo decoder (2). Is not included in the output signal of the synchronous detection circuit (4) (L-
The R) component can be reliably removed.

Further, in FIG. 1, the L and R signals generated from the stereo decoder (2) are respectively amplified by -1.
Amplify by 1/2 and 1/2, then add, (-L + R) / 2
Signal is obtained, but the amplification rate of the L and R signals is 1/2
The signal of (-L + R) / 2 may be obtained by subtracting after amplifying at. Further, the L and R signals are amplified by an amplification rate of 1/2 and then subtracted to obtain a signal of (LR) / 2. After that, a subtraction circuit is provided instead of the third addition circuit (14), The output signal of the synchronous detection circuit (4) and the signal of (LR) / 2 are subtracted to remove the (LR) component in the output signal of the synchronous detection circuit (4).

FIG. 3 shows an example of a concrete circuit of the main part of FIG.
(19) is a cancel signal generation circuit composed of a multiplication circuit including differential pairs (20), (21) and (22), and current mirror circuits (23), (24) and (25),
(26) is a stereo decoder composed of a multiplication circuit including differential pairs (27), (28) and (29), and current mirror circuits (30) and (31).

In FIG. 3, the PLL circuit (3)
The reproduced subcarrier signals Q and * Q are applied to the differential pair (20) and (21), and the reference voltage Vref applied to the differential pair (22) is divided by the resistors (32) and (33). It is multiplied by the applied voltage. The signal * Q is an inverted signal of the signal Q. The output signals of the differential pair (20) and (21) are supplied to the current mirror circuits (23) and (24), respectively. The output current of the current mirror circuit (23) is supplied to the current mirror circuit (25), and further the current mirror circuit (2
The output currents of 4) and (25) are mixed at the connection point (b) and supplied to the load resistor (34). Load resistance (34)
The signal generated from one end of the input terminal (35) is used as a subcarrier cancellation signal in the first addition circuit (10).
Is added to the composite signal applied to. The levels of the sub-carrier cancel signal are the resistances (32) and (3
It is determined by the voltage division ratio of 3), the value of the load resistance (34), and the current value of the constant current source (36). Also, the resistance (3
If one of 2) and (33) is set as a variable resistor, the level of the subcarrier cancellation signal can be changed according to the level of the subcarrier in the composite signal, and the subcarrier can be canceled. Then, the output signal of the first adder circuit (10) is applied to the differential pair (29) and is multiplied by the subcarrier signals Q and * Q applied to the differential pair (27) and (28). By multiplying, the composite signal becomes L
Current mirror circuits (30) and (3) which are separated into R and R signals and which are supplied with the output signals of the differential pair (27) and (28).
The L and R signals are generated at the output terminals of 1). The output signal of the current mirror circuit (30) is supplied to the load resistors (37) and (38), and the output signal of the current mirror circuit (31) is supplied to the load resistors (39) and (40). The signals generated from one ends of the load resistors (37) and (39) are de-emphasized by the capacitors (16) and (17), respectively, and are generated at the output terminals (41) and (42). Also, load resistances (38) and (4
The signal generated at one end of (0) is amplified by the first and second amplifiers, respectively, and then added by the second adding circuit (13),
It is transmitted to the third adding circuit (14) in the subsequent stage. The signal generated from one end of the load resistors (38) and (40) is separated from the signal transmitted to the subsequent stage and applied to the first and second amplifiers (11) and (12). Has the same frequency characteristic as that of the low frequency component in the composite signal. Therefore, the low-frequency component in the output signal of the synchronous detection circuit (4) can be reliably removed in the third adder circuit (14).

FIG. 4 shows another embodiment of the present invention, in which (43) is a comparison circuit for comparing the output signals of the stereo decoder (2), and (44) is the output signal of the comparison circuit (43). Smoothing circuit for smoothing, (45) smoothing circuit (44)
Is a variable gain amplifier whose gain is controlled according to the output signal of In FIG. 4, the L and R signals generated from the stereo decoder (2) are applied to the (+) and (−) terminals of the comparison circuit (43), respectively, and compared. After that, the output signal of the comparison circuit (43) is smoothed by the smoothing circuit (44). Therefore, the comparison circuit (43) and the smoothing circuit (44) are equivalent to comparing the DC components contained in the L and R signals. Then, the smoothing circuit (4
The output signal of 4) is applied to the variable gain amplifier (45),
The level of the subcarrier cancellation signal is changed according to the output signal. The subcarrier cancel signal whose level is adjusted according to the DC component in the left and right audio signals is applied to the first adder circuit (10). And the first
In the adder circuit (10), the subcarrier signal in the composite signal is canceled. Here, when the output level of the smoothing circuit (44) is high, the variable gain amplifier (45)
The variable gain amplifier (45) has a large gain, and when the output level of the smoothing circuit (44) is small, the gain is small. Incidentally, as shown in FIG. 4, even if the level of the subcarrier cancellation signal is not controlled by providing the variable gain amplifier (45), one of the resistors (32) or (33) of FIG. The resistance value of the variable resistor may be varied according to the output signal of 44).

[0031]

According to the present invention, a subcarrier cancellation signal is generated according to a reproduced subcarrier signal, and the subcarrier cancellation signal is added to the composite signal, so that it is included in the output signal of the stereo demodulation circuit. Unnecessary DC components will not be generated, and shock noise due to DC fluctuations during stereo / monaural switching can be prevented. Further, the bias difference between the left and right audio signals caused by the unnecessary DC component is eliminated, and the adverse effect of the bias difference can be prevented.

Further, after the low frequency component is removed from the output signal of the synchronous detection circuit used for stereo identification, the output signal is smoothed by the low pass filter. Therefore, the cutoff frequency of the low pass filter is set to the audio signal band. It can be set, and therefore, the capacity of the capacitor that constitutes the low-pass filter can be reduced. In particular, since the capacitance of the capacitor can be reduced, it is a circuit suitable for making into an IC, and is also suitable for making a set small.

Further, since the output terminals for generating the output signal of the stereo decoder applied to the circuit subsequent to the stereo demodulation circuit and the output signal of the stereo decoder applied to the removal circuit are made different, in the removal circuit. ,
The low frequency component in the output signal of the synchronous detection circuit can be removed without being affected by the circuit in the latter stage.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a circuit diagram showing a main part of the present invention.

FIG. 4 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

 9 Cancellation signal generation circuit 10 First addition circuit 11 First amplifier 12 Second amplifier 13 Second addition circuit 14 Third addition circuit

Claims (5)

[Claims] 1. A PLL circuit for reproducing a sub-carrier frequency from a composite signal, and the composite signal for the PL circuit.
A stereo decoder for decoding according to the output signal of the L circuit, a synchronous detection circuit for synchronously detecting the composite signal and the output signal of the PLL circuit, a low-pass filter for smoothing the output signal of the synchronous detection circuit, and the low-pass filter. In a stereo demodulation circuit of a polar modulation system, which comprises a switch for conducting or blocking an output signal of a PLL circuit applied to the stereo decoder according to an output signal of a filter, a subcarrier cancellation signal according to an output signal of the PLL circuit. A stereo demodulation circuit comprising: a cancel signal generation circuit for generating the signal; and a first addition circuit for adding the subcarrier cancellation signal to the composite signal. 2. The stereo demodulation circuit according to claim 1, further comprising a removing circuit for removing a low frequency component in the output signal of the synchronous detection circuit according to the output signal of the stereo decoder. 3. An inverting circuit for inverting a left audio output signal of the stereo decoder, a second adding circuit for adding an output signal of the inverting circuit and a right audio output signal of the stereo decoder, and the synchronous detection circuit. The stereo demodulation according to claim 2, further comprising a third adder circuit connected between the low pass filter and the output signal of the synchronous detection circuit and the output signal of the second adder circuit. circuit. 4. In the stereo decoder, output terminals of left and right audio output signals applied to a circuit subsequent to the stereo demodulation circuit, and output terminals of left and right audio output signals applied to the cancel circuit. 3. The stereo demodulation circuit according to claim 2, wherein 5. A comparison circuit for comparing the DC components of the left and right audio output signals of the stereo decoder, and a variable circuit for varying the level of the subcarrier cancellation signal according to the output signal of the comparison circuit. The stereo demodulation circuit according to claim 1, characterized in that.