JPH0812641B2 - TLB entry control method - Google Patents

Description

DETAILED DESCRIPTION [Overview] Regarding control of a TLB composed of a plurality of ways (WAYs), a control method capable of rationally registering a translation pair when a virtual address and a real address are the same is described. Means for retaining a first translation pair for translating a virtual address into an absolute address and a second translation pair for translating a real address into an absolute address, and the first translation pair And a means for holding information indicating whether the second transform pair is used, or whether the first transform pair and the second transform pair can be used together. , A means for preventing the inclusion of the other conversion pair in the one conversion pair when registering the conversion pair in which the first conversion pair and the second conversion pair can be used together Configured by

[Industrial applications]

The present invention is a translation index buffering mechanism (hereinafter referred to as TLB) provided in the CPU of an information processing device to speed up address exchange
In particular, in a TLB that adopts a two-way (WAY) configuration of translation from virtual address to absolute address and translation from real address to absolute address, translation pair when virtual address and real address are equal It relates to a TLB control method that can reasonably perform registration of.

[Conventional technology]

FIG. 2 is a diagram showing an example of the configuration of the information processing device,
Reference numeral 51 represents a central processing unit (hereinafter also referred to as CPU), 52 represents a main memory control unit (hereinafter also referred to as MCU), and 53 represents main memory (hereinafter also referred to as MSU).

As shown in the figure, the CPU 51 controls the execution of instructions.
A unit 54 (hereinafter also referred to as IU), an E unit 55 (hereinafter also referred to as EU) that performs calculation, and an S unit 56 (hereinafter also referred to as SU) that reads / writes data are composed of three units. Further, the S unit 56 comprises a cache memory 57 for holding a copy of a part of the main memory, and a dynamic address translator (DAT) and a translation index buffer 58 (TLB) as a virtual memory mechanism.

The main memory access request from the IU 54 is made by the IU-REQ signal. IU-REQ-ADRS when IU-REQ signal is on
In accordance with / IU-REQ-ID, SU56 controls main memory read / write. If the IU-REQ-ID is a read instruction, the read data is stored in IU54 if it is an instruction fetch, in EU55 if it is an operand fetch, and in IWR59 or OWR60 by the CACHE-DATA signal. . If the IU-REQ-ID is a write instruction, a STORE-DATA signal is received from the EU and a store process is executed.

Data of REQ-ADRS is cached by read control 57
If not present, the SU 57 issues a main memory fetch request to the MCU 52. The main memory fetch request from SU56 is made by the MS-REQ signal. The MCU 52 starts main memory fetch according to MS-REQ-ADRS / MS-REQ-ID when the MS-REQ signal is on, accesses MSU53 and outputs the result to MS-D.
Send it to SU56 by ATA signal. SU56 receives this MS-DATA, stores it in the cache, and reports the result to IU54 or EU55.

In the case of write control, the SU 56 stores in the cache 57 and requests the MCU 52 for main memory store. MCU52 is MS-REQ / MS-REQ-ADRS / MS-REQ-ID / MS-D
Access MSU53 to execute main store according to ATA.

 FIG. 3 is a diagram showing an example of the configuration of the S unit.

The S unit (SU) has a pipeline of 4 cycles and is called a P cycle, a T cycle, a B cycle and an R cycle, respectively.

In P cycle, request from IU (IU-REQ / IU-
REQ-ADRS / IU-REQ-ID) and receive IU-REQ-ADRS
Store in TLAR61 (Tcycle-Logical-Address-Register).

In the T cycle, the TLB 62 is indexed by a part of the TLAR 61, and the directory part (CACHE-DIR) of the cache 63 is indexed by another part of the TLAR 61. The directory portion of the cache 63 stores valid bits and absolute addresses indicating the validity of each block of the data array portion. The cache is composed of multiple ways, and the directory information indexed from each way of the cache in the T cycle is matched in parallel with the absolute address read from the TLB62, and the result is MWNR64 (Match- Way
-Number-Register). At this time, all
If you don't get a match on WAY,
A miss occurs and the main memory fetch operation is started from the subsequent R cycle. When TLB62 misses, TMHR65 (TLB-MissHit-Register) is set.

In cycle B, read / write processing is performed on the data array section (CACHE-DAR) of the cache indicated by MWNR64, and if read, the result is stored in IWR66 or OWR67. In the case of a TLB miss hit, DAT68 is activated here.

 In the R cycle, MCU access is performed.

FIG. 4 is a diagram showing an example of the internal configuration of the TLB. TLB is
PRIMARY 72, and Alternate (ALTE
RNATE) 73 two ways, and the following entry information is stored in both ways similarly.

TLB71 has STATUS74a, 74bLOG-ADRS75a, 75bSYS-ADRS7
6a, 76b SPACE-ID77a, 77b DOMAIN-ID 78a, 78b each five pieces of information is stored.

STATUS74a and 74b are Valid indicating the validity of the entry.
Bit, V bit and R indicating whether LOG-ADRS75a, 75b (logical address) is a virtual address or a real address
It is composed of bits and CS bits that indicate common segments. First, the relationship between the V bit and the R bit
Shown in the table. The cases of V = R = 0 and V = R = 1 are prohibited conditions.

SYS-ADRS76a, 76b (absolute address) stores the conversion result of DAT and is a system address.

SPACE-IDs 77a and 77b store identification information of spaces in multi-virtual. This entry is ignored if the CS bit in STAUS is on.

The DOMAIN-IDs 78a and 78b store VM identification information in the VM (virtual machine) mode.

Each of the above information is checked at the same time as the TLB index of the T cycle, and only when all match, it becomes a TLB hit. In other cases, TLB miss hit occurs and DAT is started. The DAT performs conversion by referring to a predetermined conversion table and sends the result to the TLB. Note that the DAT also executes real address → absolute address conversion such as prefix conversion.

When the TLB 71 receives the DAT result (SYS-ADRS), it stores the result in the empty entry in either the primary 72 or the alternate 73. If there is no vacancy in either WAY, a replacement WAY candidate (TLB-H & C-REPL) is selected by the HOT & COLD algorithm. Actually, because of this HOT & COLD algorithm, it is equipped with REPLACE-ARRAY that registers the most recently accessed WAY number (0/1) for each entry as the reference history of TLB.
When the T result TLB is registered, this entry information is TLB-H &
It is read as C-REPL.

When registering an entry of a common segment, if TLB simultaneous matching occurs in two ways (WAY), it will be considered as a hardware failure and it will be a machine check, so in order to prevent it, the way to register Opposite W
Care must be taken that the AY entry information is not included in the common segment entry registration information, for which the TLB-H & C-REPL signal alone is not sufficient.

Therefore, in reality, the logic gate 81 as shown in FIG.
By using the circuit consisting of ~ 88, the entry information of the WAY opposite to the WAY to be registered is not included in the entry registration information of the common segment.

That is, in the figure, PRI-COM-MCH and ALT-CO
Each signal of M-MCH is the SPACE of PRIMARY or ALTERNATE.
-A signal indicating that the entry information excluding the ID matches the entry registration information of the common segment,
The COMMON-SEGM signal is a signal that indicates that the result of DAT is a common segment, and is TLB-PRI-WRT-1 / TLB.
Each signal of -ALT-WRT-1 is a signal for instructing the final replacement of each WAY. Also, TLB-ALT-
The INV-1 signal is a signal instructing to turn off the valid bit of ALTERNATE.

[Problems to be Solved by the Invention]

In the conventional system as described above, registration is prohibited when V = R = 1 (virtual address = real address) as the V / R bit relationship shown in Table 1. However, in an actual system, the virtual address and the real address are often the same in the system-specific area, and the access frequency is often high. In such cases, LO
G-ADRS = virtual address / LOG-ADRS = two entries are always used depending on the real address, which is insufficient in terms of TLB usage efficiency. Therefore, V = R
It was desired that the case of = 1 can be registered in the same entry. However, if the conventional method permits the entry of V = R = 1, the following inconvenience occurs. For example, in this conventional method, V = R = 1
When registering the entry in the TLB, the TLB-PRI-WRT-1 is turned on according to the above algorithm, and V = R =
Considering the case where the entry of 1 is registered on the primary side, at this time, if the V bit on the alternate side is off and the R bit is on (only real address → absolute address conversion is possible), The TLB registration information may be included on the primary side (other registration information except V bit is the same). In this case, as in the case of the previous common segment, a double match occurs, resulting in a machine check. this is,
The same applies when the primary and alternate are reversed. As described above, in the conventional method, when the entry of V = R = 1 is permitted, there is a problem that a double match occurs in the TLB.

In view of such a conventional problem, the present invention provides a TLB entry control method that can provide an entry of V = R = 1 when a virtual address and a real address are equal and does not cause a double match. It is intended to be provided.

[Means for solving the problem]

According to the invention, the above mentioned objects are achieved by the means recited in the claims. That is, according to the present invention, in a TLB that is a translation lookaside buffer mechanism provided for speeding up address translation when an information processing device is used by using a virtual address, a first address that translates a virtual address into an absolute address is provided. And a means for holding a second translation pair for translating a real address into an absolute address, and whether the first translation pair is used or the second exchange pair is used. Alternatively, a means for holding information indicating whether the first exchange pair and the second exchange pair can be used together and the first conversion pair and the second conversion pair can be used together. This is a TLB entry control system provided with means for suppressing inclusion of the other conversion pair in the one conversion pair when registering possible conversion pairs.

[Action]

As described above, in the conventional method, when the TLB is composed of a plurality of ways as described above, the conversion from the real address to the absolute address is (R = 1) and the virtual address to the absolute address is set. Is performed as (V = 1), when the virtual address and the real address are equal, that is, when an entry of V = R = 1 is to be registered,
Although it has a drawback that another entry included by the registered entry may remain, according to the method of the present invention, when the entry of V = R = 1 is registered, the above means is used. Since another entry included by the registered entry is not generated, no inconvenience occurs even when the common segment is registered.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention.
Each indicate a logic gate.

In the figure, the circuit consisting of logic gates 1 to 8 is the WAY opposite to the conventional way to register already shown in FIG.
This is the same as the circuit for preventing the entry information of 1) from being included in the entry registration information of the common segment.

That is, in FIG. 5, the signal indicated by the letter A is + TLB-PRI-WRT-1 in FIG. 5, the signal indicated by the letter B is + TLB-ALT-WRT-1, and The signal indicated by C corresponds to + TLB-ALT-INV-1.

On the other hand, the circuit including the logic gates 9 to 18 is provided for realizing the present invention.

In the figure, each signal of PRI-REAL-MCH / ALT-REAL-MCH indicates that other TLB registration information except the V bit of the entry to be registered matches the TLB registration information of each PRIMARY / ALTERNATE. TLB-V =
The R-ENTRY signal indicates that the entry to be registered is V =
This is a signal indicating that the entry is R = 1. The
The signals indicated by the letters A, B, and C were signals of the TLB replacement result logic in the conventional method, but TLB-PRI-WRT-2 / T
Each signal of LB-ALT-WRT-2 / TLB-ALT-INV-2 is a signal of TLB replacement result logic in the method of the present invention.

〔The invention's effect〕

As described above, according to the method of the present invention, in a TLB including a plurality of ways (WAY), V = R =
Since it is possible to register one entry without causing a double match, it is possible to improve the processing efficiency of the TLB, and it is possible to register a larger number of entries in the TLB, which results in processing speed. There is an advantage that it is possible to speed up.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of an information processing device, FIG. 3 is a diagram showing an example of the configuration of an S unit, and FIG. 4 is the inside of a TLB. FIG. 5 shows an example of the configuration, and FIG. 5 is a circuit for preventing entry information of a way opposite to the conventional way to be registered from being included in the entry registration information of the common segment. 1-18 …… Logic gate

Claims (1)

[Claims] 1. A TLB, which is a translation lookaside buffer mechanism provided for accelerating address exchange when an information processing device is used by using a virtual address, converts a virtual address into an absolute address. Means for holding a translation pair and a second translation pair for translating a real address into an absolute address, and a state of using the first translation pair or a state of using the second exchange pair, Alternatively, the first transform pair and the second
When registering a means for holding information indicating whether it is possible to use both the conversion pair and the conversion pair capable of using both the first conversion pair and the second conversion pair, A TLB entry control method, characterized in that a means for suppressing inclusion of the other conversion pair in one conversion pair is provided.