JPH08126367A - Inverter - Google Patents

Abstract

PURPOSE: To set an optimal slow down time causing no overcurrent automatically when a DC brake power is applied to an induction motor. CONSTITUTION: Upon provision of an operation stop command, a frequency reference f* is fixed at 'FdB' and a voltage reference v* is subtracted sequentially to slow down an induction motor 24. After the induction motor 24 slowed down sufficiently, a DC brake start command Sa is delivered to prevent overcurrent flow at the time of DC braking the induction motor 24. Output current from an inverter circuit 23 is detected by means of current detectors 41a-41c and the state of subtraction time switching means 45 is switched based on the peak value of detected current such that the induction motor 24 slows down slowly when it is in overcurrent level otherwise the induction motor 24 slows down quickly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device for performing variable speed control of an AC motor, and more particularly to an inverter device having improved control characteristics during braking of the AC motor.

[0002]

2. Description of the Related Art In an inverter device, when stopping an induction motor, a method of exciting the induction motor by direct current to obtain a braking torque is often used. Recently, in particular, it has been required to apply DC braking to stop the induction motor from a high frequency range or stop from an arbitrary frequency. FIG. 4 shows a conventional configuration of an inverter device having such a DC braking function.

In FIG. 3, when the operation stop switching means 1 is in the operation mode (shown by a solid line), when the target frequency Fc is set by the frequency setting device 2, the target frequency Fc is the acceleration / deceleration means 3 as the frequency command fc. Is output to. Then, the acceleration / deceleration means 3 sets the current output frequency to the frequency command f.
The frequency reference f ^* is created by accelerating or decelerating to c, and the created frequency reference f ^* is generated by the PWM signal generator 4
And output to the V / f setting means 5.

When the frequency reference f ^* is given, the V / f setting means 5 receives the voltage reference v ^* according to the frequency reference f ^{* .}
Is generated and output to the PWM signal generator 4. Then P
The WM signal generator 4 creates a PWM signal based on the frequency reference f ^* and the voltage reference v ^*, and outputs this PWM signal to the inverter circuit 7 through the drive circuit 6. As a result, the inverter circuit 7 is switching-controlled based on the PWM signal, and the induction motor 8 is rotation-controlled.
Incidentally, 9 is a three-phase AC power supply, and 10 is a converter circuit.

On the other hand, when the operation stop switching means 1 is switched to the stop mode (shown by a chain double-dashed line), the DC braking switching means 11 is turned on. At the same time, the frequency command “0 Hz” is output to the acceleration / deceleration means 3, and the acceleration / deceleration means 3 subtracts the current output frequency toward “0 Hz”. In this state,
When the frequency detecting means 12 detects “frequency reference f ^* ≦ FdB”, the frequency detecting means 12 outputs the DC braking start command S.
a is output, the voltage reference switching unit 13 switches to "VdB", the frequency reference switching unit 14 switches to "0 Hz", and the PWM signal generator 4 receives the frequency reference "0 Hz" and the voltage reference "VdB". Given. As a result, the DC braking command S is output from the PWM signal generator 4, and the braking force acts on the induction motor 8. Along with this, the timer means 15
Starts counting up, and when it detects that a predetermined time T has elapsed, it outputs a DC braking stop command So and cancels DC braking.

However, in the above configuration, when the DC braking is performed in a state where the operating frequency of the induction motor 8 is relatively high,
When the input current of the induction motor 8 is switched from AC to DC (that is, when DC braking is started), there is a fear that an overcurrent may flow in the induction motor 8. In this way, when an overcurrent flows through the induction motor 8, the inverter device trips,
In extreme cases, the inverter device may be damaged,
The induction motor 8 is in the free-run state, and the purpose of stopping the induction motor 8 cannot be achieved.

Therefore, the present applicant has proposed an inverter device having the structure shown in FIG. Here, when the frequency detecting means 12 detects “frequency reference f ^* ≦ FdB”, the frequency reference switching means 16 changes the frequency reference f ^* to “Fd.
It is fixed to "B" and the voltage reference v ^* is switched to "0V" by the voltage reference switching means 17. Then the delay 18
, The voltage reference v ^* immediately before the “frequency reference f ^* ≦ FdB” is continuously subtracted to the voltage value “0V”, and the PWM signal generator 4 is passed through the voltage reference switching means 13 (in the state shown by the solid line). Output to.

Then, after the induction motor 8 is slowed down in accordance with the subtraction of the voltage reference v ^* , the voltage reference switching means 1
3 is switched to "VdB", the frequency reference switching means 14 is switched to "0 Hz", and the braking force is applied to the induction motor 8 to prevent the occurrence of overcurrent. 6A is a control command, FIG. 6B is a frequency reference f ^* , and FIG. 6C is a voltage reference v ^*.
And the frequency reference f ^* is "Fd" at time Ta.
When fixed at "B", the voltage reference v ^* is subtracted and the time T
DC braking is started at b.

[0009]

However, in the configuration shown in FIG. 5, the frequency detecting means 12 has the "frequency reference f ^* " ^.
When ≦ FdB ”is detected, the voltage reference v ^* is subtracted at a fixed rate, and the induction motor 8 is slowed down for a fixed time. Therefore, when the output current does not reach the overcurrent level, the slowdown time of the induction motor 8 becomes unnecessarily long, and wasteful time is spent stopping the induction motor 8.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an inverter device in which an optimum slowdown time can be selected according to the situation and unnecessary time is not required to stop the AC motor. Is to provide.

[0011]

According to another aspect of the present invention, an inverter device includes a frequency reference creating means for creating a frequency reference, a voltage reference creating means for creating a voltage reference, and the frequency reference and the voltage reference. A signal creating unit that creates a control signal and an inverter circuit that drives and controls the AC motor based on switching by the control signal are provided, and the frequency reference creating unit and the voltage reference creating unit are directed toward a target speed. In the configuration in which the AC motor is rotated at the target speed by changing the creation signal, the frequency reference created by the frequency reference creating means is fixed to a predetermined value in response to the output of the operation stop command. Fixing means for supplying to the signal generating means, and with this fixing means fixing the frequency reference to a predetermined value, The subtracting means for subtracting the voltage reference created by the voltage reference creating means and supplying it to the signal creating means, and the DC braking start command accompanying detection of the subtraction means subtracting the voltage reference to a predetermined value. To output a DC braking command from the signal generating means to the inverter circuit, a current detecting means for detecting a current indicating a rotation state of the AC motor, and a detection signal of the current detecting means. And subtraction time adjusting means for adjusting the subtraction time of the voltage reference by the subtracting means.

According to another aspect of the present invention, an inverter device is provided with current detecting means on the output side of each phase of the inverter circuit, and peak value detecting means for detecting peak values of detection signals output from the plurality of current detecting means. And comparison means for comparing the peak value detected by the peak value detection means with a predetermined value, and subtraction time switching means for switching the voltage-based subtraction time by the subtraction means between high speed and low speed based on the comparison result of the comparison means. It is characterized in that the subtraction time adjusting means is composed of

According to another aspect of the present invention, an inverter device is provided with a current detecting means on the output side of each phase of the inverter circuit, and a peak value detecting means for detecting peak values of detection signals output from the plurality of current detecting means. And the subtraction time continuous changing means for continuously changing the voltage-based subtraction time by the subtracting means according to the peak value detected by the peak value detecting means.

[0014]

According to the means described in claim 1, when the operation stop command is output, first, the voltage reference is subtracted according to the subtraction time adjusted based on the output current of the inverter circuit,
The subtracted voltage reference is sequentially supplied to the signal generating means.
At the same time, the frequency reference fixed to a predetermined value is supplied to the signal generating means. Then, the control signal is supplied from the signal generating means to the inverter circuit, the AC motor slows down in accordance with the control signal, and then the DC braking start command is output.

According to the second aspect, when the output current of each phase of the inverter circuit is detected, first, the peak value of these detection signals is detected. Next, the peak value is compared with a predetermined value, and based on the comparison result, the voltage-based subtraction time by the subtracting means is switched to high speed or low speed.

According to the third aspect, when the output current of each phase of the inverter circuit is detected, first, the peak value of these detection signals is detected. Next, the voltage-based subtraction time by the subtracting means is continuously changed according to the peak value.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will now be described with reference to FIGS.
It will be described based on. First, in FIG. 1, a converter circuit 22 is connected to the three-phase AC power supply 21. The converter circuit 22 includes a rectifier circuit 22a and a rectifier circuit 22.
a of the smoothing capacitor 22d connected to the DC power supply lines 22b and 22c.
An inverter circuit 23 is connected to 2b and 22c. The inverter circuit 23 has a well-known configuration in which switching elements such as IGBTs are bridge-connected, and each output terminal of three phases is connected to each input terminal of an induction motor 24 as an AC motor.

The main control circuit 25 is mainly composed of a microcomputer, and controls the later-described rotation control of the induction motor 24 based on the software configuration thereof. Then, the operation command and the operation stop command output from the main control circuit 25 are output to the operation stop switching means 26, and the operation stop switching means 26 operates on the basis of the operation command and the operation stop instruction in the operation mode (shown by a solid line). ) And stop mode (indicated by the chain double-dashed line). Frequency setting device 2
Reference numeral 7 sets a target frequency Fc corresponding to the target speed, and when the operation stop switching means 26 is in the operation mode, the target frequency Fc set by the frequency setter 27.
Is output to the acceleration / deceleration means 28 as a frequency command fc.
Further, when the operation stop switching means 26 is in the stop mode,
“Frequency command fc = 0 Hz” is output to the acceleration / deceleration means 28.

The acceleration / deceleration means 28 corresponds to a frequency reference creating means, creates a frequency reference f ^* based on the frequency command fc, and uses this frequency reference f ^* in the PWM signal generator 29 and V / f setting means. Output to 30. The V / f setting means 30 corresponds to a voltage reference creating means,
The voltage reference v ^* is created based on the frequency reference f ^* , and the created voltage reference v ^* is output to the PWM signal generator 29.
The PWM signal generator 29 corresponds to a signal generating means, and has a sinusoidal PW based on both references f ^* and v ^*.
An M signal is created and this PWM signal is output to the inverter circuit 23 through the drive circuit 31. As a result, the inverter circuit 23 is switching-controlled, and the induction motor 23 rotates at the frequency reference f ^* .

The acceleration / deceleration means 28 is configured to change the frequency reference f ^* by accelerating or decelerating the current output frequency toward the frequency command fc.
Therefore, the voltage reference v ^* created by the V / f setting means 30 also changes according to the frequency reference f ^* . Then, the acceleration / deceleration means 28 and the V / f setting means 30 make the frequency command fc
By changing the output signal toward, the induction motor 24 rotates at the target frequency Fc.

The frequency detection means 32 detects that the frequency reference f ^* created by the acceleration / deceleration means 28 is less than or equal to a predetermined value "FdB", and "frequency reference f ^* ≤".
When "FdB" is detected, the slowdown command Sb is output. The slowdown command transmission means 33 is ON / OFF driven in conjunction with the operation stop switching means 26, and is turned on when the operation stop switching means 26 enters the stop mode, and the slowdown command Sb of the frequency detecting means 32 is sent. Is output to the frequency reference switching means 34.

The frequency switching means 34 corresponds to a fixing means, and when the slowdown command Sb is not output, the frequency reference f ^* created by the acceleration / deceleration means 28 ^.
Is output to the PWM signal generator 29 (shown by a solid line). When the slowdown command Sb is output,
The state is switched to a state in which the fixed frequency "FdB" is output to the PWM signal generator 29 (shown by a chain double-dashed line). The slowdown command Sb of the frequency detection means 32 is also output to the voltage reference switching means 35. This voltage reference switching means 35
The voltage reference v ^* created by the / f setting means 30 is output to the delay 36a.
When "b" is received, it is switched to "0V" (state indicated by a chain double-dashed line).

The delay 36a comprises software of a microcomputer, and the voltage reference switching means 3
As 5 changes to "0V", the output voltage reference v ^* is continuously subtracted to the input voltage value (that is, "0V"). In this case, the delay 36a has a voltage reference v ^*.
There are two types of subtraction patterns, the first is a high-speed subtraction pattern for subtracting the voltage reference v ^* at a constant high rate, and the second is a low-speed subtraction pattern for subtracting the voltage reference v ^* at a constant low rate. Is. Then, the delay 36a subtracts the voltage reference v ^* according to the high-speed subtraction pattern in a short time, and subtracts according to the low-speed subtraction pattern over a long time.

Slow down command S of the frequency detecting means 32
b is also output to the voltage reference switching means 36b. This voltage reference switching means 36b is provided with the delay 36a and the subtraction means 3
When the slowdown command Sb is received, the voltage reference v ^* subtracted by the delay 36a is switched to the state of being supplied to the PWM signal generator 29 (shown by a chain double-dashed line).

The zero voltage detecting means 37a includes a delay 36.
a detects the subtracted voltage reference v ^*, and detects that the voltage reference v ^* has been subtracted to the lower limit value “0V”. When “voltage reference v ^* = 0” is detected, detection is performed. The signal Sc is output to the DC braking command generator 37b. The DC braking command generator 37b constitutes command output means together with the zero voltage detection means 37a, and is composed of, for example, an AND circuit, and the detection signal S of the zero voltage detection means 37a.
In response to receiving both c and the slowdown command Sb of the frequency detection means 32, the DC braking start command Sa is output.

The DC braking start command Sa of the DC braking command generator 37b is output to the frequency reference switching means 38 and the voltage reference switching means 39. The frequency reference switching means 38 is
The frequency reference f ^* supplied to the PWM signal generator 29 is set to “0.
Hz ", and the switching operation is executed in response to receiving the DC braking start command Sa. The voltage reference switching means 39 switches the voltage reference v ^* supplied to the PWM signal generator 29 to a predetermined voltage value “VdB”, and the switching operation is accompanied by receiving the DC braking start command Sa. To be executed. Therefore, the DC braking start command S
When “a” is output, “0 Hz” is output to the PWM signal generator 29.
And "VdB" will be supplied, resulting in
The DC braking command S is output from the PWM signal generator 29,
DC braking force acts on the induction motor 24.

The DC braking start command Sa of the DC braking command generator 37b is also output to the timer 40. The timer 40 sets an application time of DC braking to the induction motor 24, starts counting up in response to receiving the DC braking start command Sa, and when the set time T elapses, the PWM signal generator 29. DC braking stop command So
Is output to end the DC braking.

The power supply line for each phase of the inverter circuit 23 includes
Current detectors 41a to 41c are provided on the output side thereof. These current detectors 41a to 41c correspond to current detecting means and are connected to the signal detector 42. The signal detector 42 is the current detector 41.
The output current values Ia to Ic flowing in each phase of the inverter circuit 23 are detected based on the detection signals a to 41c. Also,
The peak value detecting means 43 is connected to the signal detector 42, and the peak value detecting means 43 detects the absolute maximum value Imax of the current values Ia to Ic detected by the signal detector 42.

A comparing means 44 is connected to the peak value detecting means 43, and the comparing means 44 is the peak value detecting means 43.
The absolute maximum value Imax is compared with the set level Ibase, and a signal corresponding to the comparison result is output to the voltage reduction time switching means 45. The set level Ibase is a current level at which an overcurrent does not flow reliably when applying a DC braking force to the induction motor 24.

The voltage reduction time switching means 45 corresponds to the subtraction time switching means, and when the output signal of the comparison means 44 indicates "absolute maximum value Imax≤setting level Ibase", it is indicated by the solid line "high". "Switch to the state. Also,
If it indicates "absolute maximum value Imax> setting level Ibase", the state is switched to the "low" state indicated by the chain double-dashed line. The voltage reduction time switching means 45 is connected to the delay 36a, and when the "high" state is entered, the delay 36a is changed.
The selection signal "S high" is output to and the voltage reference v ^* is subtracted according to the high speed subtraction pattern. Further, the selection signal "S low" is output to the delay 36a in accordance with the switching to the "low" state, and the voltage reference v ^* is subtracted according to the low speed subtraction pattern. The reference numeral 46 indicates a subtraction time adjusting means composed of a peak value detecting means 43, a comparing means 44 and a reduced voltage time switching means 45.

Next, the operation of the above configuration will be described.
When the operation stop switching means 26 is in the operation mode as indicated by the solid line in FIG. 1, the target frequency Fc set by the frequency setting device 27 is the acceleration / deceleration means 2 as the frequency command fc.
8 is supplied. Then, acceleration and deceleration means 28 creates a frequency reference ^{f *} based on the frequency instruction fc, PW frequency reference ^{f *} through frequency reference switching means 34 and 38
It is supplied to the M signal generator 29. At the same time, the frequency reference f ^* is supplied to the V / f setting means 30, converted into the voltage reference v ^* by the V / f setting means 30, and then supplied to the PWM signal generator 29 through the voltage reference switching means 36b and 39. To be done.

When the frequency reference f ^* and the voltage reference v ^* are supplied, the PWM signal generator 29 outputs both references f ^* and v ^*.
A PWM signal is created based on ^* , and this PWM signal is supplied to the inverter circuit 23 through the drive circuit 31. As a result, the inverter circuit 23 is switching-controlled, and the induction motor 24 rotates at the frequency reference f ^* .
Therefore, the frequency reference f output from the acceleration / deceleration means 28
^{As *} changes sequentially toward the frequency command fc,
The frequency reference f ^* and the voltage reference v ^* output to the PWM signal generator 29 change, and the induction motor 24 finally rotates at the frequency command fc.

When an operation stop command is output from the main control circuit 25 in this state, the operation stop switching means 26 is switched to the stop mode as shown by the chain double-dashed line in FIG. Is turned on. At the same time, the frequency command “0 Hz” is supplied to the acceleration / deceleration means 28, the acceleration / deceleration means 28 sequentially subtracts the frequency reference f ^* toward “0 Hz”, and the V / f setting means 30 makes the acceleration / deceleration means 28. The voltage reference v ^* is subtracted according to the frequency reference f ^* .

2A is a command signal of the main control circuit 25, FIG. 2B is a frequency reference f ^* , and FIG. 2C is a voltage reference v ^* .
(D) is the absolute maximum value I detected by the peak value detecting means 43.
Max indicates the case where the operating frequency of the induction motor 24 is high (when it is at the overcurrent level), and the two-dot chain line shows when the operating frequency of the induction motor 24 is low (when it is not at the overcurrent level). As is clear from the figure, when the stop command is output from the main control circuit 25 at time T1, the frequency reference f ^* is subtracted, and the voltage reference v ^* is also subtracted accordingly.

On the other hand, while the induction motor 24 is operating, the current detectors 41a to 41c detect the output current values Ia to Ic of the inverter circuit 23, and the peak value detecting means 43.
Detects the absolute maximum value Imax of the output current values Ia to Ic,
The comparison means 44 compares the absolute maximum value Imax with the set level Ibase, the reduction voltage time switching means 44 outputs a signal according to the comparison result of the comparison means 44, and the delay 36a outputs the output signal of the reduction voltage time switching means 44. The subtraction pattern of the voltage reference v ^* according to is selected.

For example, as shown by the solid line in FIG.
When the operating frequency of the induction motor 24 is high, when the subtraction of the frequency reference f ^* and the voltage reference v ^* is started at time T1, the absolute maximum value Imax is set as shown by the solid line in (d) of FIG. Exceed level Ibase. Therefore, the comparison result of the comparison means 44 becomes "absolute maximum value Imax> setting level Ibase", the voltage reduction time switching means 44 is switched to the "low" state, and the selection signal "S low" is output. Therefore, the delay 36a selects the low speed subtraction pattern for subtracting the voltage reference v ^* at a constant low rate based on the selection signal "S low".

Thereafter, when the frequency detecting means 32 detects "frequency reference f ^* ≤FdB", the frequency detecting means 32 outputs the slowdown command Sb, and the frequency reference switching means 34 switches to the state shown by the chain double-dashed line. Instead, the fixed frequency reference “FdB” is output to the PWM signal generator 29. At the same time, the voltage reference switching means 35 and 36b are switched to the state indicated by the chain double-dashed line, and the delay 36a outputs the slowdown command Sb based on the subtraction pattern selected when the slowdown command Sb is output. The voltage reference v ^* immediately after being output is subtracted toward "0V".
Here, since the low speed subtraction pattern is selected, the delay 36a slowly subtracts the voltage reference v ^* according to the low speed subtraction pattern.

The delay 36a, every time the voltage reference v ^* is subtracted, subtracts the subtracted voltage reference v ^* from the voltage reference switching means 36.
It outputs to the PWM signal generator 29 through b and 39. Then, the PWM signal generator 29 creates a PWM signal in which the (v ^* / f ^* ) ratio gradually decreases based on the fixed frequency reference “FdB” and the subtracted voltage reference v ^*, and The induction motor 24 is slowly slowed down based on the PWM signal. The time T2 in FIG. 2 is
2 shows the output time of the slowdown command Sb. When the slowdown command Sb is output, the frequency reference f ^* is fixed to "FdB" as shown in (b) of FIG. As shown in c), the voltage reference v ^* is slowly subtracted and the induction motor 24 slowly slows down,
As shown in FIG. 2D, the absolute maximum value Imax is attenuated.

After that, when the zero voltage detecting means 37a detects "voltage reference v ^* = 0", the zero voltage detecting means 37a.
Outputs a detection signal Sc from the DC braking command generator 37b to the DC braking command generator 37b.
And both the detection signal Sc and the DC braking start command S
Output a. Then, the frequency reference switching means 38 and the voltage reference switching means 39 are switched to the states shown by the alternate long and two short dashes line, and the PWM signal generator 29 outputs "0 Hz" and "Vd".
B "is supplied. As a result, the PWM signal generator 29
A DC braking command S is output from the drive circuit 31 to the inverter circuit 23, and a DC braking force acts on the induction motor 24.

At the same time, the timer 40 starts the counting operation upon receiving the DC braking start command Sa, and when the set time T elapses, outputs the DC braking stop command So to the PWM signal generator 29 to terminate the DC braking. . In FIG. 2, the time T3 is the output start time of the DC braking start command Sa,
Time T4 is the output time of the DC braking stop command So,
(T4-T3) corresponds to the set time of the timer 40.

When the operating frequency of the induction motor 24 is low, as indicated by the chain double-dashed line in FIG.
2, even if the subtraction of the frequency reference f ^* and the voltage reference v ^* is started, as indicated by a chain double-dashed line in (d) of FIG.
The absolute maximum value Imax does not exceed the set level Ibase. Therefore, the comparison result of the comparison means 44 is “absolute maximum value Imax ≦
The set level Ibase "is reached, the voltage reduction time switching means 45 switches to the" high "state and outputs the selection signal" S high ", and the delay 36a sets the voltage reference v ^* constant based on the selection signal" S high ". The high-speed subtraction pattern that subtracts at a high rate is selected.

Therefore, when the slowdown command Sb is output from the frequency detecting means 32 at the time T2 'in FIG. 2, the delay 3 is generated as shown by the chain double-dashed line in FIG.
6a quickly subtracts the voltage reference v ^* according to the high-speed subtraction pattern to quickly slow down the induction motor 24,
A DC braking force is applied at time T3 '. For this reason, the induction motor 24 is quickly stopped at the time T4 '.

According to the above embodiment, the inverter circuit 23
Output current of the induction motor 24, that is, the rotation state of the induction motor 24 is detected by the current detectors 41a to 41c, and when the induction motor 24 is at the overcurrent level, the overcurrent does not occur due to the application of the DC braking force. , Slowly induction motor 2
No. 4 is slowed down, and when the induction motor 24 is not at the overcurrent level, the induction motor 24 is quickly slowed down so that the slowdown time of the induction motor 24 does not become unnecessarily long.

Therefore, the optimum slowdown time is automatically selected according to the situation, and stable DC braking without current disturbance is performed without spending unnecessary time for stopping the induction motor 24. Become. In addition, the induction motor 24
Level Ibase such as whether or not is at the overcurrent level
Since the subtraction time of the voltage reference v ^* is switched between the high speed and the low speed based on the above, the slowdown time is adjusted sufficiently in practical use.

In the first embodiment, the subtraction time of the voltage reference v ^* is adjusted by selectively using two types of subtraction patterns, but the present invention is not limited to this. For example, three or more determination levels may be provided, and three or more types of subtraction patterns may be selectively used based on which determination level the absolute maximum value Imax corresponds to.

In the first embodiment, the subtraction pattern is selectively used to adjust the subtraction time of the voltage reference v ^* . However, the present invention is not limited to this. The second embodiment may be configured as shown in FIG. The second embodiment of the present invention will be described below. The delay 36a 'corresponds to a subtraction time continuous changing means and is composed of an A / D converter. The detection signal of the peak value detecting means 43 is directly input to the delay 36a ', and the comparing means 44 and the reduced voltage time switching means 45 are omitted. The reference numeral 36 'indicates a subtracting means composed of a delay 36a' and a voltage reference switching means 36b, and a reference numeral 46.
Reference numeral ′ denotes a subtraction time adjusting means including a delay 36a ′ and a peak value detecting means 43b.

In the case of this construction, when the peak value detecting means 43 detects the absolute maximum value Imax and outputs the absolute maximum value Imax to the delay 36a ', the delay initial value of the delay 36a' is larger than the absolute maximum value Imax. The subtraction time of the voltage reference v ^* continuously changes according to the magnitude of the absolute maximum value Imax. Therefore, the absolute maximum value I
When the max is large, the subtraction time by the delay 36a 'becomes long, and when the absolute maximum value Imax is small, the subtraction time by the delay 36a' becomes short. Therefore, the slowdown time is finely controlled as compared with the first embodiment in which the subtraction ratio is selected based on the comparison result between the absolute maximum value Imax and the set level Ibase.

In the first and second embodiments, the lower limit of subtraction of the delays 36a and 36a 'is "0".
However, the present invention is not limited to this, and in short,
Any value may be used as long as it can sufficiently slow down the induction motor 24.

[0049]

As is clear from the above description, the inverter device of the present invention has the following excellent effects. According to the means described in claim 1, when the AC motor is at the overcurrent level, the AC motor is slowly slowed down so that the overcurrent does not occur due to the application of the DC braking force. When the AC motor is not at the overcurrent level, the AC motor can be quickly slowed down so that the AC motor slowdown time does not become unnecessarily long. Therefore, the optimal slowdown time is automatically selected according to the situation, and stable DC braking without current disturbance is performed without spending unnecessary time for stopping the AC motor.

According to the second aspect of the invention, the voltage reference subtraction time can be switched between high speed and low speed based on a boundary value such as whether or not the AC motor is at the overcurrent level. The slowdown time is adjusted. According to the third aspect, the subtraction time can be changed according to the peak value of the output current of the inverter circuit, so the slowdown time can be finely adjusted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

2A shows a control command, FIG. 2B shows a frequency reference, FIG. 2C shows a voltage reference, and FIG. 2D shows an absolute maximum value of an output current of an inverter circuit.

FIG. 3 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 4 is a view corresponding to FIG. 1 showing a conventional example.

FIG. 5 is a view corresponding to FIG. 1 showing another conventional example.

6A is a diagram showing a frequency reference, and FIG. 6B is a diagram showing a voltage reference.

[Explanation of symbols]

23 is an inverter circuit, 24 is an induction motor (AC motor), 28 is acceleration / deceleration means (frequency reference creating means), 29
Is a PWM signal generator (signal creating means), 30 is V / f setting means (voltage reference creating means), 34 is frequency reference switching means (fixing means), 36 and 36 'are subtracting means, and 36a.
′ Is a delay (subtraction time continuous change means), 37 is a command output means, 41a to 41c are current detectors (current detection means), 43 is a peak value detection means, 44 is a comparison means, 45
Represents subtraction time switching means, and 46 and 46 'represent subtraction time adjusting means.

Claims (3)

[Claims] 1. A frequency reference creating means for creating a frequency reference, a voltage reference creating means for creating a voltage reference, a signal creating means for creating a control signal based on the frequency reference and the voltage reference, and the control signal. An inverter circuit for driving and controlling the AC electric motor based on switching by the AC electric motor, the frequency reference creating unit and the voltage reference creating unit changing the creating signal toward a target speed, thereby changing the AC motor to the In a configuration of rotating at a target speed, fixing means for fixing the frequency reference created by the frequency reference creating means to a predetermined value and supplying it to the signal creating means with the output of the operation stop command, With the fixing means fixing the frequency reference to a predetermined value, the voltage reference created by the voltage reference creating means is And a subtracting means for calculating and supplying the signal to the signal generating means, and a DC braking start command is output by detecting that the subtracting means subtracts the voltage reference to a predetermined value, and the signal generating means outputs the inverter circuit. A command output means for outputting a DC braking command to the, a current detection means for detecting a current indicating a rotating state of the AC motor, and a subtraction time of the voltage reference by the subtraction means based on a detection signal of the current detection means. An inverter device comprising: subtraction time adjusting means for adjusting. 2. The current detecting means is provided on the output side of each phase of the inverter circuit, and the subtraction time adjusting means detects the peak value of the detection signals output from the plurality of current detecting means. And comparing means for comparing the peak value detected by the peak value detecting means with a predetermined value, and subtraction time switching means for switching the voltage-based subtraction time by the subtracting means between high speed and low speed based on the comparison result of the comparing means. The inverter device according to claim 1, wherein the inverter device comprises: 3. The current detecting means is provided on the output side of each phase of the inverter circuit, and the subtraction time adjusting means detects the peak value of the detection signals output from the plurality of current detecting means. And a subtraction time continuous changing means for continuously changing the voltage-based subtraction time by the subtracting means according to the peak value detected by the peak value detecting means. Inverter device.