JPH08125934A - Signal processing circuit for solid-state image pickup element and its processing method - Google Patents

Abstract

PURPOSE: To perform gain matching among plural channels by simple circuit constitution by integrating the video signal parts of the plural channels for a prescribed period, performing comparison with a reference in common among the channels and controlling the output system gain of the plural channels. CONSTITUTION: The video signal parts of a first channel and a second channel passed through the respective horizontal transfer registers 4 and 5 of a CCD solid-state image pickup element 11 are respectively integrated for the prescribed period in the detection circuits 17 and 18 of this signal processing circuit 12 and average signals are detected. The respective detection outputs are compared with the same reference signals based on the assumption that the signal levels of fields each other are approximately the same in respective comparators 19 and 20. Then, corresponding to a compared result, the gains of the respective plural channels such as the two channels or the like are controlled through AGCs 15 and 16. By the simple circuit constitution using a common reference value, the gain matching of the plural channels is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for a solid-state image pickup device and a processing method thereof, and more particularly to a signal processing circuit for processing output signals of respective channels of a solid-state image pickup device having an output system of a plurality of channels and processing thereof. Regarding the method.

[0002]

2. Description of the Related Art As a solid-state image pickup device having an output system of a plurality of channels, for example, a so-called all-pixel read-out type CCD solid-state image pickup device which reads out signal charges read from respective pixels without being mixed in a vertical transfer register. is there.
This all-pixel-reading CCD solid-state image sensor is provided with two horizontal transfer registers in order to improve the resolution, and the signal charges of the odd lines and the signal charges of the even lines are horizontally transferred simultaneously by separate horizontal transfer registers. The signal charges for two lines are read out within 1H (H is a horizontal scanning period).

In a CCD solid-state image pickup device having a two-channel output system such as the CCD read-out type solid-state image pickup device, when variations occur in the gain of the output system of each channel, the variations occur. It will be reflected as a level difference in the output signal of the channel.
For example, in FIG. 5, when the signal charges of each pixel of the original image (a) are read out in two channels and are combined, if there is a gain difference between the channels, the output (b) of each channel is accompanied by this. , (C) cause a level difference (density difference in the drawing), which causes the output image (d) to have horizontal stripes and impair the image quality.

In order to solve this, it is necessary to match the gain between the channels in the signal processing circuit of the CCD solid-state image pickup device. Therefore, conventionally, in the output portions of the two horizontal transfer registers, the same amount of pilot signal charges are injected into each channel so that the signal level of one channel based on the injected charges becomes a predetermined reference voltage. While controlling the gain of the channel, the gain of the other channel is adjusted to the gain of the one channel so that the signal level of the other channel becomes equal to the signal level of the one channel. The configuration of the conventional example is shown in FIG.

In FIG. 6, the same amount of pilot signal charges are injected into the dummy bit portions on the output side of the two horizontal transfer registers 61 and 62 of the CCD solid-state image pickup device 60. Then, the charge for pilot signal is transferred horizontally before the charge detecting unit 6 by the horizontal transfer.
3, 64 converted into voltage signals and output amplifiers 65, 66
Through, and is supplied to the signal processing circuit 67. In the signal processing circuit 67, the CCD outputs 1 and 2 of the CCD solid-state image pickup device 60 are sampled / held (S
/ H) is sampled / held by the circuits 68 and 69, and
After passing through the GC (Auto Gain Control) circuits 70 and 71, A
The signals are converted into digital signals by the / D (analog / digital) converters 72 and 73.

In the subsequent stage of the AGC circuit 70, the signal level of the pilot signal included in the output of one channel ch1 is detected by the detection circuit 74, and the signal level is compared with a predetermined reference voltage Vref by the comparator 75. . As a result, the reference voltage Vre is output as the comparison output of the comparator 75.
The level difference of the pilot signal on the channel ch1 side with respect to f is derived. Then, this comparison output becomes the gain control signal of the AGC circuit 70. As a result, the gain of the output system of the channel ch1 is automatically adjusted so that the signal level of the pilot signal on the channel ch1 side always becomes the reference voltage Vref.

On the other hand, on the output side of the A / D converters 72 and 73, the pilot signals contained in the respective outputs of the channels ch1 and ch2 are sample / hold circuits 76 and 7.
7 is sampled and held, and the respective signal levels are compared by the comparator 78. As a result, the level difference between the signal levels of the pilot signals of the channels ch1 and ch2 is derived as the comparison output of the comparator 78. Then, this comparison output becomes the gain control signal of the AGC circuit 71. As a result, the gain of the output system of the channel ch2 is automatically adjusted so that the signal level of the pilot signal of the channel ch2 becomes equal to the signal level of the pilot signal of the channel ch1 adjusted with respect to the reference voltage Vref. Will be done.

[0008]

However, in the conventional signal processing circuit having the above-described structure, it is necessary to inject a dedicated pilot signal charge for gain matching, and the gain of one channel ch1 is required. Since a circuit system for automatically adjusting and a circuit system for adjusting the gain of the channel ch1 to the gain of the other channel ch2 are required, there is a problem that the configuration becomes very complicated and the cost becomes high.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a signal of a solid-state image pickup device capable of reliably performing gain matching between a plurality of channels with a simple circuit configuration. A processing circuit and a processing method thereof are provided.

[0010]

A signal processing circuit according to the present invention is a circuit for processing an output signal of each channel of a solid-state image pickup device having an output system of a plurality of channels. Integrating means for integrating the video signal portion within a predetermined period, comparing means for comparing the integrated value of each of the plurality of channels with a common reference voltage between the channels, and depending on the comparison output for each channel of the comparing means. It has a configuration including a gain control means for controlling the gain of the output system of a plurality of channels.

A signal processing method according to the present invention is a method for processing output signals of respective channels of a solid-state image pickup device having an output system of a plurality of channels, wherein a video signal portion in each output signal of the plurality of channels is subjected to a predetermined period. Then, the integrated value of each of the plurality of channels is compared with a reference voltage common to each channel, and the gains of the output systems of the plurality of channels are controlled according to the comparison result of each channel.

[0012]

In the present invention, it is noted that the average signal levels of fields (or frames) in a general image are almost the same. Then, in the signal processing circuit and the processing method thereof having the above-described configuration, first, the integral value of each video signal of a plurality of channels within a predetermined period is obtained, and the integral value of each channel is compared with a reference voltage common to each channel. Since the average signal levels of fields (or frames) are almost the same, the reference voltage for gain setting can be made common to each channel. Then, the gain of the output system of each channel is controlled according to the comparison result obtained for each channel.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention applied to a CCD solid-state image pickup device of the all pixel reading type will be described in detail below with reference to the drawings. It should be noted that the present invention is not limited to the application to the CCD solid-state image pickup device of the all-pixel readout system, and can be applied to all solid-state image pickup devices having an output system of a plurality of channels.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, a plurality of sensor units (photoelectric conversion units) 1 arranged in a matrix in a row direction (vertical direction) and a column direction (horizontal direction) and accumulating signal charges according to the amount of incident light, and these sensor units. An image pickup area 3 is configured by a plurality of vertical transfer registers 2 which are arranged for each vertical column and vertically transfer the signal charges read from each sensor unit 1.

In the image pickup area 3, the sensor section 1 is composed of, for example, a PN junction photodiode, and the vertical transfer register 2 is composed of a CCD. Sensor part 1
The signal charge stored in the vertical transfer register 2 is read by applying a charge read pulse XSG to a read gate (not shown). The vertical transfer register 2 is transfer-driven by, for example, four-phase vertical transfer clocks φV1 to φV4. The signal charges read out to the vertical transfer register 2 are sequentially transferred in the vertical direction for each part corresponding to one scanning line in a part of the horizontal blanking period.

On the lower side of the image pickup area 3 in the drawing, two horizontal transfer registers 4 and 5 composed of CCDs to which signal charges corresponding to one scanning line are sequentially transferred from a plurality of vertical transfer registers 2 are transferred. The gates 6 are arranged in parallel with each other. Of these two horizontal transfer registers 4 and 5, odd line signal charges are transferred to the horizontal transfer register 4 on the side of the imaging region 3, and even line signal charges are transferred to the other horizontal transfer register 5. 4 and the transfer gate 6. The two horizontal transfer registers 4 and 5 are transfer-driven by the two-phase horizontal transfer clocks φH1 and φH2. As a result, the signal charges for two lines are sequentially transferred in the horizontal direction in the horizontal scanning period after the horizontal blanking period.

At the ends of the horizontal transfer registers 4 and 5, for example, charge detecting units 7 and 8 having a floating diffusion structure are arranged, and the signal charges of the two channels that are horizontally transferred are supplied to the charge detecting units 7 and 8. The voltage signals are sequentially converted. Then, this voltage signal is amplified by the output amplifiers 9 and 10 and then derived as image pickup outputs of two channels ch1 and ch2 according to the incident amount of light from the subject. As described above, the interline transfer type CCD solid-state imaging device 11 is configured.

2 channels c of CCD solid state image pickup device 11
The image pickup outputs of h1 and ch2 are supplied to the signal processing circuit 12 according to the present embodiment. The signal processing circuit 12 is provided to adjust the variation in gain between the channels, and is a sample / hold (S / H) circuit 13 that samples / holds the imaging outputs of the two channels ch1 and ch2, respectively. , 14 and an AGC circuit 1 for amplifying the sample / hold output with a variable gain.
5, 16 and detection circuits 17, 18 for integrating the AGC outputs in time, and the detection outputs for comparison with a predetermined reference voltage Vref, and the comparison outputs are used as gain control signals for the AGC circuits 15, 16. Comparator 1
It is composed of 9 and 20.

In the signal processing circuit 12 having the above configuration, the detection circuits 17 and 18 temporally integrate the video signal portion in the output signals of each of the two channels within a predetermined period, for example, one field (or one frame). Then, an integrating means for obtaining the average value (integral value) of the video signal portion is configured. In a general image, the average signal level of the field (or frame) of each channel is almost the same.
Therefore, in the output system of each channel, if there is no variation in the gain among the channels, the output signals of the channels will be at substantially the same level.

Here, the signal processing when the gain varies among the channels will be described. When the gain becomes unbalanced between the channels, the detection circuit 1
A level difference occurs between the average signals (integrated values) detected at 7 and 18, and as shown in FIG. 2, the level difference (density difference in the drawing) occurs at the outputs (a) and (b) of each channel. Occurs. Originally, this average signal level should be almost the same level. Therefore, in the present embodiment, the reference voltage Vref at the time of gain adjustment is set commonly for each channel.

As a result, even if the gain varies among the channels, the average signal level of the field (or frame) of each channel is detected by the detection circuits 17, 1.
8 and each average signal level has a common reference voltage Vre
f is compared with the comparators 19 and 20, respectively, and the gain control of the AGC circuits 15 and 16 is performed according to the level difference between them. Thus, by comparing the average signal level of each channel with the common reference voltage Vref and feeding back the gain control, it is possible to match the gain between the channels. As a result, variations in gain occur in the 2-channel output system of the CCD solid-state imaging device 11, and even if there is a level difference between the outputs (a) and (b) as shown in FIG. 2, the signal processing circuit 12 At
A good reproduced image (c) can be obtained by performing gain matching between the channels.

FIG. 3 is a block diagram showing another embodiment of the present invention applied to a CCD solid-state image pickup device for color images. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. There is. A color solid-state CCD solid-state image sensor has a structure in which a color filter is superimposed on each of the two-dimensionally arranged pixels to obtain color information in a form multiplexed with luminance information. An example of the color arrangement of the color filter array is shown in FIG. In this color arrangement, G (green) that is close to the luminance signal that requires high resolution is arranged in a checkerboard pattern, and B (blue) and R (red) that do not require relatively high resolution are arranged in a checkerboard pattern in the rest. It is said to be a green checkered system that is arranged in the following manner. The application of the present embodiment is not limited to this green checkered method. However, the condition is that the same color must exist in each line.

In the case of the color filter of the green checkered system, the signal processing circuit 12 'according to the present embodiment has the configuration shown in FIG.
In addition to the constituent elements of the previous embodiment shown in FIG. 1, a sample for color separation for sampling / holding the information of G in the output signal of the channel ch1 passing through the AGC circuit 15 and supplying the output to the detection circuit 17. / Hold circuit 21 and A
G in the output signal of channel ch2 that has passed through the GC circuit 16
Information is sampled / held and its output is detected by the detection circuit 1
Sample / hold circuit 2 for color separation supplied to 8
2 and 2 are newly provided.

According to this configuration, the detection circuits 17 and 18 detect the average signal level of the field (or frame) of each channel with respect to the G information sampled / held by the sample / hold circuits 21 and 22. Therefore, if there is no variation in gain among the channels, the average signal level of each channel will be approximately the same level. On the other hand, when the gain varies among the channels, the information of G is sampled / held, the average value (integral value) is taken, and the average signal of each channel is obtained as in the case of the previous embodiment. By comparing the level with the common reference voltage Vref and feeding back the gain control, the gain can be matched between the channels.

[0025]

As described above, according to the present invention,
In a general image, paying attention to the fact that the average signal levels of fields (or frames) are almost the same, the video signal portions in the output signals of a plurality of channels are integrated within a predetermined period, and the respective integrated values are calculated. By injecting the signal charge for the pilot signal for gain matching by comparing with the common reference voltage between each channel and controlling the gain of the output system of multiple channels according to the comparison result for each channel. Since it is not necessary, gain matching between channels can be reliably achieved with a simple circuit configuration, and cost reduction and failure rate reduction can be achieved by reducing parts. Moreover, since variations in the characteristics of the circuit components can be canceled, it is possible to reduce the number of steps for component selection and the adjustment cost.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention applied to an interline transfer type CCD solid-state imaging device.

FIG. 2 is an operation explanatory diagram of the present invention.

FIG. 3 is a block diagram showing another embodiment of the present invention applied to a CCD solid-state image sensor for color images.

FIG. 4 is a diagram showing a green checkered color filter array.

FIG. 5 is an operation explanatory diagram of a conventional example.

FIG. 6 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 sensor part 2 vertical transfer register 4, 5 horizontal transfer register 7, 8 charge detection part 11 CCD solid-state image sensor 12, 12 'signal processing circuit 15, 16 AGC circuit 17, 18 detection circuit 19, 20 comparator

Claims (2)

[Claims] 1. A signal processing circuit for processing an output signal of each channel of a solid-state imaging device having an output system of a plurality of channels, wherein a video signal portion in each output signal of the plurality of channels is integrated within a predetermined period. Integrating means, comparing means for comparing the integrated value of each of the plurality of channels with a common reference voltage between the respective channels, and gain of the output system of the plurality of channels according to the comparison output for each channel of the comparing means. A signal processing circuit for a solid-state image sensor, comprising: 2. A signal processing method for processing an output signal of each channel of a solid-state imaging device having an output system of a plurality of channels, wherein a video signal portion in each output signal of the plurality of channels is integrated within a predetermined period. Then, the integrated value of each of the plurality of channels is compared with a common reference voltage between the respective channels, and the gain of the output system of the plurality of channels is controlled according to the comparison result of each channel. Signal processing method of device.