JPH08125703A - Data transmission method and electronic device or semiconductor device using the same - Google Patents

Abstract

PURPOSE: To reduce transmission waveform distortion and to perform highly reliable data transmission by making the timings of the rise and fall of the sine waves of the same period as the clock signals of the sine wave voltage of a fixed period earlier or later than the clock signals. CONSTITUTION: A transmission LSI is provided with a transmission circuit and a reception LSI is provided with a reception circuit. The transmission circuit converts the clocks Ckt. of pulse waves to the sine waves, converts data Dt1 expressed by NRZ codes to PSK waves for which the timing of the rise or the fall of the sine waves is shifted and outputs them to a Ck1 and a D1 . In the reception circuit, the received clocks Ck2 of the sine waves and data D2 of the PSK waves are demodulated to the clocks Ckr2 of the pulse waves and the data Dr2 of the NRZ codes. For the waveforms of the Ck1 and the D1 , phases are matched at the rise from a set voltage Vref , however, the phases are different at the fall. By the timing difference, '1' or '0'is discriminated and the data transmission is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission method and an input / output circuit of a semiconductor device, and more particularly to a circuit system suitable for inputting / outputting a highly reliable high frequency signal.

[0002]

2. Description of the Related Art In recent years, the speed of LSIs (Large Scale Integrated Circuits) has been increasing, and the operating frequency of microprocessors is 100M.
Those exceeding Hz have been realized. Synchronous DRA that operates at 100MHz or more even in memory LSI
M (Dynamic Random Access Memory) has been reported.

As described above, although speeding up is progressing at the LSI chip level, in electronic devices such as WS (workstation) and PC (personal computer) that use these LSIs, at the board level where the LSI is mounted. It is becoming difficult to accelerate. The cause is as follows.

Conventionally, in electronic devices such as WS and PC,
Pulse transmission using a non-return-zero (NRZ) code is used for digital signal transmission between LSIs. That is, the transmission circuit transmits a binary voltage pulse, for example, a relatively high voltage represents 1 and a relatively low voltage represents 0. When the wavelength of the harmonic component contained in this pulse wave is shortened to the same level as the wiring on the board, the wiring behaves as a distributed constant line, and the signal is at the wiring end or branch,
Since significant reflection occurs in the parasitic inductance and the parasitic capacitance of the LSI package, waveform distortion such as ringing occurs in the transmission waveform. This disturbance in the waveform reduces the reliability of data transmission, making it difficult to increase the speed.

As an example, two L's shown in FIG.
A case where signals are transmitted (one-to-one transmission) between SIs will be described. FIG. 17B shows this equivalent circuit. Two LSIs are connected to both ends of the transmission line TL. LSI
-M21 has an internal circuit and a transmission circuit T21. L
The SI / M22 has an internal circuit and a receiving circuit R22. Further, a package lead frame, a bonding wire, and the like exist between the LSI and the transmission line, and these have a parasitic capacitance and a parasitic inductance. In order to model this, a parasitic inductance L and a parasitic capacitance C are inserted between the connection portions of IO21 and IO22 and the transmission line. Although the case where the input / output terminals are independent is shown here, when the input / output terminals are common, the parasitic capacitance of the terminals becomes large, and therefore the waveform is more disturbed.

FIG. 18 shows a circuit conventionally used as a transmission circuit in pulse transmission. This circuit has an output stage,
It comprises a drive circuit for the PMOS transistor and the NMOS transistor in the output stage, and an output control circuit. IV11 in the figure
To IV15 indicate inverter circuits, NAND2
Indicates a NAND circuit, and NOR indicates a NOR circuit. When the DOE signal is low level (Vss), the output control circuit puts the output terminal OUT in a high impedance state regardless of the value of the signal at the input terminal IN. When DOE is high level, the same signal as IN is output to OUT. In general, I
The size of the transistor in the internal circuit in the previous stage of N is small,
Since the size of the transistor in the output stage is large, an inverter array in which the size of the transistor is gradually increased is used as the drive circuit.

Next, a simulation result of a transmission waveform when this circuit is used as the transmission circuit T21 of FIG. 17B will be shown. In the simulation shown below, the following conditions are used unless otherwise specified. As for the power supply voltage, Vdd is 1.5V and Vss is 0V. The transmission line has a characteristic impedance of 50Ω and a length of 2 cm. The end is V
tt is 0.75V and Rtt is 50Ω. L of the package was 10 nH and C was 5 pF. The output resistance of the output circuit is set to about 22Ω, and an amplitude of ± 0.4V is obtained for a load of 25Ω.

FIG. 19 shows a simulation waveform. M
21 shows waveforms at the transmission end IO21 and the reception end IO22 when a rectangular wave having a period of 10 ns is transmitted from 21. this is,
This means that data 0, 1, 0, 1 is transferred at a cycle of 5 ns. Reflection at the transmitting end and the receiving end is large, and large ringing occurs. The margin with respect to Vref at the minimum point of the waveform due to ringing at the rising edge of the signal is 0.2.
2V, which is 55% of the 0.4V amplitude on one side. If this minimum point falls below Vref,
The receiving circuit erroneously determines that it has received two pulses. Therefore, a small margin means low reliability when transmitting a high-speed signal.

The disturbance of the waveform due to the multiple reflection becomes more remarkable in the bus transmission. In electronic devices such as WS and PC, the memory LSI is often used in the module configuration shown in FIG. In this case, the signal transmission method between the elements is 1 as shown in the equivalent circuit of FIG.
This is a bus transmission in which many elements are connected to a book transmission line. Here, M31 to M38 represent LSI chips, and
It is connected to the transmission line at intervals of cm. The terminal end of the transmission line is connected to the terminal power supply Vtt by a terminal resistance Rtt. Let M31 be a transmitting chip and M32-M38 be a receiving chip. Although the internal configurations of M32 to M38 are all the same, only the internal configuration of M38 is shown in the figure. Here, the case where the input / output terminals are independent is shown, but when the input / output terminals are common, the parasitic capacitance of the terminals increases, so that the waveform is more disturbed.

Next, a simulation result of a transmission waveform when pulse transmission is performed by using the transmission circuit of FIG. 18 as the transmission circuit T31 of FIG. 20 (b) is shown. M3
Transmission end I when a rectangular wave with a period of 1 to 10 ns is transmitted
FIG. 21 shows the waveforms at O31 and the receiving ends IO32, IO35, and IO38. Large ringing occurs in the received waveform. Although Vref is shown as 0.75V, Vr at the minimum point of the waveform due to ringing at the rising edge of the signal
The margin for ef is only 0.09V. This is 22% of the 0.4 V amplitude on one side. This is because multiple reflection occurs due to parasitic components of the LSI connected in the middle of the bus and branching of the bus.

As described above, when the pulse transmission by the NRZ code is used in the data transmission between the LSIs in the electronic equipment such as WS and PC, the reduction of the margin in the high frequency region becomes a problem.

A data transmission method between LSIs using pulse phase modulation is described in International Sol.
id-State Circuits Confere
nce (ISSCC) Digest of Tech
natural Papers, pp. 108-109.

On the other hand, various modulation transmissions other than pulse transmission by the NRZ code are known as techniques for digital data transmission. Phase shift keying (PSK), which is one of them, uses a sine wave as a carrier wave, for example, 0 when the phase is advanced and 1 when the phase is delayed.
Represents the data as. Regarding this PSK, for example, "Concept of oscillation / modulation / demodulation circuit, second edition"
(Norio Koshiba, Yoshinori Ueda, Ohmsha, 1991), pages 146-147.

22 and 23 are a block diagram of the PSK modulation circuit shown in the same document and timing charts showing its operation. In the figure, φs0 and φs1 are voltage sources that output a sine wave, and have different phases to represent 0 and 1. This is switched by the data signal Dt1 and output to D1. Here, SW1 is ON when Dt1 is 1,
OFF when 0, SW0 OFF when Dt1 is 1,
Turns on when it is 0. Therefore, Dt1 is 0 in D1.
, Φs0 is output, and when Dt1 is 1, φs0 is output.
s1 is output.

The problem with this circuit is that a voltage discontinuity occurs at the output D1 when the phases are switched, as shown in FIG. At this point, the output contains higher harmonics than the clock frequency. As will be described later, this causes a disturbance in the transmission waveform and causes a decrease in the reliability of transmission.

It has also been proposed to use PSK for data transmission between LSIs. (Nikkei Microdevice, September 1994 issue, page 105)

[0017]

As described above, W
In electronic devices such as S and PC, 100MH between LSI
When a high-speed pulse of z or higher is transmitted, the transmission waveform is disturbed in a system such as a bus in which branching and multiple reflection of a signal due to a parasitic element cannot be avoided. The cause is described below. A rectangular wave used as a signal in pulse transmission using the NRZ code contains many harmonic components having a frequency that is an integral multiple of the fundamental frequency, in addition to the fundamental frequency. For example, cycle 100
In addition to the basic frequency of 100 MHz for the square wave of MHz, 3
Frequency components such as 00 MHz and 500 MHz are included. On the other hand, in the parasitic element and the branch of the transmission line, reflection and phase delay occur in each harmonic, but the reflectance and the phase delay have frequency dependence. That is, the harmonics contained in the transmitted wave are reflected according to their respective frequencies. Therefore, the reflected wave contains harmonics with a different ratio and phase relationship from the transmitted wave. As a result, the received waveform does not become a strict rectangular wave, and disturbance occurs.

Therefore, the problem of pulse transmission by the NRZ code conventionally used for data transmission between LSIs is that the transmission waveform thereof contains a lot of harmonic components having a frequency higher than the fundamental frequency which determines the data transmission rate. To be out. Therefore, an object of the present invention is to provide a data transmission method in which the ratio of harmonic components included in a transmission waveform is suppressed to a minimum in the inter-LSI data transmission in electronic equipment such as WS and PC, and the disturbance of the transmission waveform is reduced. It is to provide a semiconductor device or an electronic device using the above data transmission method.

[0019]

In order to achieve the above object, in a typical embodiment of the present invention, the first voltage to the second voltage are provided at a phase of 0 ° with a constant time period.
Voltage waveform of a rectangular wave that switches from the second voltage to the first voltage at a predetermined phase, and switches from the first voltage to the second voltage when the phase is 360 °. And a clock signal having the same period as the clock signal, switching from the third voltage to the fourth voltage when the phase is 0 °, and the fourth voltage before or after the predetermined phase. To the above-mentioned third voltage, and at a phase of 360 °, a data signal having a rectangular wave voltage waveform that switches from the above-mentioned third voltage to the above-mentioned fourth voltage is cut off from harmonics above a specific frequency. Which are simultaneously transmitted through the low-pass filter, and the first output waveform of the low-pass filter corresponding to the clock signal has a waveform oscillating between a fifth voltage and a sixth voltage and corresponds to the data signal. The second output waveform of the low-pass filter is a waveform that oscillates between a seventh voltage and an eighth voltage, and after receiving the first output waveform and the second output waveform, A timing at which the first output waveform changes from the first set voltage set between the fifth voltage and the sixth voltage to the first set voltage via the fifth voltage, and And a timing at which the second output waveform changes from the second set voltage set between the seventh voltage and the eighth voltage to the second set voltage via the sixth voltage. The data transmission method is characterized in that binary data is discriminated according to the context.

By adjusting the frequency cut off by the low-pass filter, the first output waveform becomes a waveform like a sine wave, but it is not an accurate sine wave. But,
In terms of suppressing harmonic components, the same effect as that obtained when a sine wave is used as a carrier is ideally obtained. Hereafter, the sine wave means a waveform like a sine wave. By adjusting the frequency at which the second output waveform is also cut off by the low-pass filter, the sine wave is changed from the second set voltage set between the seventh voltage and the eighth voltage to the sixth set voltage. The timing at which the voltage reaches the second set voltage again via the above voltage has a waveform shifted back and forth.

Further, as a semiconductor device for realizing the above-mentioned data transmission method, an internal circuit and a transmission circuit having the low-pass filter for outputting to the outside of the chip in response to an internal signal from the internal circuit are provided on the chip. Then, the transmitter circuit outputs the first signal having the first output waveform and the second signal.
And a second signal having an output waveform of

Further, as a semiconductor device for realizing the above data transmission method, it has a receiving circuit for receiving the first signal and the second signal and an internal circuit on a chip, and the receiving circuit is the first circuit. It is assumed that a rectangular wave is output to the internal circuit in response to this signal and the second signal.

Further, the above data transmission method is used between a plurality of semiconductor devices of an electronic device.

[0024]

First, in the data transmission method according to the present invention, the harmonic content contained in the transmission waveform is smaller than that of the rectangular wave. Therefore, with respect to the transmitted waveform, even if multiple reflection occurs in a branch of a transmission line or a parasitic element, the waveform is less disturbed than a rectangular wave.

Second, it is easy to adjust the timing in the receiving circuit. In this transmission method, binary data is represented by the difference between the rising and falling timings of the clock and the data. Therefore, even if multiple reflections occur on the transmission line, if the clock and data transmission lines have the same conditions,
Since the clock signal and the data signal are similarly reflected, the timing difference is transmitted while being preserved.

For these reasons, the use of the data transmission method according to the present invention enables highly reliable and high-speed data transmission.

Further, the semiconductor device which realizes the above-described data transmission method can accurately transmit information at a high operating frequency.

Furthermore, by using the above data transmission method between a plurality of semiconductor devices of an electronic device, information transmission of the entire electronic device can be performed at high speed.

[0029]

【Example】

[First Embodiment] A first embodiment of the present invention will be described below with reference to the drawings. In the following, the terminal name also serves as the signal name at the terminal.

Phase shift keying (PSK) is shown in FIG.
The figure showing the principle of is shown. It is assumed that the two LSIs in FIG. 1A perform data transmission. The clock transmission terminal Ck1 of the transmission LSI and the clock reception terminal Ck2 of the reception LSI are connected by a transmission line. Similarly, the data transmission terminal D1 of the transmission LSI and the data reception terminal D2 of the reception LSI are also connected by a transmission line.

In this figure, two LSs are provided in one transmission line.
Although the case of the one-to-one transmission in which I is connected is shown, the present transmission method can also be applied to the bus transmission in which two or more LSIs are connected to one transmission line. In either case, the two transmission lines have substantially the same electrical characteristics, wiring patterns, and loads.

Although only one data transmission line is shown here, even when transmitting a plurality of data in parallel, since only one clock signal is required, a plurality of data transmission lines can be used. Only one clock transmission line is required.

The transmitter LSI includes a transmitter circuit, and the receiver LSI includes a receiver circuit. The transmission circuit converts the pulse wave clock Ckt1 and the data Dt1 represented by the NRZ code into a sine wave as a clock and data as a PSK wave with the timing of the falling or rising of the sine wave shifted, respectively, and Ck1 and D1. Output to. The receiving circuit demodulates the received sine wave clock Ck2 and PSK wave data D2 into pulse wave clock Ckr2 and NRZ code data Dr2.

FIG. 1B shows a conceptual diagram of the waveforms of Ck1 and D1. The two have the same phase at the rising edge from the set voltage Vref, but have a phase at the falling edge, that is, V again.
The phase of ref is different. Data transmission is performed at the falling edge of Ck1. That is, the data is transmitted when the falling timing of D1 is "0" when it is earlier than the falling timing of Ck1 and when it is later than "1".

FIG. 1C shows an example in which data is transmitted at both the rising and falling edges of the clock. When the phase of Ck1 and D1 is shifted at both the rising and falling timings of Ck1
Data is transmitted with 0 "and" 1 "when it is slow. In this case, the data transfer rate is doubled as compared with FIG. 1B.

Further, the falling phases of Ck1 and D1 are aligned, the rising phases are shifted forward and backward, and the rising timing of D1 is "0" when it is earlier than the rising timing of Ck1 and when it is later. It is also possible to transmit data by setting "1".

Vref can be set for each of Ck2 and D2 in the receiving circuit described later.
If the set voltages for both are the same, the design of the receiving circuit becomes easy. Further, if the set voltage for both is set at the center of vibration of both, a large margin can be secured.

These transmission methods have the following advantages.

First, the PSK wave has few harmonic components.
Since the sine wave remains the sine wave even if the phase is shifted, the waveform is not disturbed even if multiple reflection occurs in a transmission line branch or a parasitic element in the bus. The PSK wave has a falling edge or a rising edge and is slightly deviated from the sine wave, and thus contains some harmonics, but its proportion is smaller than that of the pulse wave. Therefore, as described in the conventional example, the disturbance of the received waveform is caused by the difference in the reflection of the fundamental wave and the harmonic or the way of receiving the phase shift. Therefore, the disturbance of the received waveform of the PSK wave is larger than that of the pulse wave. Few.

Second, it is easy to adjust the timing in the receiving circuit. In this method, "1" and "0" are represented by the difference between the falling timing and the rising timing of the clock and the data. Therefore, even if multiple reflections occur on the transmission line, if the clock and data transmission lines are subjected to the same conditions, the clock and data are reflected in the same manner, so that the difference in timing is transmitted while being preserved.

A configuration example of the data transmission method using the sine wave and the PSK wave of FIG. 1B as carrier waves will be described below.
As in the voltage waveform of (c), Vre
PSK with rising and falling phases shifted from f
A data transmission method using waves as a carrier wave and the above-described data transmission method can be realized with the same configuration.

FIG. 2 shows a block diagram of the transmission circuit. The transmission circuit is a pulse phase modulation (PPM) circuit, output buffer 2
And two low-pass filters. here,
When transmitting a plurality of data signals simultaneously, only one clock output buffer and one low-pass filter are required.

The operation of the transmission circuit will be described with reference to FIG.
The clock Ckt1 and the data Dt1 represented by the NRZ code are input to the PPM circuit. Dt1 changes at the rising edge of Ckt1. The output Dpt1 of the PPM circuit is a pulse wave, which rises at the same timing as Ckt1 at the rising edge of Ckt1 and falls at a timing different from Ckt1 at the falling edge. When Dt1 is "0", Dp
The falling timing of t1 is earlier than Ckt1, and Dt
When 1 is "1", the falling timing of Dpt1 is later than Ckt1.

Ckt1 and Dpt1 are input to the output buffers respectively for driving the external load. The pulse transmission circuit shown in FIG. 18 can be used for the output buffer. The pulse wave output from the output buffer has its harmonic components cut by the low-pass filter, and the clock Ck1 is output.
Becomes a sine wave, and the data D1 becomes a PSK wave.

FIG. 4 shows a circuit diagram of the PPM circuit included in FIG. The operation of this circuit will be described with reference to FIG. PP
Ckt1 and Dt1 are input to the M circuit. Ckt1 is input to the delay circuit and generates pulse waves φ0 and φ1 having the same frequency as Ckt1 but different phases. φ0 is "0"
, And φ1 is used to create an edge of "1", and the delay amount of each delay circuit is adjusted by the voltage applied to the control terminals P0 and P1. P
The PM wave Dpt1 is generated by performing the following logical operation with the above four signals.

Dpt = Dt1. (Ckt1 + φ1)
+ / Dt1 · Ckt1 · φ0 Here, / Dt1 represents a negative signal of Dt1. Also, FIG.
IV1 is an inverter circuit, NAND1 is a NAND circuit, 3NAND is a 3-input NAND circuit, and ORNAND is an ORNAND circuit. The OR NAND circuit has an input A,
The calculation of / (A · (B + C)) is performed on B and C.

FIG. 6A shows an example of the circuit configuration of the low-pass filter included in FIG. By setting the cutoff frequency to be about 1.5 times the frequency of the clock, it is possible to convert the pulse wave clock into a sine wave and the PPM wave data into a PSK wave.

Further, as shown in FIG. 6 (b), the low-pass filter of FIG. 2 can be composed of active elements. Here, Reg1 is a variable resistor composed of a MOS transistor. Source of the MOS transistor
One end of the drain path is connected to the IN terminal and the other end is connected to the resistor Reg2 and the capacitor C4.
The resistance value between the source and drain of the MOS transistor can be controlled by applying the control voltage Vcon2 to the gate of the transistor. In this case, when the frequency of the transmission data changes, the control voltage Vco from the outside of the chip
By changing the resistance value of the variable resistor Reg1 with n2, the cutoff frequency can be changed to an appropriate value.

Further, the low pass filter of FIG.
It may be outside of I. In this case, the cutoff frequency can be freely selected by exchanging the filter.

In this modulation method, there is no discontinuity in voltage when switching phases, and it is possible to ideally suppress harmonics.

FIG. 7 shows a block diagram of the receiving circuit. The reception circuit is composed of two input buffers and a demodulation circuit. Here, when a plurality of data signals are simultaneously received, the output buffer for clock and the low-pass filter are set to 1
I need only one. The operation of the receiving circuit will be described with reference to FIG.
FIG. 9 shows a circuit diagram of the input buffer. The input signal IN is compared with Vref by the differential amplifier circuit, amplified, and further amplified by the inverters IV2 and IV3. As a result, Ckr2 and Dpr2 become pulse waves, and the rising and falling edges thereof coincide with the time when Ck2 and D2 pass Vref.

The demodulation circuit has a pulse wave Ck2 and a PPM wave Dp.
r2 is input and the data is demodulated to NRZ code. The demodulation circuit is composed of a two-stage latch circuit as shown in FIG. Here, IV4-IV8 are inverters. Ck
When r2 is high level, latch 1 is through and D
Although the signal of pr2 passes through to Ce, since the latch 2 is in the latched state, the previous data is still output to Dr2. When Ckr2 changes from the high level to the low level, the latch 1 latches the data of Dpr2 at that moment and Ce
Since the latch 2 is in the through state, the data of the latch 1 is output to Dr2. Therefore, the data of Dpr2 latched at the falling edge of Ckr2 is continuously output to the output Dr2 of the demodulation circuit for the next one cycle. This is NRZ as shown in FIG.
This is the data demodulated into codes. The demodulated data is delayed by a half cycle with respect to the original data Dt1 shown in FIG.

Next, the effect of this embodiment will be described with reference to the drawings.

FIG. 11 shows a model for one-to-one transmission by the data transmission method of this embodiment. Transmission LSI / M
The clock transmission terminal Ck1 of No. 1 and the clock reception terminal Ck2 of the reception LSI M2 are connected by a transmission line.
A parasitic element of the package exists between these terminals and the transmission line. Similarly, M1 data transmission terminals D1 and M2
The data receiving terminal D2 of is also connected by a transmission line. The end of the transmission line is terminated at Vtt by a terminating resistor. T1 is the transmitting circuit shown in FIG. 2, and R2 is the receiving circuit shown in FIG.

FIG. 12 shows a simulation waveform of each signal shown in FIG. The simulation conditions are the same as in FIG. 17 of the conventional example. In order to make the data transmission rate the same, the clock frequency is set to 200 MHz in FIG. Dpt1 is the output of the PPM circuit as shown in FIG. 2, but is modulated as in FIG.

At the transmitting end, sinusoidal Ck1 and PSK wave D2 are obtained. Also at the receiving ends Ck2 and D2,
The waveform is not disturbed, and the phase relationship between the clock and data is maintained. It can be seen that the waveforms Ckr2 and Dr2 of the receiving circuit are also demodulated as in FIG.

Therefore, according to the data transmission method of the present invention, it becomes possible to perform high-speed data transmission with little waveform distortion in one-to-one transmission between LSIs.

Next, FIG. 13 shows a model for performing bus transmission by the data transmission method of this embodiment. Where M
Reference numeral 11-M18 represents an LSI chip, and the clock terminal and the data terminal are connected to independent transmission lines. The terminal end of the transmission line is connected to the terminal power supply Vtt by a terminal resistance Rtt. M11 is a transmission LSI, M12
-M18 is a receiving LSI. Although the internal configurations of M12-M18 are all the same, only the internal configuration of M15 is shown in the figure.

M11 includes the transmission circuit T11 shown in FIG. M12-M18 includes R12-R18 having the same circuit configuration as the receiving circuit shown in FIG.

In FIG. 14, of the signals shown in FIG. 13, the transmission LSI M11 and the reception LSIs M12 and M1 are shown.
5 shows simulation waveforms of signals at M18. The demodulated signal shows waveforms Ckr15 and Dr15 at M15. The simulation conditions are the same as in FIG. 19 of the conventional example. In order to make the data transmission rate the same, the clock frequency is set to 200 MHz in FIG.

At the transmitting end and each receiving end, the transmission waveform is not disturbed, and the phase relationship between the clock and the data is maintained. It can be seen that the waveforms Ckr15 and Dr15 of the receiving circuit are also demodulated as in FIG.

Therefore, according to the data transmission method of the present invention, it is possible to perform high-speed data transmission with little waveform distortion even in the inter-LSI bus transmission.

The same effect can be obtained by disposing the low-pass filter outside the transmission LSI and transmitting the output from the transmission LSI to the reception LSI via the low-pass filter.

[Embodiment 2] FIG. 15 is a block diagram of a transmission circuit showing a second embodiment of the present invention. Here, FIG.
As shown in the timing chart of No. 6, the data signal D1
The signal / D1 having the opposite phase change is transmitted at the same time. A circuit similar to that of the first embodiment can be used as the receiving circuit, and by inputting / D1 to the terminal corresponding to Ck2 in FIG. 7 and latching D1, it is possible to demodulate to the NRZ code.

Attention is paid to the harmonics contained in the modulated signal. In the first embodiment, as shown in FIG. 3, the modulation signal D1 has a different cycle compared to Ck1. The greater the deviation of this cycle, the more harmonic components are contained in the transmission signal.

Further, pay attention to the phase relationship between the data signal and the signal that latches it. The larger this value, the larger the margin when the data is latched in the receiving circuit and the higher the reliability.

Let Δφ be the relative phase difference between the falling edges of Ck1 and D1 in FIG. 3 of the first embodiment. Since only the signal D1 is modulated in the first embodiment, the deviation of the period of the sine wave of D1 is Δφ itself. On the other hand, in Example 2, D1 and /
In order to make the relative phase difference of D1 Δφ, both signals may be shifted in the opposite direction by Δφ / 2. Therefore, the deviation of the cycle from both sine waves is Δφ / 2.
According to this method, harmonics contained in the transmission signal can be further suppressed. In FIG. 16, the relative phase difference between D1 and / D1 is Δφ when the phase is 180 °, but the same effect can be obtained even when the relative phase difference between D1 and / D1 is Δφ when the phase is 0 °. can get.

The same effect can be obtained even if the relative phase difference between the rising edges of Ck1 and D1 is Δφ.

The low-pass filter shown in FIG. 15 can also be composed of active elements. For example, it is possible to use the low-pass filter including the active element shown in FIG. 6B described in the first embodiment.

The low pass filter of FIG.
It may be outside the SI. In this case, the cutoff frequency can be freely selected by exchanging the filter.

Using the data transmission method of this embodiment, LS
A one-to-one transmission model between I or a bus transmission model can be configured similarly to the model described in the first embodiment.

[0072]

As described above, when the data transmission method according to the present invention is used, even if the frequency of the transmission wave is increased, the harmonic component contained in the transmission wave is suppressed to the minimum as compared with the pulse transmission. Even if branching of the transmission path with respect to the transmission waveform or multiple reflections due to parasitic elements or the like occur, the disturbance of the transmission waveform can be reduced. Further, by using the data transmission method according to the present invention for high-speed bus transmission between LSIs or one-to-one transmission, even if branching of a bus or multiple reflections due to parasitic elements or the like occur, it is possible to reduce the disturbance of the transmission waveform, which is reliable High-speed data transmission is possible.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of an embodiment of the present invention.

FIG. 2 is a block diagram of a transmission circuit of the present invention.

FIG. 3 is a timing chart showing the operation of the circuit of FIG.

FIG. 4 is a circuit diagram of a pulse phase modulation circuit included in the transmission circuit of the present invention.

5 is a timing chart showing the operation of the circuit of FIG.

FIG. 6 is a circuit configuration example of a low-pass filter included in the transmission circuit of the present invention.

FIG. 7 is a block diagram of a receiving circuit of the present invention.

8 is a timing chart showing the operation of the circuit of FIG.

FIG. 9 is a circuit diagram of an input buffer included in the receiving circuit of the present invention.

FIG. 10 is a circuit diagram of a demodulation circuit included in the receiving circuit of the present invention.

FIG. 11 is a model of one-to-one transmission according to the present invention.

FIG. 12 is a transmission / reception waveform of one-to-one transmission according to the present invention.

FIG. 13 is a model of bus transmission according to the present invention.

FIG. 14 is a transmission / reception waveform of bus transmission according to the present invention.

FIG. 15 is a block diagram of a transmission circuit according to a second embodiment of the present invention.

16 is a timing chart showing the operation of the circuit of FIG.

FIG. 17 is a model of one-to-one transmission.

FIG. 18 shows a conventional transmission circuit for pulse transmission.

FIG. 19 is a transmission / reception waveform of conventional one-to-one transmission by pulse transmission.

FIG. 20 is a model of an LSI module and bus wiring.

FIG. 21 is a transmission / reception waveform of bus transmission by conventional pulse transmission.

FIG. 22 is a block diagram of a conventional PSK modulation circuit.

FIG. 23 is a timing chart showing the operation of the circuit of FIG. 22.

[Explanation of symbols]

M1, M2, M11, M12, M13, M14, M1
5, M16, M17, M18, M21, M22, M3
1, M32, M33, M34, M35, M36, M3
7, M38 ... LSI T1, T11, T21, T31, Ti ... Transmission circuit R2, R18, R22, R38 ... Reception circuit Ckt1, Ckr2, Ckt11, Ckr15, Ck
1, Ck2, Ck11, Ck15, Dt1, Dr2, D
t11, Dr15, D1, D2, D11, D15, Dp
t1, Dpr2, DOE, P0, P1, φ0, φ1, I
N, OUT, Ce, IO21, IO22, IO31, I
O38 ... Node L, L1 ... Inductance C, C1, C2, C3, C4, C5 ... Capacitance Reg1 ... Variable resistance consisting of active elements Reg2 ... Resistor OP1 ... Differential amplifier TL ... Transmission line Mp1, Mp2 , Mp4, Mp5, Mp6, Mp7, M
p11 ... P-channel MOS transistor Mn1, Mn2, Mn3, Mn4, Mn5, Mn6, M
n7, Mn11 ... N-channel MOS transistors IV1, IV2, IV3, IV4, IV5, IV6, I
V7, IV8, IV11, IV12, IV13, IV1
4, IV15, IV20, IV21 ... Inverter circuit φs0, φs1 ... Sine wave voltage source SW0, SW1 ... Switch NAND1, NAND2 ... NAND circuit NOR ... NOR circuit 3NAND ... 3-input NAND circuit ORNAND ... ORNAND circuit Vdd, Vss, Vtt ... Power supply Vref ... Reference voltage Vcon, Vcon2 ... Control voltage Rtt ... Termination resistance.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshinobu Nakagome 1-280, Higashi Koigokubo, Kokubunji, Tokyo Metropolitan Research Center, Hitachi, Ltd.

Claims (41)

[Claims] 1. A switch from a first voltage to a second voltage at a phase of 0 °, which has a constant time period, and switches from the second voltage to the first voltage at a predetermined phase. ,
From the first voltage to the second voltage at a phase of 360 °
And a clock signal having a rectangular wave voltage waveform that switches to the above voltage and having the same period as the above clock signal, and switching from the third voltage to the fourth voltage when the phase is 0 °, and the above predetermined phase. And a data signal having a rectangular wave voltage waveform that switches from the fourth voltage to the third voltage, and switches from the third voltage to the fourth voltage at a phase of 360 °. Are simultaneously transmitted through a low-pass filter that cuts off harmonics above a specific frequency, and the first output waveform of the low-pass filter corresponding to the clock signal has a period of a fixed time and a fifth voltage and a sixth voltage. The second output waveform of the low-pass filter corresponding to the data signal has the same period as the first output waveform and has a seventh voltage and an eighth voltage. Between After the oscillating waveform is received and the first output waveform and the second output waveform are received, the first output waveform is set between the fifth voltage and the sixth voltage. And the second output waveform is set between the seventh voltage and the eighth voltage at the timing when the first set voltage is returned to the first set voltage via the fifth voltage again. A data transmission method, wherein binary data is discriminated according to the context of the timing at which the second set voltage is changed to the second set voltage again via the seventh voltage. 2. The first set voltage is set in the middle of the fifth voltage and the sixth voltage, and the second set voltage is set between the seventh voltage and the eighth voltage. The data transmission method according to claim 1, wherein the data transmission method is set to an intermediate value. 3. The data transmission method according to claim 1, wherein the first set voltage and the second set voltage are the same voltage. 4. A first voltage is switched to a second voltage when the phase is 0 ° and which has a constant time period, and is switched from the second voltage to the first voltage at a predetermined phase. ,
From the first voltage to the second voltage at a phase of 360 °
And a clock signal having a rectangular voltage waveform that is switched to the voltage of 4 and having the same period as the clock signal, and the phase is switched from the third voltage to the fourth voltage before or after 0 °. From the fourth voltage to the third voltage in a predetermined phase
To a low-pass filter that cuts off harmonics of a specific frequency or higher, and a data signal having a rectangular waveform that switches from the third voltage to the fourth voltage when the phase is 360 °. Through the low-pass filter corresponding to the clock signal.
Has a fixed time period and oscillates between the fifth voltage and the sixth voltage. The second output waveform of the low-pass filter corresponding to the data signal is the first waveform. A waveform having the same period as the output waveform and oscillating between the seventh voltage and the eighth voltage is formed, and after receiving the first output waveform and the second output waveform, the first waveform is received. When the output waveform of the second output waveform is the first set voltage set between the fifth voltage and the sixth voltage, and the second output waveform is the seventh voltage and the eighth voltage. 2 in relation to the timing at which the second set voltage set between
A data transmission method characterized by determining value data. 5. The first set voltage is set between the fifth voltage and the sixth voltage, and the second set voltage is set between the seventh voltage and the eighth voltage. The data transmission method according to claim 4, wherein the data transmission method is set to an intermediate value. 6. The data transmission method according to claim 4, wherein the first set voltage and the second set voltage are the same voltage. 7. A switch from a first voltage to a second voltage at a phase of 0 °, which has a constant time period, and switches from the second voltage to the first voltage at a predetermined phase. ,
From the first voltage to the second voltage at a phase of 360 °
And a clock signal having a rectangular wave voltage waveform that switches to the above voltage, and that has the same period as the clock signal and switches from the third voltage to the fourth voltage before or after the phase of 0 °. , 360 ° before or after the 180 ° phase, switching from the fourth voltage to the third voltage.
And a data signal composed of a rectangular wave voltage waveform that switches from the third voltage to the fourth voltage before or after the phase of, are simultaneously transmitted through a low-pass filter that blocks harmonics of a specific frequency or higher, The first output waveform of the low-pass filter corresponding to the clock signal has a period of a fixed time and oscillates between a fifth voltage and a sixth voltage, and the low-pass corresponding to the data signal. The second output waveform of the filter has the same period as the first output waveform and has a waveform that oscillates between the seventh voltage and the eighth voltage. And a timing at which the first output waveform becomes a first set voltage set between the fifth voltage and the sixth voltage, and the second output waveform. Is between the seventh voltage and the eighth voltage Set data transmission method characterized in that to determine the binary data in the context of the second set becomes the voltage timing. 8. The first set voltage is set at an intermediate point between the fifth voltage and the sixth voltage, and the second set voltage is set between the seventh voltage and the eighth voltage. The data transmission method according to claim 7, wherein the data transmission method is set to an intermediate value. 9. The data transmission method according to claim 7, wherein the first set voltage and the second set voltage are the same voltage. 10. A semiconductor device comprising an internal circuit for outputting an internal signal indicating a first state and a second state and a transmission circuit for transmitting the internal signal to the outside of the chip on a chip, wherein the transmission circuit is provided. Has a period of a certain time, and switches from the first voltage to the second voltage when the phase is 0 °, switches from the second voltage to the first voltage at a predetermined phase, and At 360 °, a clock signal having a rectangular wave voltage waveform that switches from the first voltage to the second voltage and the internal signal are input, and in response to the internal signal, the same clock signal as the clock signal is input. It has a cycle and switches from the third voltage to the fourth voltage when the phase is 0 °, and the fourth voltage is applied before or after the predetermined phase.
Voltage is switched to the above third voltage and the phase is 360
A modulation circuit that outputs a data signal having a rectangular wave voltage waveform that switches from the third voltage to the fourth voltage at a temperature of °, and a harmonic of the clock signal and the output signal of the modulation circuit that is equal to or higher than a specific frequency. A semiconductor device comprising: a low-pass filter that blocks waves. 11. A semiconductor device comprising an internal circuit for outputting an internal signal indicating a first state and a second state and a transmission circuit for transmitting the internal signal to the outside of the chip on a chip, wherein the transmission circuit is provided. Has a period of a certain time, and switches from the first voltage to the second voltage when the phase is 0 °, switches from the second voltage to the first voltage at a predetermined phase, and At 360 °, a clock signal having a rectangular wave voltage waveform that switches from the first voltage to the second voltage and the internal signal are input, and in response to the internal signal, the same clock signal as the clock signal is input. Has a period, and a phase switches from a third voltage to a fourth voltage before or after 0 °, switches from the fourth voltage to the third voltage at the predetermined phase, and has a phase of 360 Is the third voltage at ° A modulation circuit that outputs a data signal having a rectangular wave voltage waveform that switches to the fourth voltage, and a low-pass filter that blocks harmonics of a specific frequency or more of the clock signal and the output signal of the modulation circuit are provided. A semiconductor device comprising: 12. A semiconductor device having an internal circuit for outputting an internal signal indicating a first state and a second state and a transmission circuit for transmitting the internal signal to the outside of the chip on a chip, wherein the transmission circuit is provided. Has a period of a certain time, and switches from the first voltage to the second voltage when the phase is 0 °, switches from the second voltage to the first voltage at a predetermined phase, and At 360 °, a clock signal having a rectangular wave voltage waveform that switches from the first voltage to the second voltage and the internal signal are input, and in response to the internal signal, the same clock signal as the clock signal is input. Has a cycle and switches from the third voltage to the fourth voltage before or after the phase of 0 °, and from the fourth voltage to the third voltage before or after the phase of 180 °. Switching, rather than 360 ° phase A modulation circuit that outputs a data signal having a rectangular wave voltage waveform that switches from the third voltage to the fourth voltage before or after, and a harmonic higher than a specific frequency of the clock signal and the output signal of the modulation circuit. And a low-pass filter for blocking the semiconductor device. 13. The semiconductor device according to claim 10, wherein the low-pass filter comprises an active element, and the cutoff frequency can be adjusted by a control voltage. 14. The semiconductor device according to claim 11, wherein the low-pass filter comprises an active element, and the cutoff frequency can be adjusted by a control voltage. 15. The semiconductor device according to claim 12, wherein the low-pass filter comprises an active element, and the cutoff frequency can be adjusted by a control voltage. 16. An internal circuit that outputs an internal signal indicating a first state and a second state, and a cycle having a fixed time, and a phase from 0 ° to a second voltage from a first voltage. A clock having a rectangular waveform that switches from the second voltage to the first voltage at a predetermined phase, and switches from the first voltage to the second voltage at a phase of 360 °. An output circuit that outputs a signal to the outside of the chip,
The clock signal and the internal signal are input, and in response to the internal signal, the clock signal has the same period as the clock signal, and switches from the third voltage to the fourth voltage when the phase is 0 °, The fourth phase before or after the predetermined phase
Voltage is switched to the above third voltage and the phase is 360
A semiconductor device having on a chip a modulation circuit for outputting a data signal having a rectangular wave voltage waveform that switches from the third voltage to the fourth voltage at a position outside the chip; and the output of the semiconductor device. An electronic device, comprising: a circuit and an output of the modulation circuit, and an electronic device including a transmission circuit having a low-pass filter for cutting off harmonics of a specific frequency or higher of the input. 17. An internal circuit for outputting an internal signal indicating a first state and a second state, and a period having a constant time, and a phase from 0 ° to a second voltage when the phase is 0 °. A clock having a rectangular waveform that switches from the second voltage to the first voltage at a predetermined phase, and switches from the first voltage to the second voltage at a phase of 360 °. An output circuit that outputs a signal to the outside of the chip,
The clock signal and the internal signal are input, and in response to the internal signal, the clock signal has the same period as the clock signal and the phase changes from the third voltage to the fourth voltage before or after 0 °. It is composed of a rectangular-wave voltage waveform that switches from the fourth voltage to the third voltage at the predetermined phase, and switches from the third voltage to the fourth voltage at a phase of 360 °. A semiconductor device having a modulation circuit for outputting a data signal to the outside of the chip on a chip, and outputs of the output circuit and the modulation circuit of the semiconductor device are input, and a harmonic wave having a frequency higher than a specific frequency of the input is cut off And an electronic device including a transmission circuit having a low-pass filter. 18. An internal circuit which outputs an internal signal indicating a first state and a second state, and a cycle of a constant time, and when the phase is 0 °, the first voltage is changed to the second voltage. A clock having a rectangular waveform that switches from the second voltage to the first voltage at a predetermined phase, and switches from the first voltage to the second voltage at a phase of 360 °. An output circuit that outputs a signal to the outside of the chip,
The clock signal and the internal signal are input, and in response to the internal signal, have the same period as the clock signal, and the third voltage to the fourth voltage before or after the phase of 0 °. Switching to voltage, switching from the fourth voltage to the third voltage before or after the 180 ° phase, switching from the third voltage to the fourth voltage before or after the 360 ° phase. A semiconductor device having, on the chip, a modulation circuit for outputting a data signal composed of a rectangular wave voltage waveform to be exchanged to the outside of the chip, and outputs of the output circuit and the modulation circuit of the semiconductor device are input, and the input is specified. An electronic device comprising a transmission circuit having a low-pass filter that cuts off higher harmonics than a frequency. 19. The electronic device according to claim 16, wherein the low-pass filter includes an active element, and a cutoff frequency can be adjusted by a control voltage. 20. The electronic device according to claim 17, wherein the low-pass filter includes an active element, and a cutoff frequency can be adjusted by a control voltage. 21. The electronic device according to claim 18, wherein the low-pass filter includes an active element, and a cutoff frequency can be adjusted by a control voltage. 22. An output of the semiconductor device according to claim 10, the semiconductor device according to claim 13, the electronic device according to claim 16, or the electronic device according to claim 19 is received. In a semiconductor device having a receiving circuit and an internal circuit that outputs an internal signal indicating a first state and a second state on a chip, the receiving circuit receives the output of the device and has a cycle of a fixed time. And switching from the first voltage to the second voltage when the phase is 0 °, switching from the second voltage to the first voltage at a predetermined phase, and the first voltage when the phase is 360 °. A clock signal having a rectangular wave voltage waveform that switches from a voltage of 1 to the second voltage has the same period as the clock signal, and has a phase of 0.
At the angle of °, switch from the third voltage to the fourth voltage,
From the voltage waveform of the rectangular wave that switches from the fourth voltage to the third voltage before or after the predetermined phase, and switches from the third voltage to the fourth voltage when the phase is 360 °. And a demodulation circuit that receives the output of the input buffer and outputs a rectangular wave that switches between the fifth voltage and the sixth voltage to the internal circuit in response to the input. A semiconductor device comprising. 23. An output of any one of the semiconductor device according to claim 11, the semiconductor device according to claim 14, the electronic device according to claim 17, or the electronic device according to claim 20 is received. In a semiconductor device having a receiving circuit and an internal circuit that outputs an internal signal indicating a first state and a second state on a chip, the receiving circuit receives the output of the device and has a cycle of a fixed time. And switching from the first voltage to the second voltage when the phase is 0 °, switching from the second voltage to the first voltage at a predetermined phase, and the first voltage when the phase is 360 °. A clock signal having a rectangular wave voltage waveform that switches from a voltage of 1 to the second voltage has the same period as the clock signal, and has a phase of 0.
Before or after °, the third voltage is switched to the fourth voltage, and at the predetermined phase, the fourth voltage is switched to the third voltage. When the phase is 360 °, the third voltage is switched.
Input buffer for outputting a data signal having a rectangular wave voltage waveform that switches from the voltage of 4 to the fourth voltage, and the output of the input buffer is input, and in response to the input, the fifth voltage and the sixth voltage And a demodulation circuit that outputs a rectangular wave that switches to the voltage of 1 to an internal circuit. 24. An output of the semiconductor device according to claim 12, the semiconductor device according to claim 15, the electronic device according to claim 18, or the electronic device according to claim 21 is received. In a semiconductor device having a receiving circuit and an internal circuit that outputs an internal signal indicating a first state and a second state on a chip, the receiving circuit receives the output of the device and has a cycle of a fixed time. And switching from the first voltage to the second voltage when the phase is 0 °, switching from the second voltage to the first voltage at a predetermined phase, and the first voltage when the phase is 360 °. A clock signal having a rectangular wave voltage waveform that switches from a voltage of 1 to the second voltage has the same period as the clock signal, and has a phase of 0.
Before or after °, the third voltage is switched to the fourth voltage, and before or after the predetermined phase, the fourth voltage is switched to the third voltage, and the phase is before 360 °. Alternatively, an input buffer that outputs a data signal having a rectangular wave voltage waveform that switches from the third voltage to the fourth voltage later, and an output of the input buffer are input, and a fifth signal is generated in response to the input. And a demodulation circuit that outputs a rectangular wave that switches to the sixth voltage to a sixth voltage to an internal circuit. 25. A semiconductor device according to claim 10, a semiconductor device according to claim 13, an electronic device according to claim 16, or an electronic device according to claim 19, and a device according to claim 22. An electronic device comprising the semiconductor device according to claim 1 and using the data transmission method according to claim 1. 26. A semiconductor device according to claim 11, a semiconductor device according to claim 14, an electronic device according to claim 17, or an electronic device according to claim 20, and a device according to claim 23. An electronic device, comprising: the semiconductor device according to claim 2; wherein the data transmission method according to claim 2 is used. 27. A semiconductor device according to claim 12, a semiconductor device according to claim 15, an electronic device according to claim 18, or an electronic device according to claim 21, and a device according to claim 24. An electronic device, comprising: the semiconductor device according to claim 3; wherein the data transmission method according to claim 3 is used. 28. The semiconductor device according to claim 22, wherein the semiconductor device has a period of a constant time and a first phase at 0 °.
Voltage is switched to the second voltage, and the second voltage is switched to the first voltage at a predetermined phase, and the phase is 3
A clock signal having a rectangular voltage waveform switching from the first voltage to the second voltage at 60 ° and the internal signal are input, and in response to the internal signal, the same period as the clock signal. And the third voltage is switched to the fourth voltage when the phase is 0 °, and the fourth voltage is switched to the third voltage before or after the predetermined phase, and the phase is 360 degrees. A modulation circuit that outputs a data signal having a rectangular wave voltage waveform that switches from the third voltage to the fourth voltage at a temperature of °, and a harmonic of the clock signal and the output signal of the modulation circuit that is equal to or higher than a specific frequency. A semiconductor device further comprising a transmission circuit having a low-pass filter for blocking a wave. 29. The semiconductor device according to claim 23, wherein the semiconductor device has a period of a fixed time and a first phase at a phase of 0 °.
Voltage is switched to the second voltage, and the second voltage is switched to the first voltage at a predetermined phase, and the phase is 3
A clock signal having a rectangular voltage waveform switching from the first voltage to the second voltage at 60 ° and the internal signal are input, and in response to the internal signal, the same period as the clock signal. And the phase switches from the third voltage to the fourth voltage before or after 0 °, switches from the fourth voltage to the third voltage at the predetermined phase, and has a phase of 360 °. By the way, a modulation circuit that outputs a data signal having a rectangular wave voltage waveform that switches from the third voltage to the fourth voltage, and a harmonic of a specific frequency or more of the clock signal and the output signal of the modulation circuit. A semiconductor device further comprising a transmission circuit having a low-pass filter for cutting off the noise. 30. The semiconductor device according to claim 24, wherein the semiconductor device has a period of a fixed time and a first phase at 0 °.
Voltage is switched to the second voltage, and the second voltage is switched to the first voltage at a predetermined phase, and the phase is 3
A clock signal having a rectangular voltage waveform switching from the first voltage to the second voltage at 60 ° and the internal signal are input, and in response to the internal signal, the same period as the clock signal. And switching the phase from a third voltage to a fourth voltage before or after 0 °, and from the fourth voltage to a third voltage before or after the predetermined phase, A modulation circuit that outputs a data signal having a rectangular wave voltage waveform that switches from the third voltage to the fourth voltage when the phase is 360 °, and a specific frequency of the clock signal and the output signal of the modulation circuit. A semiconductor device further comprising a transmission circuit having a low-pass filter that blocks the above harmonics. 31. An electronic device comprising a plurality of semiconductor devices according to claim 28 and using the data transmission method according to claim 1. 32. An electronic device comprising a plurality of semiconductor devices according to claim 29 and using the data transmission method according to claim 2. 33. An electronic device comprising a plurality of semiconductor devices according to claim 30 and using the data transmission method according to claim 3. 34. A semiconductor device according to claim 22, wherein the semiconductor device has a period of a constant time and a first phase at a phase of 0 °.
Voltage is switched to the second voltage, and the second voltage is switched to the first voltage at a predetermined phase, and the phase is 3
An output circuit for outputting a clock signal composed of a rectangular wave voltage waveform switching from the first voltage to the second voltage at 60 ° to the outside of the chip, the clock signal and the internal signal are input, It has the same period as the clock signal in response to the internal signal, switches from the third voltage to the fourth voltage when the phase is 0 °, and the fourth voltage is applied before or after the predetermined phase. From the voltage above the third
And a modulation circuit for outputting a data signal having a rectangular wave voltage waveform that switches from the third voltage to the fourth voltage at a phase of 360 ° to the outside of the chip. And an electronic device including a transmission circuit having a low-pass filter that cuts off harmonics of a specific frequency or higher of the input, to which the outputs of the transmission circuit and the modulation circuit of the semiconductor device are input. And electronic device. 35. The semiconductor device according to claim 23, wherein the semiconductor device has a period of a constant time and a first phase at 0 °.
Voltage is switched to the second voltage, and the second voltage is switched to the first voltage at a predetermined phase, and the phase is 3
An output circuit for outputting a clock signal composed of a rectangular wave voltage waveform switching from the first voltage to the second voltage at 60 ° to the outside of the chip, the clock signal and the internal signal are input, In response to the internal signal, it has the same cycle as the clock signal, and the phase switches from the third voltage to the fourth voltage before or after 0 °,
A data signal having a rectangular wave voltage waveform that switches from the fourth voltage to the third voltage at the predetermined phase and switches from the third voltage to the fourth voltage at a phase of 360 ° is generated. A semiconductor device further comprising a modulation circuit for outputting to the outside of the chip, and a low-pass filter for inputting outputs of the transmission circuit and the modulation circuit of the semiconductor device and for blocking harmonics of a specific frequency or higher of the input. And an electronic device including the transmission circuit having the electronic device. 36. The semiconductor device according to claim 24, wherein the semiconductor device has a period of a fixed time and a first phase at a phase of 0 °.
Voltage is switched to the second voltage, and the second voltage is switched to the first voltage at a predetermined phase, and the phase is 3
An output circuit for outputting a clock signal composed of a rectangular wave voltage waveform switching from the first voltage to the second voltage at 60 ° to the outside of the chip, the clock signal and the internal signal are input, In response to the internal signal, it has the same cycle as the clock signal, and the phase switches from the third voltage to the fourth voltage before or after 0 °,
From the voltage waveform of the rectangular wave that switches from the fourth voltage to the third voltage before or after the predetermined phase, and switches from the third voltage to the fourth voltage when the phase is 360 °. A semiconductor device further including a modulation circuit for outputting the data signal to the outside of the chip, and outputs of the transmission circuit and the modulation circuit of the semiconductor device are input, and a harmonic wave having a frequency higher than a specific frequency of the input is cut off. And an electronic device including a transmission circuit having a low-pass filter. 37. An electronic device comprising a plurality of electronic devices according to claim 34 and using the data transmission method according to claim 1. 38. An electronic device comprising a plurality of the electronic devices according to claim 35, and using the data transmission method according to claim 2. 39. An electronic device comprising a plurality of the electronic devices according to claim 36 and using the data transmission method according to claim 3. 40. The first voltage is switched to the second voltage when the phase is 0 °, which has a constant time period, and is switched from the second voltage to the first voltage at a predetermined phase. , Having the same period as the clock signal composed of a rectangular wave voltage waveform that switches from the first voltage to the second voltage when the phase is 360 °, and from the third voltage to the third voltage when the phase is 0 °. 4 and then switches from the fourth voltage to the third voltage before or after the predetermined phase, and switches from the third voltage to the fourth voltage at a phase of 360 °. The first data signal, which has a rectangular voltage waveform that alternates, has the same period as the clock signal, and the first data signal has the third voltage from the third voltage before the predetermined phase. When switching to the voltage of Switch from the fifth voltage to the sixth voltage, switch from the sixth voltage to the fifth voltage after the predetermined phase, and switch from the fifth voltage to the above at a phase of 360 °. It is composed of a rectangular voltage waveform that switches to a sixth voltage, and the first data signal is changed from the fourth voltage to the third voltage after the predetermined phase.
When the phase is 0 °, the fifth voltage is switched to the sixth voltage, and the sixth voltage is switched to the fifth voltage before the predetermined phase. , A second data signal having a rectangular wave voltage waveform that switches from the fifth voltage to the sixth voltage at a phase of 360 ° is passed through a low-pass filter that blocks harmonics of a specific frequency or higher. A first of the low-pass filters that transmits at the same time and corresponds to the first data signal.
Has a waveform oscillating between the seventh voltage and the eighth voltage, and the second output waveform of the low pass filter corresponding to the second data signal is the ninth voltage and the tenth voltage. After the first output waveform and the second output waveform are received, the first output waveform is a waveform oscillating between a voltage and the second output waveform. The timing at which the first set voltage set between them becomes the first set voltage again via the seventh voltage, and the second output waveform becomes the ninth voltage and the tenth voltage. In the context of the timing at which the second set voltage is set again during the period from the second set voltage via the ninth voltage to the second set voltage again.
A data transmission method characterized by determining value data. 41. A first voltage is switched to a second voltage when the phase is 0 °, which has a constant time period, and is switched from the second voltage to the first voltage at a predetermined phase. , Having the same period as the clock signal having a rectangular wave voltage waveform that switches from the first voltage to the second voltage at the phase of 360 °, and the third period before or after the phase of 0 °. The voltage is switched to the fourth voltage, the fourth voltage is switched to the third voltage at the predetermined phase, and the third voltage is switched to the fourth voltage when the phase is 360 °. First composed of rectangular wave voltage waveform
And the clock signal, the first data signal has a phase of 0 when the third voltage switches to the fourth voltage before the phase of 0 °. After 5 °, the fifth voltage is switched to the sixth voltage, the sixth phase is switched to the fifth voltage at the predetermined phase, and the fifth voltage is switched at a phase of 360 °. To a sixth voltage, the phase of the first data signal is 0 °.
When the third voltage is switched to the fourth voltage later, the phase is switched from the fifth voltage to the sixth voltage before 0 °, and the sixth voltage is switched at the predetermined phase. To a fifth voltage, and a second data signal having a rectangular waveform that switches from the fifth voltage to the sixth voltage when the phase is 360 ° and a second data signal with a harmonic of a specific frequency or higher. The first output waveform of the low-pass filter corresponding to the first data signal is a waveform oscillating between a seventh voltage and an eighth voltage, which are simultaneously transmitted through a low-pass filter for blocking a wave. The second output waveform of the low-pass filter corresponding to the second data signal has a waveform oscillating between the ninth voltage and the tenth voltage, and the first output waveform and the second output waveform After receiving the output waveform and The timing when the force waveform becomes the first set voltage set between the seventh voltage and the eighth voltage, and the second output waveform becomes the ninth voltage and the tenth voltage. The data transmission method is characterized in that binary data is discriminated according to the context of the timing of reaching the second set voltage set during the period.