JPH08125202A - Rarallel optical link - Google Patents

Abstract

PURPOSE: To provide a parallel optical link which easily achieves high-speed parallel transmission of a plurality of light signals, has a high transmission quality and is compact. CONSTITUTION: In a transmission link 1, a digital signal processing circuit substrate 10 where a skew compensation/code conversion circuit is formed, an analog signal processing circuit substrate 20 where an LD drive circuit 21 is formed, and an LD/fiber array module 30 connected to a light ribbon fiber 7 are arranged and connected in this order before being housed and sealed into a case 1-1. In a reception link 4, a PD/fiber array module 40 connected to the light ribbon fiber 7, an analog signal processing circuit substrate 50 where an amplification circuit 51 and a limiter amplification circuit 52 are formed, and a digital signal processing circuit substrate 60 where a skew compensation/code conversion circuit 61 is formed are arranged and connected in this order before being housed and sealed in a case 4-1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical parallel link for transmitting a plurality of optical signals in parallel, and more particularly to an optical parallel link for connecting within a communication device, between racks or a short distance such as a computer device. Regarding links.

In recent years, with the increase in the capacity of transmission signals between communication devices, there has been a need for wiring between intra-frame and intra-frame such as a transmission terminal device, ATM (asynchronous transmission mode) switch, and signal transmission between computer devices. Requires a throughput of about (100 Mb / s x N channels), which is difficult to handle with conventional electrical parallel transmission engagement using coaxial cables. Therefore, optical parallel signals using optical cables with parallel optical fibers are used. Is dealt with by.

In a trunk optical parallel link, a long distance (40 km
After a weak optical signal has been transmitted, it is converted into a signal level that can be processed by the digital processing unit in the analog processing unit.

Further, in order to cope with an increase in signal level variation due to long-distance transmission, an increase in timing deviation, etc., an APC (Automatic Power Controller) is used in the transmission link.
AGC (Automatic Gain Controller) function on the transmission link
Functions and retiming functions are provided.

On the other hand, an optical parallel link for connecting a short distance (about 400 m or less) such as a communication equipment rack, a rack, or a computer device is compared with a trunk optical parallel link.
There is a strong demand for cost reduction with a simple circuit configuration.

Meanwhile, when considering the improvement of the transmission speed, in the optical parallel link, the skew (propagation delay time difference) between each channel is a factor that prevents the speedup.
The skew between the channels is caused by the light emission delay of the LD, the skew due to the variation in the pattern length difference of the circuit board on which the LSIs of the transmission link and the reception link are mounted, and the strain stress of each optical fiber core wire of the optical cable as the optical transmission line. There is a skew caused by the variation in the refractive index.

[0007]

2. Description of the Related Art A conventional optical parallel link for connecting short distances will be described with reference to FIGS.

A conventional optical parallel link is shown in FIGS.
As shown in FIG. 3, a transmission link 100 that receives an electric signal from the input line 1-10, converts the electric signal into an optical signal, and outputs the optical signal,
Receives optical signals, converts them to electrical signals and outputs electrical signals. Output line 4-10
The receiving link 400 sent from the optical ribbon fiber 7
It was connected with.

The transmission link 100 includes an LD drive circuit 21 and an LD.
The array 31 and the optical fiber array 32 are arranged and connected in this order, housed in a case 1-1, and hermetically sealed. The receiving link 400 has an optical fiber array 41, a PD array 42, an amplifier circuit 51, a limiter amplifier circuit 52, and a D-type flip-flop circuit 63 arranged in this order and housed in a case 4-1, and hermetically sealed. It is a thing.

Here, LD means a light emitting element such as a semiconductor laser, and PD means a light receiving element such as a high speed photodiode. The transmission link 100 will be described in detail below.

The LD drive circuit 21 is formed on a circuit board (ceramic board or the like) (hereinafter referred to as the analog signal processing circuit board 20).
The analog signal processing circuit board 20M is a carrier.
Mounted on the surface of 25M, carrier 25M is metal base 110
It is installed in.

Input line 1-10 and analog signal processing circuit board
The 20M are connected via a bonding wire. LD array 31 in which LDs are arranged in a horizontal row on the base 31
Is a carrier near the analog signal processing circuit board 20M.
It is mounted on 25M, and the LD array 31 and the analog signal processing circuit board 20 are connected via a bonding wire.

The optical fiber array 32 is an optical ribbon fiber.
A ferrule is attached to a terminal of 32 A (the number of core wires is, for example, 10 cores). The ferrule includes a lower half substrate made of silicon or the like having V grooves arranged on the upper surface at an equal pitch, and an upper half substrate pressed and fixed to the lower half substrate.

The optical fiber array 32 is constructed by separating the ends of the optical ribbon fiber 32A into respective optical fiber cores and inserting and fixing the optical fiber cores in the corresponding V grooves of the ferrule.

The LD to which the incident end face of the optical fiber core wire corresponds
Fiber optic array so that it is close to the output surface of the
32 is mounted on the metal base 110. The optical ribbon fiber 32A of the optical fiber array 32 is connected to the optical ribbon fiber 7 through the optical connector 7-1, and the other end of the optical ribbon fiber 7 is connected through the other optical connector 7-2.
It is connected to the optical ribbon fiber 41A of the optical fiber array 41 on the reception link 400 side.

As shown in FIG. 23, the optical fiber array 41 includes an optical ribbon fiber 41A (for example, the optical fiber core wire is
It is a 10-core terminal with a ferrule attached. The ferrule includes a lower half substrate made of silicon or the like having V grooves arranged on the upper surface at an equal pitch, and an upper half substrate pressed and fixed to the lower half substrate.

The optical fiber array 41 is constructed by separating the ends of the optical ribbon fiber 41A into respective optical fiber core wires and inserting and fixing the optical fiber core wires into the corresponding V grooves of the ferrule.

PD in which PDs are arranged in a horizontal row on a base
The array 42 is mounted on the carrier 55M in proximity to the optical fiber array 41 so that the light-receiving surface of each PD approaches and optically couples to the emission end surface of the optical fiber core wire of the optical fiber array 41 facing each other. .

The amplifier circuit 51 and the limiter amplifier circuit 52 are formed on a circuit board (ceramic substrate or the like) (hereinafter referred to as an analog signal processing circuit board 50M), and the analog signal processing circuit board 50M faces the PD array 42. Adjacently, it is mounted on the surface of the carrier 55M, and the carrier 55M is mounted on the metal base 410.

The PD array 42 and the amplifier circuit 51 are connected via a bonding wire. The D-type flip-flop circuit 63 is formed on a circuit board (ceramic substrate) (hereinafter referred to as a digital signal processing circuit board 60M), and the digital signal processing circuit board 60M faces the analog signal processing circuit board 50M and is close to the analog signal processing circuit board 50M. It is mounted on the surface of carrier 55M.

The D-type flip-flop circuit 63 and the limiter amplifier circuit 52 are connected via a bonding wire, and the D-type flip-flop circuit 63 and the output line 4-10 are connected via a bonding wire.

Since the optical parallel link is configured as described above, when data is input from the input line 1-10 to each LD drive circuit 21, the LD drive circuit 21 converts the input data into electric / optical data. Each LD is made to emit and quench.

The optical signal emitted from each LD passes through each optical fiber core of the LD array 31 and each optical fiber core of the optical ribbon fiber 7, and then the optical fiber array of the receiving link 400.
It is transmitted to 41.

In the receiving link 400, the PD array 42 optically / electrically converts the optical signal transmitted from each optical fiber core wire.
Then, the photoelectrically converted weak signal is equivalently amplified by each amplifier circuit, and further, the limiter amplifier circuit 52 limits the preamplifier output so as to be input to the discriminator with a constant signal amplitude.

Then, 1/0 discrimination is performed by a discriminator (which conventionally employs a D-type flip-flop circuit 63), and the result is transmitted to the output line 4-10. As described above, the optical ribbon fiber that connects the transmission link and the reception link has good characteristics that the skew (propagation delay time difference) between the optical fiber cores is small.

For example, the skew of an optical ribbon fiber of 10 cores (single mode optical fiber core wire) is 0.3 ns / 100 m
Is reported. (R. Matuoka et al., "Measuring
for Ribbon Fiber Skew ", Technical Report of IEICE
OCS92-32) The above-mentioned optical parallel link is intended for low cost by removing the clock extraction and retiming functions, simplifying the circuit configuration, and assuming low-speed line transmission.

The details of the conventional optical parallel link will be described below with reference to FIGS. As shown in FIG. 24, a conventional circuit board, for example, an analog signal processing circuit board
20M (eg ceramic substrate) is an F-Ni-Co alloy (
Solder (Solder 18) is mounted on a carrier 25M made of copper (trade name) or copper / tungsten alloy. Au film 17-1 on the back surface of analog signal processing circuit board 20M
And the Au film 17-2 on the entire peripheral surface of the carrier 25M.
To improve the adhesive strength of the solder 18.

As shown in FIG. 25, since the analog signal processing circuit board 50M and the digital signal processing circuit board 60M are connected by wire bonding, the power supply pad 71-1 is provided along the side edge of the digital signal processing circuit board 60M. Power supply pads 71-1 are arranged, and power supply pads 71-2 are formed along the side edge of the analog signal processing circuit board 50M so as to face the power supply pads 71-1 and heat the bonding wires between both power supply pads. Connected by crimping.

On the other hand, the signal pads 72-1 are arranged along the side edges of the digital signal processing circuit board 60M, and face the signal pads 72-1 along the side edges of the analog signal processing circuit board 50M. Signal pads 72-2 are formed in an array, and bonding pads are connected by thermocompression bonding between both signal pads.

As shown in FIG. 26, the LD array (similar to the PD array) and the analog signal processing circuit board are connected by, for example, LD on the analog signal processing circuit board 20M on which the LD driving LSI 90Z is mounted. Drive LSI 90Z
The signal pad 94a is provided corresponding to the signal electrode 91, and another signal pad 94b connected to the signal pad 94a via a pattern is provided at the side edge of the analog signal processing circuit board 20M.

The signal electrode 91 of the LD driving LSI 90Z and the signal pad 94a are connected via a bonding wire, and the other signal pad 94b and the electrode of the LD array 31 are connected via a bonding wire. Connected.

Also, the analog signal processing circuit board 20M is provided corresponding to the power / ground electrode 92 of the LD driving LSI 90Z.
A power / ground pad 93 is provided on the upper side, and the power / ground electrode 92 and the power / ground pad 93 are connected via a bonding wire.

As shown in FIG. 27, a signal pad 94 formed on the analog signal processing circuit board 20M on the transmission side.
A damping resistor is placed between a and the other signal pad 94b.
95-1 is inserted and mounted so that a large current does not flow momentarily to the LD.

On the other hand, as shown in FIG. 28, the pads 24 are provided on the circuit board, for example, the analog signal processing circuit board 20M, and the entire surface of the analog signal processing circuit board 20M except the surface of the pads 24 is protected by polyimide. It is covered with a layer 29 to protect the analog signal processing circuit board 20M.

The surfaces of these pads 24 are plated with Ni-Au to improve the reliability of connection of the bonding wires. However, in order to prevent the parts other than the pads 24 from being plated, FIG. (B), the entire surface of the analog signal processing circuit board 20M excluding the surface of the pad 24 is previously covered with the plating resist 24Z.

As shown in FIG. 29, a bare chip 90 mounted on a circuit board, for example, an analog signal processing circuit board 50M.
Are separated into a first channel area, a second channel area, a third channel area, ... 90-1, 90-2, 90-3 ,. Has a power supply electrode and a ground electrode.

On the other hand, an elongated rectangular power source pattern 96-1A and an earth pattern 96-1B are provided on the surface of the analog signal processing circuit board 50M. And the power supply pattern 96-1A
Power supply pads 93A are formed in an array so as to be connected to the side edge of the power supply pad, and the power supply pads 93A and the power supply electrodes are connected via bonding wires.

Further, ground pads 93 are formed in an array so as to be connected to the side edge of the ground pattern 96-1B, and the ground pads 93B and the ground electrode are connected via a bonding wire.

As shown in FIG. 30, the surface of the analog signal processing circuit board 50M, for example, corresponds to the power electrode 92D, the ground electrode 92G, and the signal electrode 91 arranged on the bare chip 90 mounted on the circuit board. A strip-shaped power supply pad 93D, a ground pad 93G, and a signal pad 94 each made of a thick film are provided in the.

The power supply pad 93D, the ground pad 93G and the signal pad 94 are connected to the inner layer pattern via the via 97.

[0041]

Although the conventional optical parallel link has been downsized and reduced in cost by simplifying the circuit configuration as described above, it has an electric / optical conversion function and an optical / optical conversion function.
The electrical conversion function is mainly used, and no special consideration has been given to the skew countermeasures except that the optical ribbon fiber is adopted.

As described above, the skew of the optical ribbon fiber is 0.3 ns / 100 m × 300 m = 0.9 ns when the transmission distance is 300 m.

On the other hand, since the electronic circuits of the transmission link and the reception link are configured as shown in FIGS. 24 to 30, there is a concern that the skew may be large and the speedup may be hindered, and the transmission quality may be deteriorated. I was afraid to do it.

Conventionally, as described with reference to FIG. 24, since the circuit board is soldered and mounted by covering the entire peripheral surface of the carrier with the Au film, the solder flows out to the side surface of the carrier and the adjacent circuit is connected. There is a possibility that the distance from the substrate or the like becomes large, and as a result, the length of the bonding wire to be connected becomes long and the skew becomes large.

Conventionally, as described with reference to FIG. 25, since the signal pads are arranged close to each of the circuit boards connected through the bonding wires, the bonding wires are arranged close to each other. There was a risk of crosstalk.

Conventionally, as described with reference to FIG. 26, a signal pad connected to a signal electrode of a bare chip via a bonding wire and an LD on an analog signal processing circuit board.
Alternatively, another signal pad connected to the electrode of the PD via another bonding wire is provided, and both signal pads are connected via a pattern.

Therefore, the bare chip and LD (or P
There has been a problem that the connection line length between D) becomes large and the speedup is hindered. Conventionally, as described with reference to FIG. 27, a damping resistor is mounted on the surface of the analog signal processing circuit board on the transmission side. Therefore, the damping resistance is separated from the LD driving LSI, which may lead to deterioration of the characteristics of the damping resistance.

Further, conventionally, as shown in FIG. 28, the entire surface of the circuit board except the pad surface is covered with a protective polyimide layer. As a result, when the plating layer is provided on the pad surface, a crack K is generated in the plating resist portion corresponding to the corner of the protective polyimide layer, and the plating solution penetrates into the crack K to the corner of the protective polyimide layer. Metal fragments may precipitate.

Further, there is a problem that the metal piece remains on the circuit board 2 side even after the plating resist is removed, peels off during operation and adheres to a pad or the like. Conventionally, as shown in FIG. 29, an elongated rectangular power source pattern and a ground pattern common to each channel are provided on the surface of a circuit board.

Therefore, there is a possibility that the power supply and the ground are not completely separated and crosstalk occurs between the channels. Conventionally, as shown in FIG. 30, a strip-shaped power supply pad, a grounding pad and a signal pad made of a thick film are arranged close to each other on the surface of a circuit board. Such a thick film pad is formed by screen printing means, but when the width of the thick film pad is 150 μm or less, the printing medium around the window is lifted so as to adhere to the mask when the mask is removed.

As a result, both side edges of the surface of the thick film pad are projected and the central portion becomes a recessed pad, which may reduce the strength of wire bonding connection. Since the electronic circuits of the conventional transmission link and reception link are formed as described above, the skew is about 1 ns.

Therefore, in the conventional optical parallel link using the optical ribbon fiber with the skew of 0.9 ns / 300 m, the speed that can be identified by the flip-flop circuit with the setup and hold time of 1 ns is limited to about 200 Mb / s, and the high-speed optical parallel link is possible. There was a problem that transmission was hindered.

The present invention was created in view of the above points, and it is easy to realize high-speed optical parallel transmission and has high transmission quality.
It is also intended to provide a compact optical parallel link.

[0054]

In order to achieve the above object, the present invention receives an electric signal from an input line 1-10, converts it into an electric signal and outputs an optical signal as shown in FIG. In the optical parallel link in which the transmission link 1 for receiving the optical signal and the reception link 4 for receiving the optical signal and converting the signal to the electric signal through the output line 4-10 are connected by the optical ribbon fiber 7, the transmission link 1 is The digital signal processing circuit board 10 on which the skew compensation / code conversion circuit 11 is formed, the analog signal processing circuit board 20 on which the LD drive circuit 21 is formed, and the LD / fiber array module 30 connected to the optical ribbon fiber 7.
And are arranged and connected in this order and housed and sealed in the case 1-1. The reception link 4 includes the optical ribbon fiber 7
A PD / fiber array module 40 connected to the analog signal processing circuit board 50 on which an amplifier circuit 51 and a limiter amplifier circuit 52 are formed, and a skew compensation / code conversion circuit
It is assumed that the digital signal processing circuit board 60 on which 61 is formed is arranged and connected in this order and housed and sealed in the case 4-1.

As illustrated in FIG. 8, the analog signal processing circuit board 50 is formed by forming a copper polyimide board 50-2 on the surface of a ceramic board 50-1, and the digital signal processing circuit board 60 is It shall consist of glass ceramics. Further, as illustrated in FIG. 8, the analog signal processing circuit board 50 is adhesively mounted on the upper surface of the carrier 55 via the high melting point bonding agent 58-A, and the carrier 55 is bonded via the low melting point bonding agent 58-B. Adhesively mounted on the bottom plate of Case 4-1, or fixedly mounted on the bottom plate of Case 4-1, by screw means, the digital signal processing circuit board 60 is attached to the upper surface of another carrier 65 with a high melting point bonding agent 68-A. The carrier 65 is adhesively mounted on the bottom plate of the case 4-1 via the low melting point bonding agent 68-B, or the case 4-1 is mounted by screwing.
It is configured to be fixedly mounted on the bottom plate of.

As illustrated in FIG. 9, each of the above-mentioned carriers has a bottom length substantially equal to the length of the analog signal processing circuit board or the digital signal processing circuit board on which the bottom surface is mounted, and the top surface length of the carrier has an analog signal processing. It is smaller than the length of the circuit board or the digital signal processing circuit board.

As illustrated in FIG. 10, a Cu layer 27a, a Ni layer 27b, and an Au layer 27c are formed in this order on the back surface of the analog signal processing circuit board 20, and an Au film 27-2 is formed on the upper surface of the carrier 25. The analog signal processing circuit board 20 and carrier 25 are
The structure is such that it is bonded via Ag non-flux solder.

As illustrated in FIG. 11, the Ag / Pd layer 17a, the Ni layer 17b, and the Au layer 17c are formed in this order on the back surface of the digital signal processing circuit board 10, and the Au film 17-2 is formed on the upper surface of the carrier 15. Formed, the digital signal processing circuit board 10 and the carrier 15 are
It is configured to be bonded via n, Ag non-flux solder.

As illustrated in FIG. 12, the signal transmission path connecting the digital signal processing circuit board 10 and the analog signal processing circuit board 20 is assumed to be a pair of two parallel signals for transmitting the same signal in parallel. .

Signal pads 72A-1, 72 for a pair of signal transmission paths
B-1 The signal pads are arranged close to the side edges of the digital signal processing circuit board 10 so that the distance b is smaller than the distance B between the signal pads of another pair of adjacent signal transmission paths. .

Signal pads 72A-2 and 72B-2 are arranged on the side edges of the analog signal processing circuit board 20 so as to face the signal pads of the digital signal processing circuit board 10. A power supply pad 71-1 is arranged at a side edge of the digital signal processing circuit board 10 at a predetermined distance from the signal pad, and the digital signal processing circuit board is provided.
A power supply pad 71-2 is arranged on the side edge of the analog signal processing circuit board 20 so as to face the power supply pad 71-1 on the side edge portion of the device 10.

Then, a bonding wire 73 for connecting between the power supply pads 71-1 and 71-2 arranged opposite to the digital signal processing circuit board 10 and the analog signal processing circuit board 20,
It is assumed that it is longer than the bonding wire 74 that connects between the signal pads arranged to face the digital signal processing circuit board 10 and the analog signal processing circuit board 20.

As illustrated in FIG. 13, the respective electrodes of the PD array 42 and the signal electrodes 91 of the amplification LSI 50Z mounted on the analog signal processing circuit board 50 are directly connected via bonding wires. It will be configured.

As shown in FIG. 14, the LD driving LSI 90Z is mounted on the analog signal processing circuit board 20 of the transmission link 1, and the signal pad is connected to the signal electrode 91 of the LD driving LSI 90Z via a bonding wire. 94A
The damping resistance film 95 formed on the surface of the analog signal processing circuit board 20 and formed on the inner layer of the analog signal processing circuit board 20 is connected to the signal pad 94A via the via.

As illustrated in FIG. 15, the pad 24 formed on the analog signal processing circuit board 20 or the digital signal processing circuit board is formed by plating the surface of the good conductive metal layer. The protective resin layer 29 provided so as to cover the surface of the removed analog signal processing circuit board 20 (digital signal processing circuit board) is the analog signal processing circuit board 20.
It shall not be formed on the upper part of the side edge of four laps.

As illustrated in FIG. 16, an amplification LSI mounted on the analog signal processing circuit board 50 of the reception link 4.
50Z has a preamplifier circuit 51-1 in one half,
The main amplifier circuit 51-2 is configured in the other half, and the power supply pattern formed in the inner layer of the analog signal processing circuit board 50 is a power supply pattern 59-1 for supplying power to the preamplifier circuit 51-1. A power supply pattern 59-2 for supplying power to the main amplifier circuit 51-2 is separated.

As shown in FIG. 17, the power supply pattern and the ground pattern provided corresponding to the bare chip 90 mounted on the analog signal processing circuit board or the analog signal processing circuit board 50 are provided on different inner layers. Yes, the inner layer power pattern 96A is connected to the power pad 93A formed on the surface layer via the via 97A having a predetermined impedance, and the inner layer ground pattern 96B is connected to the ground pad 93B formed on the surface layer with a predetermined pattern. It is assumed that they are connected via the via 97B having impedance.

As illustrated in FIG. 18, the analog signal processing circuit board or the surface layer of the analog signal processing circuit board 50 is provided in correspondence with the bare chip 90 mounted on the analog signal processing circuit board 50. , The signal electrode of the bare chip 90, the power electrode, and the signal electrode that is connected to the ground electrode via the bonding wire, the power pad, and the ground pad are formed in two rows, and each pad has a wide thickness. It shall consist of a membrane.

Further, as illustrated in FIG. 19, the projections 98 are arranged on the side edges of the power supply pads and the ground pads in the number equal to the number of bonding wires to be connected.
Furthermore, a via 97 connected to the inner layer is provided on each of the signal pad, the power supply pad, and the ground pad, and the pad for connecting a plurality of bonding wires is
The protrusion 99 is provided, and the beer 97 is also provided on the protrusion 99.

As illustrated in FIG. 20, the transmission link or the reception link has an L-shaped terminal that insulates and penetrates the side wall of the case.
85 arranged. The tip of the L-shaped terminal 85 protruding into the case is connected to the analog signal processing circuit board, and the through-hole 82 is inserted and soldered into the vertical portion of the L-shaped terminal 85 protruding outside the side wall to thereby print the printed circuit board. 81 is case 1-1, 4-11
The adjustment resistor 80 is mounted outside the device and the printed circuit board 81 is mounted with the adjusting resistor 80.

[0071]

In the transmission link, the digital signal processing circuit board on which the skew compensation / code conversion circuit is formed, the analog signal processing circuit board on which the LD drive circuit is formed, and the LD / fiber array module are housed in a case. The receiving link contains the PD / fiber array module, the analog signal processing circuit board on which the amplifier circuit and the limiter amplifier circuit are formed, and the digital signal processing circuit board on which the skew compensation / code conversion circuit is formed in the case. It is sealed and the transmission link and the reception link are connected through an optical ribbon fiber.

Therefore, optical parallel transmission with a small skew and a high speed is possible. Further, both the transmission link and the reception link are housed in the case, and thus each is small.

According to a second aspect of the present invention, the analog signal processing circuit board is formed by forming a copper polyimide board on a ceramic board. A narrow pattern can be formed at high density on this copper-polyimide substrate, and since the polyimide resin has a low dielectric constant, it is easy to increase the signal speed.

On the other hand, since the digital signal processing circuit board is made of glass ceramics, the cost is low. According to a third aspect of the present invention, the analog signal processing circuit board and the digital signal processing circuit board are bonded and mounted on the upper surfaces of different carriers through a high melting point bonding agent, and the carrier is bonded to the bottom plate of the case through a low melting point bonding agent. It is mounted or fixedly mounted on the bottom plate of the case by screw means.

Therefore, the analog signal processing circuit board and the digital signal processing circuit board can be attached to or detached from the case with the carrier mounted on the carrier, which facilitates maintenance and inspection / replacement work.

Further, since the analog signal processing circuit board and the digital signal processing circuit board are mounted on the carrier, respectively, the test can be carried out independently before mounting on the case.

In the invention of claim 4, the bottom length of each carrier is substantially equal to the length of the analog signal processing circuit board or the digital signal processing circuit board on which the bottom surface is mounted, and the top surface length of the carrier is the analog signal processing circuit board or It is smaller than the length of the digital signal processing circuit board.

Therefore, even if the circuit board and the carrier are bonded with solder and the solder may flow out to the side surface of the carrier, the solder does not protrude outside the side surface of the circuit board.

Accordingly, since there is no obstacle to the close proximity of the circuit boards to be mounted adjacently, the close proximity mounting of the circuit boards is possible, and the bonding wire length connecting both circuit boards can be reduced, which is effective for speeding up the signal. is there.

According to a fifth aspect of the present invention, a Cu layer, a Ni layer, and an Au layer are formed in this order on the back surface of the analog signal processing circuit board, and an Au film is formed on the upper surface of the carrier. And are bonded via non-flux solder.

Therefore, the wettability of the solder is improved and the adhesive strength is increased. In addition, since the non-flux solder is used, the cleaning work for removing the flux of the analog signal processing circuit board after soldering and bonding is unnecessary, so the components mounted on the analog signal processing circuit board due to the cleaning liquid will not be damaged. Be blocked.

According to a sixth aspect of the present invention, the Ag / Pd layer and the Ni layer are provided on the back surface of the digital signal processing circuit board (glass ceramics).
A layer and an Au layer are formed in this order, an Au film is formed on the upper surface of the carrier, and the digital signal processing circuit board and the carrier are bonded together via non-flux solder.

Therefore, the wettability of the solder is improved and the adhesive strength is increased. In addition, since non-flux solder is used, cleaning work for flux removal of the digital signal processing circuit board after solder bonding is unnecessary, so damage to the components mounted on the digital signal processing circuit board by the cleaning liquid is not necessary. Be blocked.

According to a seventh aspect of the present invention, the signal transmission path connecting the digital signal processing circuit board and the analog signal processing circuit board is configured such that two parallel lines are paired to transmit the same signal in parallel. The distance between the bonding wire for the signal and the other pair of bonding wires for the signals is increased.

Further, the bonding wires connecting the power supply pads are separated from the bonding wires connecting the signal pads and are longer than the bonding wires.

Therefore, there is no crosstalk between channels.
Further, the high frequency impedance of the power supply between the digital signal processing circuit board and the analog signal processing circuit board can be increased, and the noise due to the sneak from the power supply is reduced.

According to the eighth aspect of the present invention, each electrode of the PD array of the PD / fiber array module and the signal electrode of the amplification LSI mounted on the analog signal processing circuit board are directly connected via a bonding wire. are doing.

Therefore, the length of the coupling line is short and the speed of signal transmission is increased. The invention of claim 9 is an LD driving LSI.
A signal pad to be connected to the signal electrode of the above through a bonding wire is formed on the surface of the analog signal processing circuit board, and a damping resistance film formed on the inner layer of the analog signal processing circuit board is connected to the signal pad through the via. Connected to.

That is, since the damping resistor is not mounted on the surface of the analog signal processing circuit board, miniaturization of the analog signal processing circuit board is promoted accordingly. Claim 1
According to the invention of No. 0, the pad formed on the circuit board is formed by plating a good conductive metal layer on the surface, and the protective resin layer provided so as to cover the surface of the circuit board is formed around the circuit board. Is not formed on the upper side edge. That is, there is no corner at the peripheral edge of the circuit board.

Therefore, when the plating layer is provided on the pad surface, the back surface side of the plating resist formed on the surface of the circuit board becomes gentle and cracks do not occur in the plating resist. That is, metal pieces of plating are not deposited on the circuit board, and short-circuit failure does not occur between the leads of the components mounted on the circuit board.

In the eleventh aspect of the present invention, the power supply pattern for supplying power to the preamplifier circuit and the power supply pattern for supplying power to the main amplifier circuit are formed separately in the inner layer of the analog signal processing circuit board of the reception link.

Therefore, the interference between the preamplifier circuit and the main amplifier circuit due to the voltage fluctuation is eliminated. Further, by reducing the opposite side edges of both power supply patterns, noise reflection is reduced.

According to the twelfth aspect of the present invention, the power source pattern and the ground pattern provided corresponding to the bare chip mounted on the circuit board are provided in different inner layers, and the inner layer power source pattern is provided on the power source pad formed on the surface layer in a predetermined manner. The inner layer ground pattern is connected to the ground pad formed on the surface layer via a via having a predetermined impedance.

Therefore, the power source and the ground are completely separated, and the interference between the channels via the power source and the ground is reduced, and there is no possibility that crosstalk occurs. According to a thirteenth aspect of the present invention, a wide thickness corresponding to a bare chip mounted on a circuit board is connected to a surface layer of the circuit board to a signal electrode, a power supply electrode, and a ground electrode of the bare chip via a bonding wire. Signal pad, power pad,
The ground pads are formed in a plurality of rows.

By arranging the pads in a plurality of rows, it is possible to widen each pad. That is, since each pad formed by screen printing is wide, even if both side edges of the surface of the thick film pad are projected, there is a sufficiently large flat portion in the central portion. Therefore, even if the wire bonding is performed by thermocompression bonding, the connection has high reliability and high strength.

According to the fourteenth aspect of the present invention, the power supply pad and the grounding pad made of a wide thick film are formed with the same number of protrusions as the number of bonding wires to be connected on the side edge. Therefore, since the positions where the respective bonding wires are to be thermocompression-bonded can be designated at positions sufficiently inside from the left and right ends of the pads, the reliability of connection of the bonding wires is high and the strength is strong.

According to a fifteenth aspect of the present invention, the signal pad, the power supply pad, and the ground pad made of a wide thick film each have a via connected to an inner layer, and the pad connecting a plurality of bonding wires has a side edge. The protrusion has a protrusion, and the protrusion also has a via.

Therefore, the reliability of the connection between the inner layer pattern and the pad is improved. In the sixteenth aspect of the present invention, the L-shaped terminals connected to the internal circuit are arranged on the side walls of the respective cases of the transmission link and the reception link, and the through holes are inserted in the vertical portions of the L-shaped terminals protruding to the outside of the side walls. The printed circuit board is mounted outside the case by soldering, and the adjustment resistor is mounted on the printed circuit board.

Therefore, not only the adjustment work of the adjustment resistor can be performed outside the case, but also the work of mounting and replacing the printed circuit board becomes easy.

[0100]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to FIGS. The same reference numerals indicate the same objects throughout the drawings.

As shown in FIGS. 1 to 7, the input line 1-
A transmission link 1 for receiving a digital electric signal from 10, converting it into an analog signal, converting it into an electric signal, and transmitting an optical signal,
It is an optical parallel link in which an optical ribbon fiber 7 is connected to a receiving link 4 for receiving an analog optical signal, converting it into an optical signal, and transmitting a digital electric signal from an output line 4-10.

The transmission link 1 includes a digital signal processing circuit board 10 on which a skew compensation / code conversion circuit 11 is formed,
An analog signal processing circuit board having a D drive circuit 21, a capacitor for stabilizing a drive waveform, a damping resistor, etc.
20 and the LD / fiber array module 30 connected to the optical ribbon fiber 7 are arranged and connected in this order to form a case.
It is housed in 1-1 and case 1-1 is sealed with lid 1-2.

The reception link 4 includes a PD / fiber array module 40 connected to the optical ribbon fiber 7, an analog signal processing circuit board 50 on which an amplifier circuit 51, a limiter amplifier circuit 52, a bypass capacitor and the like are formed, and skew compensation. The digital signal processing circuit board 60 on which the code conversion circuit 61 is formed is arranged and connected in this order and housed in the case 4-1, and the case 4-1 is sealed with the lid 4-2.

The above skew compensation / code conversion circuit is, for example, a P19BIC multiplexing / code conversion circuit, and has a small skew. For details of this P19BIC multiplex / code conversion circuit, see H. Rokgawa et al., "A Skew-free Circuit for Gig.
abit Optical Parallel Interconnection ", Technical R
Reported in eport of IEICE OCS94-14.

As shown in detail in FIGS. 2 and 4, the transmission link 1 includes a digital signal processing circuit board 10, an analog signal processing circuit board 20 and L in a shallow box-shaped case 1-1.
The D / fiber array module 30 is mounted.

Then, an elongated printed circuit board is attached to the inside of the pair of selected side walls of the case 1-1, and the input terminal 11-1, the power supply terminal 1-11 are arranged so as to vertically penetrate the printed circuit board.
D, ground terminals 1-11G are arranged, and the tip portion thereof is connected to the pattern of the digital signal processing circuit board 10 or the analog signal processing circuit board 20 via a bonding wire.

These input terminal 11-1, power supply terminal 1-11D, and ground terminal 1-11G penetrate the bottom plate of the case (insulation-sealed, for example, glass-sealed). Then, the transmission link 1 is mounted on the motherboard by inserting and soldering the lower ends of the respective terminals into through holes of a mother boat (not shown).

This printed board is connected to a predetermined pattern of the analog signal processing circuit board 20 via a bonding wire. Also, another printed circuit board 81 that is electrically connected to the printed circuit board attached inside the case 1-1 is used.
Attached to the outside of the pair of selected side walls of Case 1-1,
Mount the adjusting resistor 80 on this printed circuit board and
The characteristics of the transmission link 1 can be adjusted outside.

As shown in detail in FIG. 6, the LD / fiber array module 30 includes an LD array 31 in which a substrate 33 is mounted on a metal stem 37 and LDs (light emitting elements such as semiconductor lasers) are arranged in a horizontal row. , Is mounted on one side edge of the substrate 33.

Then, on the surface of the other side edge of the substrate, a pad 34 connected to the electrode of each LD through a pattern is formed.
Are formed in parallel. On the other hand, in the optical fiber array 32, the ferrule 35 is attached to the end of the optical ribbon fiber 32A.

The ferrule 35 is composed of a lower half substrate made of silicon or the like having V grooves arranged on the upper surface at equal pitches, and an upper half substrate pressed and fixed to the lower half substrate. The optical fiber array 32 is constructed by separating the ends of the optical ribbon fibers 32A into respective optical fiber cores and inserting and fixing the optical fiber cores in the corresponding V grooves of the ferrule 35.

The ferrule 35 portion of the optical fiber array 32 is protected by a rectangular parallelepiped metal holder 38 having a thin outer shape. Then, the metal holder 38 is penetrated through the window of the metal frame 39, and the metal frame 39 and the metal holder 38 are fixed by welding or the like.

The incident end face of the optical fiber core wire of the optical fiber array 32 is disposed in proximity so as to be optically coupled to the corresponding LD emission face of the LD array 31, and the end face of the metal stem 37 and the end face of the metal holder 38 are brought into contact with each other. The LD array 31 is brought into contact with the LD array 31 by spot welding the metal stem 37 and the metal holder 38 in that state.
And the optical fiber array 32 are integrated.

The metal holder 38 portion of the LD / fiber array module 30 is provided on the side wall of the case 1-1 and fitted into the hollowed hole, and the end face of the metal frame 39 is brought into contact with the outer side face of the side wall to allow the metal frame 39 and the case 1 to come into contact with each other. -1 and -1 are fixed by laser welding.

The optical ribbon fiber 32A of the optical fiber array 32 is connected to the optical ribbon fiber 7 via the optical connector 7-1, and the other end of the optical ribbon fiber 7 is connected to the other optical connector 7-2. Is connected to the optical ribbon fiber 41A of the optical fiber array 41 of the reception link 4 via.

The digital signal processing circuit board 10 and the analog signal processing circuit board 20 are different in carrier (F-Ni
-Co alloy or copper-tungsten alloy) 15,25, and the bottom surfaces of the carriers 15,25 are closely adhered to the bottom plate of the case 1-1.

Between the digital signal processing circuit board 10 and the analog signal processing circuit board 20, and between the analog signal processing circuit board 20 and L
The D and fiber array modules 30 are mounted via bonding wires.

As shown in FIGS. 3 and 6, the reception link 4 includes the PD / fiber array module 40, the analog signal processing circuit board 50, and the digital signal processing circuit board 60 in a shallow box-shaped case 4-1. It is implemented.

Then, an elongated printed circuit board is attached to the inside of the pair of selected side walls of the case 4-1, and the input terminal 4-11 and the power supply terminal 4-11 are arranged so as to vertically penetrate the printed circuit board.
D, ground terminals 4-11G are arranged, and the tip portion thereof is connected to the pattern of the digital signal processing circuit board 60 or the analog signal processing circuit board 50 via a bonding wire.

These input terminal 4-11, power supply terminal 4-11D, and ground terminal 4-11G penetrate the bottom plate of the case (insulation sealing, for example, glass sealing and penetrating). Then, the transmission links 4 are mounted on the mother board by inserting and soldering the lower ends of the respective terminals into the through holes of the mother boat (not shown).

The printed circuit board is also connected to a predetermined pattern of the analog signal processing circuit board 50 via bonding wires. Also, attach another printed circuit board 81, which is electrically connected to the printed circuit board mounted inside case 4-1 to the outside of the pair of selected side walls of case 4-1 and adjust the resistance to this printed circuit board. 80 is implemented so that the characteristics of the transmission link 4 can be adjusted outside Case 4-1.

As shown in detail in FIG. 7, the PD / fiber array module 40 mounted on the reception link 4 has a substrate 43 mounted on a metal stem 47, and PDs (light-receiving elements such as high-speed photodiodes) arranged in a row. PD array 42 arranged in
Are mounted on one side edge of the substrate 43.

Then, on the surface of the other side edge of the substrate, a pad 44 connected to the electrode of each PD through a pattern is formed.
Are formed in parallel. On the other hand, in the optical fiber array 41, the ferrule 45 is attached to the end of the optical ribbon fiber 41A.

The ferrule 45 is composed of a lower half substrate made of silicon or the like having V grooves arranged on the upper surface at an equal pitch, and an upper half substrate pressed and fixed to the lower half substrate. The optical fiber array 41 is constructed by separating the ends of the optical ribbon fiber 41A into respective optical fiber core wires and inserting and fixing the optical fiber core wires into the corresponding V grooves of the ferrule 35.

The ferrule 45 portion of the optical fiber array 41 is protected by a rectangular parallelepiped metal holder 48 having a thin outer shape. Then, the metal holder 48 is passed through the window of the metal frame 49, and the metal frame 49 and the metal holder 48 are fixed by welding or the like.

The incident end face of the optical fiber core wire of the optical fiber array 41 is closely arranged so as to be optically coupled to the corresponding incident face of the PD of the PD array 42, and the end face of the metal stem 47 and the end face of the metal holder 48 are brought into contact with each other. Then, the PD stem 42 and the metal holder 47 are spot welded to each other in this state.
And the optical fiber array 41 are integrated.

The metal holder 48 portion of the PD / fiber array module 40 is provided on the side wall of the case 4-1 and fitted into the hollowed hole, and the end surface of the metal frame 49 is brought into contact with the outer surface of the side wall to form the metal frame 49 and the case 4. -1 and -1 are fixed by laser welding.

The analog signal processing circuit board 50 and the digital signal processing circuit board 60 are different from each other in the carriers 55 and 65.
The bottom surface of each carrier 55, 65 is adhered and fixed to the bottom plate of the case 4-1.

Between the PD / fiber array module 40 and the analog signal processing circuit board 50, the analog signal processing circuit board
The 50 and the digital signal processing circuit board 60 are mounted via bonding wires.

Since the optical parallel link is configured as described above, a digital electric signal is input to each channel from the input terminal 1-11, and the digital electric signal is multiplexed and converted by the digital signal processing circuit board 10. Digital processing is performed, and the result is output to the analog signal processing circuit board 20.

In the LD drive circuit 21 of the analog signal processing circuit board 20, from the signal level of the standard digital circuit output from the digital signal processing circuit board 10, the L of the LD array 31 is changed.
The LD of the LD / fiber array module 30 is driven by converting it into an analog electric signal for driving D.

The optical signal electro-optically converted by the LD array 31 is transmitted to the reception link 4 via the optical fiber array 32 and the optical ribbon fiber 7. The optical signal transmitted to the reception link 4 is optically / electrically converted by the PD of the PD array 42 and then transmitted to the analog signal processing circuit board 50. Since this electric signal is weak, it is raised to the signal level of the standard digital circuit by the amplifier circuit 51 and the limiter amplifier circuit 52 of the analog signal processing circuit board 50,
It is output to the digital signal processing circuit board 60.

The skew compensation / code conversion circuit 61 of the digital signal processing circuit board 60 separates each channel by the procedure reverse to the multiplexing of the transmission link, and becomes the original electric signal input to the transmission link, and the output terminal It is output from 4-11.

Since the optical parallel link of the present invention is constructed as described above, the optical ribbon fiber 7, the transmission link 1,
Optical parallel transmission is possible in which the skew of each of the reception links 4 is small and the speed is increased.

Both the transmission link 1 and the reception link 4 are small in size because they are housed in the case. The details of the optical parallel link of the present invention will be described below with reference to FIGS.

The circuit boards of the transmission link and the reception link are
It is as illustrated in FIG. 8 (FIG. 8 shows the receiving link 4). As illustrated in FIG. 8, the analog signal processing circuit board 50 is formed by forming a copper polyimide board 50-2 on the surface of a ceramic board 50-1, and the digital signal processing circuit board 60 is made of glass ceramics. It will be.

The analog signal processing circuit board 50 is a carrier.
A high melting point bonding agent 58-A (for example, Sn with a melting point of 212 ° C,
It is mounted by adhesion via (Ag solder). Carrier 55
Close the back of the case to the bottom of Case 4-1 and
58-B (for example, Sn, Pb solder with a melting point of 183 ° C) is bonded and mounted. Alternatively, the carrier 55 is fixedly mounted on the bottom plate of the case 4-1 by screw means.

On the other hand, the digital signal processing circuit board 60 has a high melting point bonding agent 68-A (for example, a melting point of 212 ° C.) on the upper surface of the carrier 65.
(Sn, Ag solder). The carrier 65 has its back surface brought into close contact with the bottom surface of the case 4-1, and is adhesively mounted via a low melting point bonding agent 68-B (eg, Sn, Pb solder having a melting point of 183 ° C.). Alternatively, the carrier 65 is fixedly mounted on the bottom plate of the case 4-1 by screw means.

Although not shown, the analog signal processing circuit board 20 of the transmission link 1 is formed by forming a copper polyimide board on the surface of a ceramic board in the same manner as described above, and the digital signal processing circuit board is made of glass ceramics. It will be.

The analog signal processing circuit board 20 is bonded and mounted on the upper surface of the carrier 25 via a high melting point bonding agent.
The carrier 25 has its back surface brought into close contact with the bottom surface of the case 1-1 and is adhesively mounted via a low melting point bonding agent, or is fixedly mounted on the bottom plate of the case by screw means.

The digital signal processing circuit board 10 is a carrier.
The carrier 15 is adhesively mounted on the top surface of the case 15 with a high melting point bonding agent, and the back surface of the carrier 15 is closely adhered to the bottom surface of the case 1-1, and the carrier 15 is adhesively mounted on the bottom surface of the case 1-1 by a low melting point bonding agent, or by a screw means. It is fixedly mounted on the bottom plate.

Since the analog signal processing circuit board is a ceramic polyimide board on which a copper polyimide board is formed, a narrow pattern can be formed at a high density on this copper polyimide board, and since the polyimide resin has a small dielectric constant It is easy to speed up.

On the other hand, since the digital signal processing circuit board is made of glass ceramics, the cost is low. In addition, high-melting-point bonding agent is used for digital signal processing circuit boards,
The analog signal processing circuit board is adhered to the corresponding carrier, and the carrier is adhered to the bottom plate of the case with a low melting point adhesive, or it is attached with screw means, so each circuit board mounted on the carrier It can be installed or removed, and maintenance, inspection and replacement work is easy.

Further, since each circuit board is mounted on the carrier, the test can be carried out independently before mounting on the case. As illustrated in FIG. 9, for example, the bottom length of the carrier 15 is substantially equal to the length of the digital signal processing circuit board 10 on which the carrier 15 is mounted, and the top length of the carrier 15 is smaller than the length of the digital signal processing circuit board 10. To
A step 15A is provided on each of the front and rear side surfaces of the carrier 15.

Au film on the back surface of the digital signal processing circuit board 10.
17-1 is formed, an Au film 17-2 is formed on the upper surface of the carrier 15, and an Au film 17-3 is formed on the back surface of the carrier 15 to connect the digital signal processing circuit board 10 and the carrier 15 with a high melting point bonding agent 18 -A is glued.

Although not shown, the carriers 25, 55 and 65 on which the other analog signal processing circuit board 20, the analog signal processing circuit board 50 and the digital signal processing circuit board 60 are mounted also have the same shape.

Therefore, the digital signal processing circuit board 10
The carrier 15 and the carrier 15 are bonded with a high melting point bonding agent such as a high melting point solder, and even if the high melting point solder may flow out to the side surface of the carrier 15, the high melting point solder may protrude to the outside of the side surface of the digital signal processing circuit board 10. Absent.

Therefore, for example, since the analog signal processing circuit boards 20 to be mounted adjacently do not interfere with the proximity of the circuit boards, the circuit boards can be mounted close to each other, the bonding wire length connecting both circuit boards can be reduced, and the signal Effective for speeding up.

As illustrated in FIG. 10, the analog signal processing circuit board 20 of the transmission link 1 (the circuit board having the ceramic board 20-1 and the copper polyimide board 20-2 formed on the surface thereof)
A Cu layer 27a, a Ni layer 27b, and an Au layer 27c are formed in this order on the back surface of, and Sn and Ag non-flux solder sheets 28-A1 (high melting point solder) are pre-soldered and laminated on the Au layer 27c.

On the other hand, an Au film 27-2 is formed on the upper surface of the carrier 25, and a Sn, Ag non-flux solder sheet is formed on the Au film 27-2.
Pre-solder 28-A2 (high melting point solder) and stack. Then, the analog signal processing circuit board 20 is aligned and placed on the carrier 25, heated to about 320 ° C., and main soldering is performed to join the carrier 25 and the analog signal processing circuit board 20.

Analog signal processing circuit board of reception link 4
The 50 is likewise joined to the corresponding carrier 55. Since the non-flux solder is used as described above, the cleaning work for removing the flux from the analog signal processing circuit board after solder bonding is unnecessary, and the components mounted on the analog signal processing circuit board are not damaged by the cleaning liquid. It has the effect of being blocked.

Further, Sn, Ag and Au are alloyed to improve the wettability of the solder, which has the effect of increasing the reliability of the joining. The Ni of the Ni layer prevents Ag of Sn, Ag non-flux solder from diffusing into the Cu layer.

As illustrated in FIG. 11, Ag, Pd layer 17a, Ni layer 17b, Au layer 17c are formed in this order on the back surface of the digital signal processing circuit board 10 (glass ceramics) of the transmission link 1, and this Au layer is formed. A Sn, Ag non-flux solder sheet 18-A1 (high melting point solder) is pre-soldered and laminated on the layer 17c.

On the other hand, an Au film 17-2 is formed on the upper surface of the carrier 15, and Sn and Ag non-flux solder sheets are formed on the Au film 17-2.
Pre-solder 18-A2 (high melting point solder) and stack. Then, the digital signal processing circuit board 10 is aligned and placed on the carrier 15, heated to about 320 ° C., and main soldering is performed to join the carrier 15 and the digital signal processing circuit board 10.

Digital signal processing circuit board of receiving link 4
The 60 is likewise joined to the corresponding carrier 65. Since the non-flux solder is used as described above, the cleaning work for removing the flux from the digital signal processing circuit board after solder bonding is unnecessary, and the components mounted on the digital signal processing circuit board due to the cleaning liquid are not damaged. It has the effect of being blocked.

Further, Sn, Ag and Au are alloyed with each other to improve the wettability of the solder, so that there is an effect that the reliability of the joining is increased. The Ni in the Ni layer prevents Ag of the Sn, Ag non-flux solder from diffusing into the Ag, Pd layer.

As shown in FIG. 12, for example, two parallel signal transmission lines (bonding wires 74) connecting the digital signal processing circuit board 10 and the analog signal processing circuit board 20 of the transmission link 1 are paired. The same signal is transmitted in parallel as.

As illustrated in FIG. 12, the signal transmission paths of the respective channels connecting the digital signal processing circuit board 10 and the analog signal processing circuit board 20 have two parallel lines as a pair and transmit the same signal in parallel. I shall.

A pair of signal transmission line signal pads 72A-1, 72
B-1 The signal pad is provided on the side edge of the digital signal processing circuit board 10 so that the distance b is smaller than the distance B between the signal pads 72A-1 and 72B-1 of the other pair of adjacent signal transmission paths. Are arranged close to each other.

Signal pads 72A-2 and 72B-2 are provided on the side edges of the analog signal processing circuit board 20 so as to face the signal pads of the digital signal processing circuit board 10. A power supply pad 71-1 is provided at a side edge of the digital signal processing circuit board 10 at a position separated from the signal pad by at least the distance B described above.

A power supply pad 71-2 is provided on the side edge of the analog signal processing circuit board 20 so as to face the power supply pad 71-1 on the side edge of the digital signal processing circuit board 10.
The distance between the opposing power supply pads 71-1 and 71-2 is sufficiently larger than the distance between the opposing signal pads 72A-1 and 72A-2.

Therefore, the digital signal processing circuit board 10
The length of the bonding wire 73 that connects between the power supply pad 71-1 of the digital signal processing circuit board 20 and the power supply pad 71-2 of the analog signal processing circuit board 20 is equal to that of the signal pad 72A- of the digital signal processing circuit board 10.
1 and signal pad 72A-2 for analog signal processing circuit board 20
It is sufficiently longer than the bonding wire 74 that connects the two.

Therefore, there is no crosstalk between channels.
Further, the high frequency impedance of the power supply between the digital signal processing circuit board and the analog signal processing circuit board can be increased, and the noise due to the sneak from the power supply is reduced.

The signal transmission path of each channel connecting between the analog signal processing circuit board 50 and the digital signal processing circuit board 60 of the receiving link 4 is a pair of two parallel signals for transmitting the same signal in parallel. is there.

As illustrated in FIG. 13, the amplification LSI 50Z is mounted on the analog signal processing circuit board 50 of the reception link 4 close to the PD / fiber array module 40. The signal electrode 91 of the amplification LSI 50Z and the corresponding PD electrode of the PD array 42 are directly connected via a bonding wire.

On the other hand, the power / ground electrode 92 of the amplification LSI 50Z is connected to the power / ground pad 93 provided on the surface of the analog signal processing circuit board 50 via a bonding wire.

Therefore, the analog signal processing circuit board 50
The length of the coupling line connecting the PD and the fiber array module 40 is shortened, and the speed of signal transmission is increased. As shown in FIG. 14, the LD driving LSI 90Z is mounted on the analog signal processing circuit board 20 of the transmission link 1.
A signal pad 94A connected to the signal electrode 91 of the drive LSI 90Z via a bonding wire is formed on the surface of the analog signal processing circuit board 20.

A damping resistance film 95 is formed in the inner layer immediately below the signal pad 94A.
94A and the damping resistance film 95 are connected via a via. The inner layer pattern connected to the end of the damping resistance film 95 is connected to the signal pad 94 formed on the surface of the analog signal processing circuit board 20 via another via.

The signal pad 94 is connected to the electrode of the corresponding LD of the LD / fiber array module 30 via a bonding wire. As described above, by providing the damping resistance film 95 on the inner layer of the analog signal processing circuit board 20, the size of the mounting surface of the analog signal processing circuit board 20 is reduced, and the analog signal processing circuit board is downsized accordingly. Be promoted.

As shown in FIG. 15, in the analog signal processing circuit board 20, the copper polyimide board 20-2 is formed on the surface of the ceramic board 20-1, and the pads 24 are arranged on the surface of the copper polyimide board 20-2. Is formed.

The surface of the pad 24 is plated with a good conductive metal layer (eg Au). Pad 24
A protective resin layer, for example, a protective polyimide layer 29 is formed so as to cover the surface of the analog signal processing circuit board 20 except for the above.

At this time, in the present invention, the protective polyimide layer 29 is used.
Is not formed on the upper portion of the side edge of the analog signal processing circuit board 20 for four rounds. That is, since there is no protective polyimide layer 29 immediately above the peripheral portion of the analog signal processing circuit board 20, the back surface side of the plating resist 24Z formed on the surface of the circuit board is comparatively gentle when the plating layer is provided on the pad surface. become.

Therefore, the plating resist 24Z is not cracked, the plating metal pieces are not deposited, and the short circuit failure does not occur between the leads of the components mounted on the circuit board.

The above-mentioned configuration has the same effect when applied to the analog signal processing circuit board of the reception link 4 and the digital signal processing circuit board of the transmission link. As illustrated in FIG. 16, in the amplification LSI 50Z mounted on the analog signal processing circuit board 50 of the reception link 4, the preamplifier circuit 51-1 is formed in one half and the main amplifier circuit 51 is formed in the other half. -2 is configured.

Corresponding to the power supply electrode of the preamplifier circuit 51-1, one side edge of the amplification LSI 50Z (preamplifier circuit 51
The power supply pad 54-1 for the preamplifier circuit is arranged in the vicinity of the side edge on the side where -1 is formed).

Then, in the inner layer immediately below the region including the back surface of one half of the amplification LSI 50Z and the power supply pad 54-1,
One power supply pattern 59-1 for the preamplifier circuit, which is substantially trapezoidal in plan view, is provided, and is connected to the aforementioned power supply pad 54-1 for the preamplifier circuit via a via.

On the other hand, the main amplifier circuit is provided in the vicinity of the other side edge (the side edge on which the main amplifier circuit 51-2 is formed) of the amplification LSI 50Z, corresponding to the power supply electrode of the main amplifier circuit 51-2. A power supply pad 54-2 for power supply is provided.

Then, in the inner layer immediately below the region including the back surface of the other half of the amplification LSI 50Z and the power supply pad 54-2,
The other power supply pattern 59-2 for the main amplifier circuit, which is substantially trapezoidal in plan view, is provided, and is connected to the above-mentioned power supply pad 54-2 for the main amplifier circuit via a via.

Since it is constructed as described above, there is an effect that interference between the preamplifier circuit and the main amplifier circuit due to voltage fluctuation is eliminated. Also, since both trapezoidal power supply patterns 59-1, 59-2 are provided so that the short sides face each other, the opposing edge lengths of the power supply patterns are short and there are no corners, reducing noise reflection. To do.

As shown in FIG. 17, the bare chip 90 mounted on the analog signal processing circuit board 50 has a first channel area, a second channel area, a third channel area,
..... Separated into 90-1, 90-2, 90-3, .. Each channel region has a power electrode and a ground electrode.

On the surface of the analog signal processing circuit board 50 along the side edge of the bare chip 90, a power supply pad 93A connected to the power supply electrode of each channel via a bonding wire.
Are arranged in a line.

An elongated strip-shaped inner layer power supply pattern 96A is provided in the inner layer below the power supply pad row, and the inner layer power supply pattern 96A and each power supply pad 93A are connected through a via 97A having a predetermined impedance. There is.

On the other hand, the ground pads 93B connected to the ground electrodes of the respective channels via the bonding wires are arranged in a line on the surface of the analog signal processing circuit board 50 so as to be parallel to the above-mentioned power pad row. I have set up.

Below the ground pad row, an elongated strip-shaped inner layer ground pattern 96B is provided in an inner layer different from the inner layer in which the inner layer power supply pattern 96A is formed. The inner layer ground pattern 96B and each ground pad 93B are connected to each other. Are connected via a via 97B having a predetermined impedance.

With the above-mentioned structure, the power source and the ground are completely separated, and the interference between channels via the power source and the ground is reduced, so that crosstalk does not occur. The above-described configuration is not limited to the analog signal processing circuit board of the reception link 4, but may be applied to the digital signal processing circuit board of the reception link 4, the digital signal processing circuit board of the transmission link 1, and the analog signal processing circuit board. Also has the same effect.

The structure shown in FIG. 18 is applied to an analog signal processing circuit board and a digital signal processing circuit board provided with thick film pads. On the surface of the bare chip 90 mounted on the analog signal processing circuit board 50, a plurality of signal electrodes 91, power supply electrodes 92D and ground electrodes 92 are provided.
Have G.

The first row of power supply pads 93-1D made of a thick film having a wide width (width of 200 μm or more) parallel to and close to one side edge of the bare chip 90 on the analog signal processing circuit board 50. , The first row of ground pads 93-1G are arranged.

[0188] Each of the power supply pads 93-1D for the first column
, The ground pad 93-1G in the first row is connected to the power supply pattern or the ground pattern in the inner layer via the via 97. In addition, in parallel with the pads of the first row, on the surface of the analog signal processing circuit board 50, the wide second row of power supply pads 93-2D, especially the wide second row (for example, 400 μm or more) in the second row. The ground pad 93-2G for the eye and the signal pad 94-2 for the wide second row are arranged. Second row power supply pad
One projection 99 is provided on one side edge of each of the 93-2D and the signal pad 94-2 on the second row, and a via 97 is provided on the projection 99 to supply an inner layer power supply pattern or an inner layer signal pattern. Connected to.

In addition, the ground pad of the second row is particularly wide.
A plurality of protrusions 99 are provided on one longitudinal side edge of the 93-2G, and a via 97 is provided on each of the protrusions 99 to connect to the ground pattern of the inner layer.

First row ground pad 93-1G, first row power supply pad 93-1D, second row power supply pad 93-2D, second
The signal pads 94-2 in the column are connected to the corresponding electrodes via one bonding wire.

Also, the ground pad 93 of the second row, which is particularly wide, is used.
-2G is connected to the two power supply electrodes 92D of the bare chip 90 via different bonding wires.
It is connected to the power supply pattern or the inner layer signal pattern.

By arranging the pads in a plurality of rows, it is possible to widen each pad. Therefore,
Since each pad formed by screen printing is wide, even if both side edges of the surface of the thick film pad are projected, there is a sufficiently large flat portion in the central portion. Therefore, even if the wire bonding is performed by thermocompression bonding, the connection has a high reliability and a high strength.

Further, as illustrated in FIG. 19, the number of protrusions 98 (two in the figure) equal to the number of bonding wires to be connected to the ground pad 93-2G of the second row, which is particularly wide,
It is disposed at a sufficient distance from the longitudinal side edge opposite to the protruding portion 99.

The second row of ground pads 93-2G has a protruding portion 99.
Beer 97 is not only provided in the main area,
Is provided and is connected to the ground pattern of the inner layer. Therefore, since the positions where the respective bonding wires are to be thermocompression-bonded can be designated at positions sufficiently inside from the left and right ends of the pads, the reliability of connection of the bonding wires is high and the strength is strong.

Further, since a large number of vias 97 are formed, not only the reliability of the connection between the inner layer pattern and the pad is improved, but also the impedance thereof is reduced. As illustrated in FIG. 20, the receiving link 4 includes a PD / fiber array module in a shallow box-shaped case 4-1 made of a metal material.
40, the analog signal processing circuit board 50 and the digital signal processing circuit board 60 are mounted, the elongated printed board is attached to the inside of the pair of selected side walls of the case 4-1, and the printed board is vertically penetrated. Arrangement of input terminal, power supply terminal, and ground terminal, and its tip and digital signal processing circuit board
60 or the pattern of the analog signal processing circuit board 50 is connected via a bonding wire. Further, this printed board is connected to a predetermined pattern of the analog signal processing circuit board 50 via a bonding wire.

On the other hand, an L-shaped terminal is provided on the side wall of the case 4-1 so as to insulate and penetrate each of the opposite side walls of the case 4-1.
85 are arranged. The L-shaped terminal 85 has its horizontal end connected by soldering to a predetermined pattern of the above-mentioned printed circuit board in the case, and the vertical part protruding upward from the case 4-1.

Then, the through hole 82 is inserted into the vertical portion of the L-shaped terminal 85 and soldered to the printed circuit board.
The 81 is mounted horizontally outside Case 4-11. And
The adjustment resistor 80 is mounted on the printed circuit board 81.

Since it is constructed as described above, not only the adjustment work of the adjustment resistor can be performed outside the case, but also
Easy installation and replacement of printed circuit boards. In addition,
Such a configuration has the same effect when applied to the transmission link.

[0199]

The present invention has the following effects because it is configured as described above. In the transmission link, a digital signal processing circuit board on which a skew compensation / code conversion circuit is formed, an analog signal processing circuit board on which an LD drive circuit is formed, and an LD / fiber array module are housed and sealed in a case, The reception link encloses a PD / fiber array module, an analog signal processing circuit board on which an amplifier circuit and a limiter amplifier circuit are formed, and a digital signal processing circuit board on which a skew compensation / code conversion circuit is formed in a case. Moreover, since the transmission link and the reception link are connected via the optical ribbon fiber, optical parallel transmission with a small skew and high speed can be performed.

Further, both the transmission link and the reception link are housed in the case, and therefore they are small in size.
According to the invention of claim 2, a narrow pattern can be formed at high density on the analog signal processing circuit board, and the speed of the signal is increased. Further, the cost of the digital signal processing circuit board becomes low.

According to the third aspect of the present invention, the analog signal processing circuit board and the digital signal processing circuit board can be attached to or detached from the case with the carrier mounted on the carrier, which facilitates maintenance and inspection / replacement work. Further, since the circuit boards are mounted on the carriers, respectively, the test can be performed independently before mounting on the case.

According to the fourth aspect of the present invention, the circuit board and the carrier are bonded by solder, and even if the solder may flow out to the side surface of the carrier, the solder does not protrude to the outside of the side surface of the circuit board. The circuit boards can be mounted close to each other, the length of the bonding wire connecting both circuit boards can be reduced, the speed of signals can be increased, and each case can be miniaturized.

According to the fifth aspect of the present invention, since the analog signal processing circuit board and the carrier are adhered via the non-flux solder, the wettability of the solder to be joined is improved, and the carrier and the analog signal processing circuit board are improved. The adhesive strength with

Further, the cleaning work for removing the solder flux is unnecessary, and damage to the components mounted on the analog signal processing circuit board by the cleaning liquid is prevented. According to the invention of claim 6, since the digital signal processing circuit board and the carrier are bonded to each other via the non-flux solder, the wettability of the solder to be bonded is improved, and the carrier and the digital signal processing circuit board are bonded together. Adhesive strength becomes stronger.

Further, the cleaning work for removing the solder flux is unnecessary, and damage to the components mounted on the digital signal processing circuit board by the cleaning liquid is prevented. According to the invention of claim 7, there is no crosstalk between channels of the optical parallel link.

Further, the high frequency impedance of the power supply between the digital signal processing circuit board and the analog signal processing circuit board can be increased, and the noise due to the sneak from the power supply is reduced.

According to the eighth aspect of the invention, the length of the coupling line connecting the PD / fiber array module and the analog signal processing circuit board is short, and the signal transmission speed is increased. According to the invention of claim 9, since the damping resistor is not mounted on the surface of the analog signal processing circuit board, miniaturization of the analog signal processing circuit board is promoted accordingly.

According to the tenth aspect of the invention, when the plating layer is provided on the pad surface, the back surface side of the plating resist formed on the surface of the circuit board becomes gentle and cracks do not occur in the plating resist. No metal pieces are deposited, and short-circuit failure does not occur between the leads of components mounted on the circuit board.

According to the invention of claim 11, interference between the preamplifier circuit and the main amplifier circuit due to voltage fluctuation is eliminated. Also, the reflection of noise is reduced. According to the twelfth aspect of the present invention, the power supply connected to the bare chip mounted on the circuit board and the ground are completely separated, and the interference between the channels via the power supply and the ground is reduced, and there is no risk of crosstalk.

According to the thirteenth aspect of the invention, when applied to a circuit board having a thick film pad, the reliability between the bare chip mounted on the circuit board and the pad of the circuit board is high and the strength is high.

According to the fourteenth aspect of the present invention, the invention can be applied to a circuit board having a thick film pad, and the position on the pad of the bonding wire connecting the bare chip mounted on the circuit board and the pad can be specified. The connection is highly reliable and strong.

According to the fifteenth aspect of the invention, the reliability of the connection between the inner layer pattern of the circuit board and the pad is improved by applying the invention to the circuit board having the thick film pad. According to the sixteenth aspect of the present invention, the characteristic adjustment work of the transmission link or the reception link can be performed outside the cases of the transmission link and the reception link.

Further, the maintenance / replacement work of the adjusting resistor is easy.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an optical parallel link of the present invention.

FIG. 2 is a perspective view of a transmission link of the present invention.

FIG. 3 is a perspective view of a reception link of the present invention.

FIG. 4 is a plan view of a transmission link.

FIG. 5 is a plan view of a reception link.

FIG. 6 is a perspective view of an LD / fiber array module.

FIG. 7 is a perspective view of a PD / fiber array module.

FIG. 8 is a sectional view of a reception link.

FIG. 9 is a sectional view of a carrier.

FIG. 10 is a diagram showing the joining of analog signal processing circuit boards.

FIG. 11 is a diagram showing joining of digital signal processing circuit boards.

FIG. 12 is a diagram showing connections between circuit boards.

FIG. 13 is a connection diagram of a PD / fiber array module and a circuit board.

FIG. 14 is a diagram of an analog signal processing circuit board on the transmission side,
(A) is a plan view and (B) is a sectional view.

15A and 15B are diagrams of an analog signal processing circuit board, FIG. 15A is a plan view of a main part, and FIG. 15B is a cross-sectional view of the main part.

FIG. 16 is a diagram of an analog signal processing circuit board on the receiving side.

FIG. 17 is a diagram showing a connection between a power supply and a ground of a circuit board.

FIG. 18 is a diagram showing wire bonding of bare chips.

FIG. 19 is a diagram of another example of bare chip wire bonding.

20A and 20B are views showing a mounting structure of the adjustment resistor, in which FIG. 20A is a plan view and FIG. 20B is a front view.

FIG. 21 is a configuration diagram of a conventional optical parallel link.

FIG. 22 is a view of a conventional transmission link, (A) is a sectional view,
(B) is a perspective view of a main part.

FIG. 23 is a view of a conventional receiving link, (A) is a sectional view,
(B) is a perspective view of a main part.

FIG. 24 is a cross-sectional view of a conventional carrier.

FIG. 25 is a diagram showing a connection between conventional circuit boards.

FIG. 26 is a connection diagram between a conventional LD / fiber array module and a circuit board.

FIG. 27 is a diagram of a conventional transmission-side circuit board.

FIG. 28 is a diagram of a conventional analog signal processing circuit board,
(A) is a plan view of important points, and (B) is a cross-sectional view of important points.

FIG. 29 is a diagram showing a conventional power supply / ground connection of a circuit board.

FIG. 30 is a view showing wire bonding of a conventional bare chip.

[Explanation of symbols]

 1 Transmission link 1-1,4-1 Case 1-11D, 4-11D Power supply terminal 1-11G, 1-11G Ground terminal 4 Reception link 7 Optical ribbon fiber 1-10 Input line 4-10 Output line 1-11 Input Terminal 4-11 Output terminal 10,60 Digital signal processing circuit board 11 Skew compensation / code conversion circuit 15,25,55,65 Carrier 27a Cu layer 17b, 27b Ni layer 17c, 27c Au layer 17a Ag / Pd layer 17-1 , 17-2,17-3 Au film 18-A1,18-A-1 Sn, Ag Non-flux solder sheet 20,50 Analog signal processing circuit board 21 LD drive circuit 24 Pad 29 Protective polyimide layer 30 LD / fiber array Module 31 LD array 32,41 Optical fiber array 32A, 41A Optical ribbon fiber 40 PD / fiber array module 42 PD array 50Z Amplification LSI 50-1 Ceramic substrate 50-2 Copper polyimide substrate 51 Amplifier circuit 51-1 Preamplifier circuit 51- 2 Main amplifier circuit 52 Limiter amplifier circuit 58-A, 68-A High melting point adhesive 58-B, 68-B Low Point bonding agent 59-1,59-2 Power supply pattern 61 Skew compensation / code conversion circuit 72A-1,72B-1,72A-2,72B-2,94A Signal pad 71-1,71-2 Power pad 73 , 74 Bonding wire 80 Adjusting resistance 85 L-shaped terminal 90 Bare chip 90Z LD drive LSI 91 Signal electrode 93A Power supply pad 93B Grounding pad 95 Damping resistance film 95-1 Damping resistor 96A Inner layer power supply pattern 96B Inner layer ground pattern 97A, 97B Beer 98 Protrusion 99 Protrusion

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masao Hosogai, 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Yasuhide Kuroda, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Hiroshi Higashiguchi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Fujitsu Limited

Claims (16)

[Claims] 1. A transmission link for receiving an electric signal from an input line, converting the signal into an electric signal and transmitting the optical signal, and a receiving link for receiving the optical signal and converting the signal to an electric signal and transmitting the electric signal from an output line. In an optical parallel link connected by an optical ribbon fiber, the transmission link includes a digital signal processing circuit board on which a skew compensation / code conversion circuit is formed, an analog signal processing circuit board on which an LD drive circuit is formed, An LD / fiber array module connected to an optical ribbon fiber is arranged and connected in this order and housed and sealed in a case, and the reception link is a PD / PD connected to the optical ribbon fiber.
A fiber array module, an analog signal processing circuit board on which an amplifier circuit and a limiter amplifier circuit are formed, and a digital signal processing circuit board on which a skew compensation / code conversion circuit is formed are connected in this order and housed in a case. An optical parallel link characterized by being stopped. 2. The optical signal processing circuit board according to claim 1, wherein a copper polyimide board is formed on a ceramic board, and the digital signal processing circuit board is made of glass ceramics. Parallel link. 3. The analog signal processing circuit board according to claim 2, which is adhesively mounted on an upper surface of a carrier through a high melting point bonding agent, and the carrier is bonded and mounted on a bottom plate of the case through a low melting point bonding agent. Alternatively, the digital signal processing circuit board according to claim 2 is fixedly mounted on the bottom plate of the case by screw means, and the digital signal processing circuit board according to claim 2 is bonded and mounted on the upper surface of the other carrier through a high melting point bonding agent, and the other carrier is low. An optical parallel link characterized in that it is adhesively mounted on a bottom plate of a case via a melting point bonding agent, or is fixedly mounted on the bottom plate of the case by a screw means. 4. The carrier according to claim 3, wherein the bottom length is substantially equal to the length of the analog signal processing circuit board or the digital signal processing circuit board on which the bottom surface is mounted, and the top surface length of the carrier is the analog signal processing circuit board or An optical parallel link characterized by being smaller than the length of a digital signal processing circuit board. 5. A Cu layer, a Ni layer, and an Au layer are formed in this order on the rear surface of the analog signal processing circuit board according to claim 4, and an Au film is formed on the upper surface of the carrier according to claim 4. An optical parallel link characterized in that a signal processing circuit board and the carrier are bonded together via non-flux solder. 6. An Ag / Pd layer, a Ni layer, and an Au layer are formed in this order on the back surface of the digital signal processing circuit board according to claim 4, and an Au film is formed on the upper surface of the carrier according to claim 4. An optical parallel link characterized in that the digital signal processing circuit board and the carrier are bonded together via non-flux solder. 7. A signal transmission path connecting the digital signal processing circuit board and the analog signal processing circuit board according to claim 1, wherein two parallel lines are paired to transmit the same signal in parallel. The signal pad spacing of the signal transmission path is smaller than the distance between the signal pads of another pair of adjacent signal transmission paths, and the signal pads are arranged close to the side edge of the digital signal processing circuit board, The signal pads are arranged in close proximity to the side edges of the analog signal processing circuit board so as to face the signal pads of the digital signal processing circuit board, and the signal pads are arranged at the side edges of the digital signal processing circuit board. A power supply pad is disposed at a predetermined distance from the pad, and a power supply pad is disposed on the side edge of the analog signal processing circuit board facing the power supply pad on the side edge portion of the analog signal processing circuit board. , The digital A bonding wire connecting between the signal processing circuit board and the power supply pad opposed to the analog signal processing circuit board is provided with a bonding wire facing the digital signal processing circuit board and the analog signal processing circuit board. An optical parallel link characterized by being longer than the bonding wire that connects the two. 8. The respective electrodes of the PD array of the PD / fiber array module according to claim 1, and the amplification LS mounted on the analog signal processing circuit board according to claim 1.
An optical parallel link, characterized in that the signal electrode of I is directly connected via a bonding wire. 9. An LD driving LSI is mounted on the analog signal processing circuit board of the transmission link according to claim 1,
A signal pad connected to a signal electrode of the D drive LSI via a bonding wire is formed on the surface of the analog signal processing circuit board, and a damping resistance film formed on an inner layer of the analog signal processing circuit board is formed. An optical parallel link characterized by being connected to the signal pad via a beer. 10. The pad formed on the analog signal processing circuit board or the digital signal processing circuit board according to claim 1, wherein the surface is plated with a good conductive metal layer, and the pad excluding the pad is formed. The protective resin layer provided so as to cover the surface of the analog signal processing circuit board or the digital signal processing circuit board is not formed on the upper side of the four edges of the analog signal processing circuit board or the digital signal processing circuit board. An optical parallel link characterized by: 11. The amplifying LSI mounted on the analog signal processing circuit board of a receiving link according to claim 1, wherein one half body has a preamplifier circuit and the other half body has a main amplifier circuit. The power supply pattern formed on the inner layer of the analog signal processing circuit board is divided into a power supply pattern for supplying power to the preamplifier circuit and a power supply pattern for supplying power to the main amplifier circuit. Optical parallel link. 12. The power supply pattern and the ground pattern provided corresponding to the bare chip mounted on the analog signal processing circuit board or the digital signal processing circuit board according to claim 1, are provided on different inner layers, respectively. The inner layer power supply pattern is connected to the power supply pad formed on the surface layer through a via having a predetermined impedance, and the inner layer ground pattern is formed on the grounding pad formed on the surface layer through a via having a predetermined impedance. An optical parallel link characterized by being connected via an optical parallel link. 13. The bare chip mounted on the analog signal processing circuit board or the digital signal processing circuit board according to claim 1, corresponding to the bare chip mounted on the surface layer of the analog signal processing circuit board or the digital signal processing circuit board. Signal electrodes, power supply electrodes, signal pads connected to the grounding electrodes via bonding wires, power supply pads, and grounding pads are formed in a plurality of rows, and each pad is made of a wide thick film. Optical parallel link characterized by being a thing. 14. The optical parallel circuit according to claim 13, wherein the power supply pad and the grounding pad are formed by arranging projections of a number equal to the number of bonding wires to be connected on a side edge. Link. 15. The signal pad, the power supply pad, and the ground pad according to claim 13 each have a via connected to an inner layer, and the pad connecting a plurality of bonding wires has a protruding portion on a side edge. An optical parallel link characterized in that the protrusion has a via. 16. An L-shaped terminal is arranged so as to insulate and penetrate a side wall of each case of the transmission link or the reception link according to claim 1, and a tip of the L-shaped terminal protruding into the case is the transmission link. Alternatively, the printed circuit board is mounted on the outside of the case by being connected to the circuit of the analog signal processing circuit board of the receiving link and inserting and connecting the through hole in the vertical portion of the L-shaped terminal protruding to the outside of the side wall. And an adjustment resistor mounted on the printed circuit board.