JPH08125106A - Resin sealed semiconductor device and production thereof - Google Patents

Abstract

PURPOSE: To prevent a package from warping by bonding a semiconductor chip to a die pad and then injecting a sealing resin while pressing the semiconductor chip with the resiliency of the support bar of the die pad through an upper die. CONSTITUTION: An adhesive tape is applied to a die pad and a semiconductor chip 1 is thermocompressed thereto before inner leads are wire bonded to outer terminals. The semiconductor chip 1 is then mounted, on the side opposite to the circuit forming side, on a protrusion 11 of a lower die 10b. Subsequently, the support bar 9 of the die pad is pressed through the upper die 10a to retain the semiconductor chip 1 by the resiliency of the support bar 9 thus suppressing displacement of the semiconductor chip 1. Finally, a sealing resin is injected into the space formed between the upper and lower dies 10a, 10b. Since the thickness of sealing resin is equalized at the upper and lower parts the semiconductor chip 1, the package can be protected against warping.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique effective when applied to a semiconductor chip package and a method for manufacturing the same.

[0002]

2. Description of the Related Art As a first conventional resin-sealed semiconductor device, as shown in FIG. 9, an adhesive layer such as silver paste or solder is provided on a die pad 2 of a lead frame on which a pattern is formed by stamping or etching. The semiconductor chip 1 is die-bonded via 5, the semiconductor chip 1 and the inner lead 3 are connected by a gold wire or the like 6, the outer lead 4 is solder-plated, and a forming process is performed through a marking process.

As a second conventional example, there is a structure (hereinafter referred to as "LOC structure") in which inner leads 3 for electrically connecting with an external terminal are laid over the semiconductor chip 1. As shown in FIG. 10, the inner leads 3 of the lead frame and the bus bar 16 on which a pattern is formed by stamping or etching and the semiconductor chip 1 are die-bonded by thermocompression bonding via an adhesive layer (adhesive tape) 5, Chip 1 and inner lead 3
Are connected by a gold wire or the like 6, the outer leads 4 are solder-plated, and a forming process is performed through a marking process.

The adhesive tape used at this time is generally 3
Having a layered structure, a thermosetting adhesive such as a polyimide resin, a phenol resin, an epoxy resin or a thermoplastic adhesive such as a polyimide resin or a polyether resin is provided on both surfaces of a substrate such as polyimide. It is attached. Thermoplastic adhesives are generally used due to problems such as storage stability and outgassing. Also, in the case of a thermosetting adhesive, after-curing is necessary after die bonding, but in the case of a thermoplastic adhesive, after-curing is not required, and it is generally due to problems such as storage stability and outgassing. A thermoplastic adhesive is used.

Further, as a third conventional example, Japanese Patent Laid-Open No. 4-1
As shown in FIGS. 11 (a) and 11 (b), which is disclosed in Japanese Patent No. 74551, there is a modified structure of the LOC structure in which the semiconductor chip 1 is fixed by using the shared inner lead 17, which is also the shared inner lead. Since wire bonding is performed on 17, the package thickness cannot be reduced in consideration of the loop height of the gold wire 6.

Further, as a fourth conventional example, Japanese Patent Laid-Open No. 6-9
As shown in FIGS. 12A and 12B described in Japanese Patent No. 7353, external terminals of the circuit are formed on the peripheral portion of the circuit forming surface of the semiconductor chip 1, and the circuit forming surface and the die pad are formed. In some cases, the inner leads and the external terminals are wire-bonded to each other via an adhesive film so that the external terminals are exposed.

Incidentally, FIG. 9 is a sectional view of a first conventional resin-sealed semiconductor device, and FIG. 10 is a sectional view of a second conventional resin-sealed semiconductor device, which is shown in FIG. Is a plan view of a third conventional resin-encapsulated semiconductor device, FIG. 12B is a sectional view of the same resin-encapsulated semiconductor device, and FIG. 12A is a fourth conventional resin-encapsulated semiconductor device. 12B is a plan view of the type semiconductor device, and FIG. 12B is a sectional view taken along the line AA ′ in FIG. 12A of the same resin-sealed semiconductor device. 9 to 12, 1
Is a semiconductor chip, 2 is a die pad, 3 is an inner lead, 4 is an outer lead, 5 is an adhesive layer (or adhesive tape), 6 is a gold wire, 7 is a sealing resin, 9 is a support bar, 16 is a bus bar, 17 Indicates a shared inner lead.

[0008]

Generally, DRAMs and S
An IC memory card is one example of the use of memory such as RAM. For example, in an IC memory card having a thickness of 3.3 mm, as shown in FIG.
In the case of the mm package, only two layers can be mounted. IC
When the package thickness is set to 0.5 mm or less in order to increase the packaging density of the memory card, the packaging density is doubled as compared with the case of using the 1 mm thick package as shown in FIG. In FIG. 13, 13 is a package,
Reference numeral 18 is a substrate, 19 is a panel, and 20 is a resin frame.

However, the above-mentioned first conventional technique, second conventional technique, and third technique have the following problems.

In the case of the first prior art shown in FIG. 9, when the thickness of the semiconductor chip 1 is 0.2 mm and the thickness of the die pad 2 is 0.08 mm, the thickness of the adhesive layer 5 of silver paste or solder. (0.01 mm), the loop height (0.12 mm) of the gold wire 6, the thickness (0.05 mm) of the sealing resin 7 for covering the gold wire 6 and the sealing resin 7 below the die pad 2. The total thickness of the package 13 and the thickness (0.17 mm) is 0.63 mm.

In this case, the package 13 has a thickness of 0.5.
The thickness of the semiconductor chip 1 or the die pad 2 may be reduced in order to reduce the thickness of the semiconductor chip 1 to 2 mm or less. The thickness of 2 must be 0.08 mm or more. Further, the loop height of the gold wire 6 is said to be 0.12 mm at the mass production level even if a low loop wire is used. Furthermore, in order to prevent the warp of the package after the mold post cure and the deformation of the die pad after resin sealing, the position of the enclosed material must be in the center of the package 13, and the thickness of the sealing resin 7 below the die pad 2 is The thickness is 0.17 mm, which is the same as the thickness of the sealing resin 7 on the semiconductor chip 1.

In the case of the second conventional technique shown in FIG. 10, when the thickness of the semiconductor chip 1 is 0.2 mm and the thickness of the die pad is 0.08 mm, the thickness of the adhesive layer 5 (adhesive: 0.008 mm / base material: 0.020 mm / adhesive:
0.008 mm) and the height obtained by subtracting the thickness of the inner lead 3 and the thickness of the adhesive layer 5 from the loop height (0.2 mm) of the gold wire 6 when bonded to the inner lead 3 on the semiconductor chip 1. (0.084 mm) and the thickness of the sealing resin 7 for covering the gold wire 6 (0.05 m
m) and the thickness of the sealing resin 7 below the semiconductor chip 1 (0.1
34 mm) and the total thickness of the package 13 is 0.3.
It becomes 584 mm.

Further, in the case of the third prior art shown in FIG. 11, when the thickness of the semiconductor chip 1 is 0.2 mm and the thickness of the common inner lead is 0.08 mm, the thickness of the adhesive layer 5 (adhesive Agent: 0.008 mm / base material: 0.02 mm / adhesive: 0.008 mm), thickness of the sealing resin 7 (0.05 mm) for covering the gold wire 6 and the semiconductor chip 1
The total thickness (0.17 mm) of the lower sealing resin 7 is 0.6
It will be 56 mm.

Therefore, the above-mentioned first prior art and second
In the related art and the third related art, 0.5 mm which can be used for an IC card having a four-stage structure as shown in FIG.
It is not possible to produce thin packages that are less than the thickness.

In the fourth prior art shown in FIG. 12, the loop height of the gold wire 6 can be ignored, so that the thickness of the package 13 can be reduced to 0.5 mm or less. , Has the following problems.

First, as shown in FIG. 12, the encapsulating resin 7 and the semiconductor chip 1 are provided on the active region of the semiconductor chip 1 (the region in which transistors, diodes, etc. are finely formed).
Since only the die pad 2 having an area smaller than the active region of the above exists, a photo-generated current occurs when light is irradiated, which causes a malfunction. The encapsulating resin 7 covering the semiconductor chip 1 contains carbon black so as not to transmit light. However, the material of the filler is transparent glass and the thickness of the encapsulating resin 7 is I cannot block the light because it is very thin.

Further, as shown in FIG. 12, since there is a region where the die pad 2 does not exist on the semiconductor chip 1, the thickness of the sealing resin 7 below the semiconductor chip 1 and the thickness of the sealing resin 7 on the die pad 2 are different from each other. If the two are equal, this die pad 2
Since the thickness of the sealing resin 7 on the die pad 2 becomes thicker by the thickness of the sealing resin 7 on the region where no semiconductor exists, as a result, there is a difference between the upper and lower sealing resin thicknesses of the semiconductor chip 1.
A warp of the package 13 of 0.1 mm occurs.

Further, the adhesive tape 5 and the semiconductor chip 1 in the region where the die pad 2 does not exist on the semiconductor chip 1 described above.
Means that sufficient pressure is not applied at the time of die-bonding, so that sufficient bonding is not achieved.
When reflow for mounting is performed in a state where the package has absorbed moisture, a package crack occurs from this unbonded portion. In addition, even if package cracks do not occur, moisture is likely to accumulate in the unbonded portion, which causes a problem in device reliability due to aluminum corrosion or leakage.

Further, at the time of resin sealing, the semiconductor chip 1 is supported by the support bar 9, and the support bar 9 is only upset and positioned at the center of the package 13. Therefore, the semiconductor chip 1 is pushed by the resin and sealed. Objects (inner lead 3, semiconductor chip 1, gold wire 6, etc.) are displaced. When the resin thickness is thick, it does not cause much problem, but in the case of a thin package having a thickness of 0.5 mm or less, this displacement causes the semiconductor chip 1, die pad 2, gold wire 6 and the like to go out of the resin of the package 13. Easy to expose,
The package 13 becomes defective in appearance. Further, even if these are not exposed, the balance in the package 13 is lost, which causes warpage of the package. Further, since the flow path of the resin is narrowed, if the resin flow balance at the time of resin encapsulation is disturbed by the displacement of the encapsulated material of the package 13, the molding yield such as unfilling failure of the sealing resin 7 will be deteriorated.

Furthermore, the thickness of the package 13 is 0.5 mm.
If it becomes less than the following, the strength of the package 13 becomes low and the handling property becomes poor. In the semiconductor device shown in FIG. 12, the bending strength of the package 13 is the same as that of the semiconductor chip 1 and the sealing resin 7.
Keep only strength. The method for measuring the bending strength of the package 13 is to fix the package 13 having a size of 10 × 18.4 mm to a fixing base 15 having an interval of 14 mm as shown in FIG.
The central portion of the package 13 is pushed by the push-pull gauge 14. The measured value of the push-pull gauge 14 obtained at this time was defined as the bending strength of the package 13. At this time, the conventional 1 mm-thick package 13 has a bending strength of 10 kgf, but the bending strength of the package 13 shown in FIG. 12A is only about 1 kgf.

It is an object of the present invention to provide means for suppressing generation of photogenerated current and package warpage and improving package strength, as compared with a conventional resin-sealed semiconductor device having a package thickness of 0.5 mm or less. And

[0022]

According to another aspect of the present invention, there is provided a resin-encapsulated semiconductor device, wherein an external terminal of the circuit is provided on a peripheral edge of a surface of a semiconductor chip having a circuit formation region, and the circuit is provided. A surface having a formation area and a die pad covering the entire surface of the circuit formation area are adhered to each other via an insulating layer so that the external terminals are exposed, and the inner lead provided on the side of the semiconductor chip and the external surface. The terminal is characterized by being wire-bonded.

According to a second aspect of the present invention, in the resin-sealed semiconductor device of the present invention, the external terminals of the circuit are provided on the periphery of the surface of the semiconductor chip having the circuit formation region, and the circuit formation region is provided. A surface and a die pad covering the entire surface of the circuit formation region are bonded via an insulating adhesive tape located inside the die pad so that the external terminals are exposed, and are provided on the sides of the semiconductor chip. The inner lead and the external terminal are wire-bonded to each other.

Further, in the resin-sealed semiconductor device of the present invention as set forth in claim 3, the die pad is made of Invar or Super Invar. Is.

Further, in the method of manufacturing a resin-sealed semiconductor device according to the present invention, the surface having the circuit forming area of the semiconductor chip having the external terminals of the circuit at the periphery of the surface having the circuit forming area. And a die pad covering the entire surface of the circuit formation region are bonded via an insulating layer so that the external terminals are exposed, and the inner leads provided on the semiconductor chip side and the external terminals are wire-bonded to the bottom surface. On a lower die having a protrusion of a predetermined height, with the support bar being located on the same plane as the die pad, the surface of the semiconductor chip opposite to the circuit forming surface is in contact with the protrusion. The semiconductor chip is placed on the upper mold, and pressure is applied through the upper mold to generate elastic force in the support bar, and a resin for sealing is provided in the space formed by the lower mold and the upper mold. It is characterized in that injection.

[0026]

With the above structure, the entire active area of the semiconductor chip is covered by the die pad of the lead frame, and the inner leads are arranged around the semiconductor chip, which is excellent in light-shielding property, does not warp the package, and has a conventional package thickness. It is possible to manufacture a thin package having a bending thickness higher than that of a thin package of 0.5 mm or less and a package thickness of 0.5 mm or less.

When the semiconductor chip and the die pad are die-bonded by using the adhesive tape, the semiconductor chip and the die pad are adhered by the entire adhesive tape, so that the adhesive tape is sufficiently pressed at the time of die-bonding, and the package crack is generated. Can be prevented.

Further, warping of the package can be suppressed by using Invar or Super Invar having a small coefficient of thermal expansion in the die pad portion.

Furthermore, by pressing the semiconductor chip or the like by utilizing the spring property (elastic force) of the support bar, it is possible to prevent the inclusions such as the inner lead, the semiconductor chip, and the gold wire from being displaced.

[0030]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 1A is a plan view of the resin-sealed semiconductor device of the first embodiment of the present invention, FIG. 1A is a sectional view of the resin-sealed semiconductor device, and FIG. FIG. 4 is a cross-sectional view of the resin-sealed semiconductor device of the second embodiment, FIG. 3 is a diagram for explaining the manufacturing process of the present invention, and FIG. 4A is manufactured by the process shown in FIG. 6A and 6B are perspective views of the resin-sealed semiconductor device, FIG. 5B is a cross-sectional view thereof, and FIGS. 5A to 5C are views for explaining the effect of the present invention on a package crack. 7A to 7C are diagrams for explaining the effect of the present invention on the occurrence of voids, and FIG.
FIG. 7A is a plan view of a resin-sealed semiconductor device according to a third embodiment of the present invention, and FIG. 8B is a sectional view of the resin-sealed semiconductor device. 1 to 7, 1 is a semiconductor chip, 2 is a die pad, 3 is an inner lead, 4 is an outer lead, 5a is an adhesive tape, 5b is a paste, 6 is a gold wire, 7 is a sealing resin, and 9 is a support bar. 10a is an upper mold, 10b is a lower mold, 11 is a protrusion, 12 is a void, and 13 is a package.

The first embodiment of the present invention will be described below.

A lead frame having a thickness of 0.08 mm and made of Kovar having a die pad 2 as shown in FIG. 1A is used. For example, the size of the die pad 2 of this lead frame is 5.3 × 9.4 mm. When the size of the semiconductor chip 1 is 5.7 × 11.0 mm, the adhesive tape 5a for adhering the semiconductor chip 1 is cut in advance to a size of 4 × 7.4 mm, and the die pad 2 is attached at the temperature. Stick at 300 ° C.

The adhesive tape 5a has a three-layer structure in which a thermoplastic adhesive is applied to both sides of a polyimide base material (adhesive: 0.
008 mm / Substrate: 0.020 mm / Adhesive: 0.00
8 mm).

Next, as shown in FIG. 1B, the adhesive tape 5a previously attached to the die pad 2 was thermocompression-bonded to the surface of the semiconductor chip 1 using a LOC die bonder. Crimping conditions are temperature 380 ° C. and pressure 80 kg.
f / cm ² and the time was 1 second. Then 0.025
Using a low loop gold wire 6 with a diameter of mm, the loop height was controlled to 0.12 mm and wire bonding was performed. Furthermore, the looping conditions of the wire bonder may be optimized to forcibly reduce the loop. Further, the die pad 2 and the support bar 9 are not plated with silver and are not processed by up-setting or the like, but the inner lead 3 is down-set by about 50 μm, and further, the tip of the inner lead 3 is Ring silver plated.

As a result of an experiment, the inventor did not generate a package crack when the adhesive tape 5a was located on the die pad 2 as shown in FIGS. 5 (a) and 5 (c), but FIG. As shown in b), it has been confirmed that package cracks occur when the adhesive tape 5a is present in the area where the die pad 2 is not present. It is considered that this is because the adhesive tape 5a in the region where the die pad 2 does not exist is not pressed at the time of bonding, so that the adhesive tape 5a cannot obtain a sufficient adhesive force to the semiconductor chip 1. 6 (b) and 6 (c)
As shown in, the adhesive tape 5 is attached to one die pad.
If there are two a's, a void will be generated.
When one adhesive tape 5a was provided on the entire surface as shown in (a), no void was generated.

From the above, in the present invention, the adhesive tape for connecting the semiconductor chip 1 and the die pad 2 is better placed in the area inside the die pad as shown in FIG. 1 (a).

Further, in the first embodiment of the present invention and the second and third embodiments described below, as a lead frame material, instead of Kovar, the coefficient of thermal expansion is smaller than that of Kovar. When Invar, which is a% Ni-Fe alloy, is used, the warpage of the package can be reduced more than when Kovar is used. Further, as the lead frame material of the present invention, instead of Kovar, 32% Ni-5% Co-Fe, which has a smaller coefficient of thermal expansion than Invar, is used.
When the alloy Super Invar was used, the package warpage could be further reduced compared to the case where Invar was used. For example, in the case of the first embodiment, when the lead frame material is invar, the warp of the package can be reduced by 50% as compared to Kovar, and when the superinvar is used as compared with Kovar, the package warp can be reduced by 60%. did it.

After that, the upper mold 10a shown in FIG.
Using the lower mold 10b having four protrusions 11,
Resin sealing was performed at 60 ° C. At the time of this resin sealing, the semiconductor chip 1 is exposed, the support bar 9 is exposed, and the gold wire 6 is exposed.
With respect to the exposure and the warp of the package, it is necessary to prevent the displacement of the inclusion in the package due to the resin pressure during resin sealing.

Therefore, according to the present invention, an elastic force is generated in the support bar 9, and the elastic force is utilized to suppress the displacement of the inclusion.

First, the semiconductor chip 1, the die pad 2, and the inner lead 3 which are die-bonded in the above process are mounted so that the surface of the semiconductor chip 1 opposite to the circuit forming surface is in contact with the protrusion 11. For example, when the thicknesses of the enclosed materials are set as described above, the semiconductor chip 1 is attached to the lower die 10
The distance Δ between the support bar 9 and the opening surface of the lower mold 10b when it is mounted on the protrusion 11 provided in b is 46 μm.
And

Then, the support bar 9 is pressed through the upper mold 10a, and the sealing resin 7 is injected into the space formed between the upper mold 10a and the lower mold 10b. At this time, when the semiconductor chip 1 is supported by the protrusions 11, the semiconductor chip 1 tends to be displaced upward, but the springiness of the support bar 9 which is not upset suppresses displacement of the semiconductor chip 1 onto the semiconductor chip 1. The semiconductor chip 1 may be located at the center of the package 7.

When the support bar 9 is upset, the spring property is lost, and when an excessive pressing load is applied through the upper mold, the semiconductor chip 1 is damaged and the gold wire 6 is damaged. Therefore, it is necessary to optimize the pressing load at a level at which the semiconductor chip 1 does not float during mold formation. Further, in order to adjust the pressing load, the width of the support bar 9 is adjusted, or the balance of the inner lead 3 connected by the outer lead 4 and the gold wire 6 is shifted to the center of the package to hold down the support bar 9. Adjusting the weight is performed.

Further, in this embodiment, the sealing resin 7 to be injected is a biphenyl resin, and the filler is 78 wt% in order to reduce the package warpage so as not to impair the filling property, and the diameter is 50 μm. A spherical resin having a degree of about 30 to 50 poises and an ultra low viscosity resin having 40 poises in this embodiment are used, but the present invention is not limited thereto.

Further, a multi-plunger was used as the molding die, and the gate size, air bend, etc. were optimized so as to prevent generation of voids and ups and downs of the semiconductor chip 1. When the pressure-reducing molding in which the pressure was reduced from the air bend was performed, it was possible to perform molding with a viscosity higher than the above viscosity.

Further, by holding the semiconductor chip 1 with the support bar 9 as described above, the semiconductor chip 1 can be accurately positioned at the center of the package, and moldability, package warpage, etc. can be greatly improved. Although improved, on the other hand, in the present invention, the die pad 2 is package 13
Since the inner lead 3 is located on the upper side of the center, the inner lead 3 is also placed on the upper side as compared with the case where the support bar is upset processed, so that the gold wire 6 is easily exposed. Therefore, the tip of the inner lead 3 is down-set as shown in FIG. 4, whereby the gold wire 6 can be prevented from being exposed and the range of molding conditions can be significantly widened.

Then, post-curing was performed at 175 ° C. for 5 hours after the resin sealing. After that, forming was performed through the plating and marking processes.

As a second embodiment of the present invention, FIG.
A lead frame having a die pad 2 as shown in FIG. 2A is used, and as shown in FIG. 2, a thermosetting silver-free paste is used instead of the polyimide adhesive tape 5a used in the first embodiment. 5b was applied to the die pad 2 by the dispensing method and the semiconductor chip 1 was attached. Then, it was cured in an oven at 180 ° C. for 1 hour.

As in the first embodiment, the subsequent steps were performed in the order of wire bonding, resin sealing, plating, marking and forming.

Further, as a third embodiment of the present invention, FIG.
Die pad 2 divided as shown in (a) and (b)
A lead frame having a thickness of 0.080 mm and made of Kovar was used. As the adhesive tape 5a for fixing the semiconductor chip 1, the same adhesive tape 5a made of polyimide as in the first embodiment was used. After that, the die pad 2 was upset (0.12 mm) as in the first embodiment,
Die bond, wire bond, resin sealing, plating, mark, and forming were performed. As shown in FIGS. 7A and 7B, the die pad 2 has a gap of about 0.1 mm, but the light-shielding property is good even in such a pattern.

[0051]

As described above in detail, in the resin-sealed semiconductor device of the present invention, the highest point of the gold wire loop comes to the position of the upper surface of the die pad. Only the package thickness can be reduced, and as a result, the designed package thickness is 0.424.
Can be thinned to mm. The 0.424 mm package thickness is the sum of the material thicknesses shown below. Sealing resin thickness (0.05 mm) required to cover the gold wire, die pad thickness (0.08 mm), adhesive tape thickness (0.
036mm), loop height of gold wire (0.12m
The height (0.0) obtained by subtracting the thickness of the die pad (0.08 mm) and the thickness of the adhesive tape (0.036 mm) from m).
04 mm), the thickness of the semiconductor chip (0.2 mm), and the thickness of the sealing resin under the semiconductor chip (0.054 mm).
However, considering the molding failure at the time of resin sealing at this time,
The thickness of the sealing resin on the die pad and the thickness of the sealing resin under the semiconductor chip were increased to make the package thickness 0.45 mm, but the molding yield at the time of resin sealing was good.

Further, since the die pad covers the entire active area of the semiconductor chip, no photo-generated current is generated, and the thickness of the sealing resin on the die pad is equal to the thickness of the sealing resin below the semiconductor chip. The package warp is only about 0.02 mm. In addition, the conventional 0.5
The bending strength of a thin package having a thickness of mm or less was only about 1 kgf, but since the structure covers the entire active area of the semiconductor chip, the strength of the package is about double. Then, it was mounted on a mounting board or the like using a mounting machine, but it was confirmed that the thin semiconductor device of the present invention did not cause damage to the package or the semiconductor chip and did not cause damage during transportation.

Further, since the semiconductor chip and the die pad are bonded together with the adhesive tape as a whole, the adhesive tape is sufficiently pressed at the time of die bonding, so that the generation of package cracks can be prevented.

Further, by using Invar or Super Invar having a small thermal expansion coefficient in the die pad portion, it is possible to further suppress the warpage of the package.

Furthermore, by pressing the semiconductor chip against the protrusion of the lower mold by utilizing the springiness of the support bar, the semiconductor chip can be accurately positioned in the center of the package, and molding is conventionally performed. Improves performance and reduces package warpage.

As described above, according to the present invention, it is possible to secure moldability equivalent to that of the TSOP structure, and to stably produce a resin-sealed semiconductor device having a thickness of 0.45 mm by using the wire bond method. You can In addition, the warp of the package was 10 μm or less, and the coplanarity, which was about 100 μm in the related art and which indicates the degree of height irregularity between outer leads, was 50 μm at the maximum, and no problem occurred even when mounted on an IC card. As a result, the ultra-thin IC package, especially the IC card, can have a mounting density twice as high as that of the conventional TSOP structure, and the IC card can have a large capacity and a low price.

[Brief description of drawings]

1A is a plan view of a first embodiment of the present invention, and FIG. 1B is a sectional view of the same.

FIG. 2 is a sectional view of a second embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the present invention.

4A is a perspective view of a resin-sealed semiconductor device manufactured by the process shown in FIG. 3, and FIG. 4B is a cross-sectional view of the resin-sealed semiconductor device.

FIG. 5 is a diagram for explaining the effect of the present invention.

FIG. 6 is a diagram for explaining the effect of the present invention.

7A is a sectional view of a third embodiment of the present invention, and FIG. 7B is a plan view of the same.

FIG. 8 is a diagram for explaining a method of measuring the strength of a package.

FIG. 9 is a cross-sectional view of a first conventional resin-encapsulated semiconductor device.

FIG. 10 is a sectional view of a second conventional resin-sealed semiconductor device.

11A is a plan view of a third conventional resin-sealed semiconductor device, and FIG. 11B is a sectional view of the same.

12A is a plan view of a fourth conventional resin-sealed semiconductor device, and FIG. 12B is a sectional view of the same.

13A is a sectional view of an IC card having a two-stage structure, and FIG. 13B is a sectional view of an IC card having a four-stage structure.

[Explanation of symbols]

 1 Semiconductor Chip 2 Die Pad 3 Inner Lead 4 Outer Lead 5a Adhesive Tape 5b Paste 6 Gold Wire 7 Sealing Resin 9 Support Bar 10a Upper Mold 10b Lower Mold 11 Projection 12 Void 13 Package

Claims (4)

[Claims] 1. A semiconductor chip is provided with an external terminal of the circuit on a peripheral edge of a surface having a circuit forming area, and a surface having the circuit forming area and a die pad covering the entire surface of the circuit forming area have the external terminal. The resin-encapsulated semiconductor device is characterized in that it is bonded via an insulating layer so as to be exposed, and the inner lead provided on the side of the semiconductor chip and the external terminal are wire-bonded. 2. A semiconductor chip is provided with an external terminal of the circuit on a peripheral edge of a surface having a circuit forming area, and a surface having the circuit forming area and a die pad covering the entire surface of the circuit forming area are the external terminals. To be exposed via an insulating adhesive tape located inside the die pad, and the inner lead provided on the side of the semiconductor chip and the external terminal are wire-bonded. And a resin-encapsulated semiconductor device. 3. The resin-encapsulated semiconductor device according to claim 1, wherein the die pad is made of Invar or Super Invar. 4. A surface having a circuit forming area of a semiconductor chip having an external terminal of the circuit on a periphery of a surface having a circuit forming area, and a die pad covering the entire surface of the circuit forming area.
Bonded via an insulating layer so that the external terminals are exposed,
The inner lead provided on the semiconductor chip side and the external terminal were wire-bonded, and the support bar was located on the same plane as the die pad on the lower die having a protrusion with a predetermined height on the bottom surface. In this state, the semiconductor chip is arranged such that the surface opposite to the circuit forming surface of the semiconductor chip comes into contact with the protrusion, and pressure is applied through the upper mold to generate elastic force on the support bar, A method of manufacturing a resin-encapsulated semiconductor device, which comprises injecting a sealing resin into a space formed by a lower mold and the upper mold.