JPH08124827A - Method of forming pattern - Google Patents
Method of forming patternInfo
- Publication number
- JPH08124827A JPH08124827A JP6257807A JP25780794A JPH08124827A JP H08124827 A JPH08124827 A JP H08124827A JP 6257807 A JP6257807 A JP 6257807A JP 25780794 A JP25780794 A JP 25780794A JP H08124827 A JPH08124827 A JP H08124827A
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- JP
- Japan
- Prior art keywords
- image
- forming
- pattern
- substrate
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はパターン形成方法に関
し、特に段差を有する基板上に紫外線露光を用いた微細
なパターン形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a pattern, and more particularly, to a method for forming a fine pattern on a substrate having a step using ultraviolet exposure.
【0002】[0002]
【従来の技術】半導体装置や超電導装置の製造工程にお
いては、段差が形成された基板上に微細なパターンを形
成する場合が多くある。例えば、ダイナミックランダム
アクセスメモリ(DRAM)等ではチップ内にメモリ素
子部と周辺回路部とが明確に分離されるが、メモリ素子
部にはキャパシタや素子分離層などが存在する為、周辺
回路部に対して1〜2μmの段差を有することになる。
以下段差を有する半導体基板上にポジ型のフォトレジス
トを用いてラインパターンを形成する場合について図7
を用いて説明する。2. Description of the Related Art In a process of manufacturing a semiconductor device or a superconducting device, a fine pattern is often formed on a substrate having a step. For example, in a dynamic random access memory (DRAM) or the like, a memory element portion and a peripheral circuit portion are clearly separated in a chip. However, since a capacitor and an element isolation layer are present in the memory element portion, the peripheral circuit portion is not provided. On the other hand, it has a step of 1-2 μm.
FIG. 7 shows a case where a line pattern is formed using a positive photoresist on a semiconductor substrate having steps.
Will be explained.
【0003】まず図7(a)に示すように、1.5μm
の段差2を有するシリコン基板1上にポジ型フォトレジ
スト膜3を形成する。次で段差の下段面及び上断面に
0.3μmの4本の密なラインパターンを形成する為の
マスク4を用いKrFエキシマ光5で露光する。[0003] First, as shown in FIG.
A positive photoresist film 3 is formed on a silicon substrate 1 having a step 2 of. Next, exposure is performed with KrF excimer light 5 using a mask 4 for forming four dense line patterns of 0.3 μm on the lower step surface and the upper cross section of the step.
【0004】マスク4を通過した光はマスク4の開口部
で回折される為、フォトレジスト膜3に達する時の光学
的正転像(マスクの開口部下で光強度が極大になる像:
以下単に正転像という)の光強度8は、図8に示すよう
に、破線で示したマスク通過後の光強度7に比べ実線で
示したように低下する。光強度比はこの時の光強度の最
大値Imax と最小値Imin とから次式で与えられる。Since the light passing through the mask 4 is diffracted at the opening of the mask 4, an optically normal image when reaching the photoresist film 3 (an image in which the light intensity is maximized below the opening of the mask:
As shown in FIG. 8, the light intensity 8 of a normal image (hereinafter simply referred to as a normal image) is lower than the light intensity 7 after passing through the mask shown by the broken line as shown by the solid line. Light intensity ratio is given by the following equation from a maximum value I max and the minimum value I min of the light intensity at this time.
【0005】 光強度比=(Imax −Imin )/(Imax +Imin ) 光軸方向における下段面と上段面の位置11A,12A
に対する下段面及び上段面の光強度比11,12との関
係を図9に示す。下段面と上段面の光強度分布におい
て、正転像の一定以上の光強度比が得られる範囲の中央
を露光時の焦点設定位置10Aとするが、図9に示され
るようにその範囲は極めて狭いものとなる。Light intensity ratio = (I max −I min ) / (I max + I min ) Positions 11A and 12A of the lower surface and the upper surface in the optical axis direction.
FIG. 9 shows the relationship between the light intensity ratios 11 and 12 of the lower surface and the upper surface with respect to. In the light intensity distributions of the lower surface and the upper surface, the center of the range in which the light intensity ratio of the normal image is equal to or higher than a certain value is set as the focus setting position 10A during exposure, but as shown in FIG. It will be narrow.
【0006】すなわち、図7(a)で説明した条件で、
投影レンズの開口数NA=0.45のステッパーを用い
ると、光強度比0.4が得られるラインパターンの焦点
深度は図9に示したように2.0μm程度あるが、下段
面及び上段面に共通な焦点深度は約0.5μmとなる。
焦点設定位置10Aは、この共通の焦点深度が得られる
範囲の中央に設定する。That is, under the conditions described with reference to FIG.
When a stepper having a numerical aperture NA = 0.45 of the projection lens is used, the depth of focus of a line pattern that provides a light intensity ratio of 0.4 is about 2.0 μm as shown in FIG. Is about 0.5 μm.
The focus setting position 10A is set at the center of the range where the common depth of focus can be obtained.
【0007】このようにして焦点位置10Aを決定して
露光し、現像することにより、図7(b)に示すよう
に、フォトレジストからなる4本の密な0.3μmのラ
インパターン6が段差の下段面及び上段面に形成され
る。In this way, the focus position 10A is determined, exposed, and developed, whereby four dense 0.3 .mu.m line patterns 6 made of photoresist are stepped, as shown in FIG. 7B. Is formed on the lower and upper surfaces.
【0008】上述したように、0.3μmの4本の密な
ラインパターンの形成で、レンズ開口数NA=0.4
5、照明のコヒーレンス因子σ=0.7のKrFエキシ
マステッパーを用いると、焦点深度は2.0μmあるに
もかかわらず、段差の上下面両方にラインパターンの形
成を行う場合の焦点深度は0.5μmと狭くなる。0.
5μmの焦点深度において、ウェハのそり、ステッパー
レンズの収差、焦点設定誤差等の焦点ずれ要因を考慮す
れば、実際に安定してパターンを形成することは極めて
困難である。As described above, by forming four dense line patterns of 0.3 μm, the lens numerical aperture NA = 0.4.
5. When a KrF excimer stepper with a coherence factor of illumination σ = 0.7 is used, the depth of focus when forming a line pattern on both the upper and lower surfaces of the step is 0. It becomes as narrow as 5 μm. 0.
At a focal depth of 5 μm, it is extremely difficult to actually form a stable pattern in consideration of defocus factors such as wafer warp, stepper lens aberration, and focus setting error.
【0009】この対策として、多層レジスト法や多重焦
点露光法等が提案されている。As a countermeasure, a multilayer resist method, a multi-focus exposure method, and the like have been proposed.
【0010】多層レジスト法は、例えば特公平4−66
097号報に記載されているように、段差を有する半導
体基板上に平坦化用の厚い下層レジスト膜とSiO2 か
らなる中間層と薄い上層レジスト膜を順次形成し、平坦
な上層レジスト膜に微細パターンを形成したのちこのパ
ターンを中間層に転写し、次でこの中間層をマスクとし
て下層レジストをエッチングするものである。The multilayer resist method is disclosed in, for example, Japanese Patent Publication No. 4-66.
As described in No. 097, a thick lower layer resist film for planarization, an intermediate layer made of SiO 2 and a thin upper layer resist film are sequentially formed on a semiconductor substrate having a step, and a flat upper layer resist film is finely divided. After forming a pattern, this pattern is transferred to an intermediate layer, and then the lower layer resist is etched by using this intermediate layer as a mask.
【0011】又、多重焦点露光法は、例えば特開昭63
−42122号公報に記載されているように、段差を有
する基板上にフォトレジスト膜を形成したのち、光軸上
の複数の位置で露光を行ない、焦点深度を拡大するもの
である。A multifocal exposure method is disclosed in, for example,
As described in JP-A-42122, after a photoresist film is formed on a substrate having a step, exposure is performed at a plurality of positions on an optical axis to increase the depth of focus.
【0012】[0012]
【発明が解決しようとする課題】しかしながら、上述し
た従来のパターン形成方法のうち多層レジスト法では、
レジストパターンの形成の為に3層の膜を形成し、各膜
をエッチングしなければならない為、工程が複雑になる
という問題点がある。However, among the above-mentioned conventional pattern forming methods, the multilayer resist method involves:
In order to form a resist pattern, three layers of films must be formed and each film must be etched, which causes a problem that the process becomes complicated.
【0013】又、多重焦点露光方法では、1つのパター
ンを形成する際に、複数回光軸方向に基板を移動して露
光を行なわなければならない為に、製造装置における動
作が複雑になり、処理能力が低下する等の問題点があ
る。Further, in the multi-focus exposure method, when forming one pattern, it is necessary to move the substrate in the optical axis direction a plurality of times to perform the exposure, which complicates the operation in the manufacturing apparatus, and the processing is performed. There are problems such as reduced ability.
【0014】本発明の目的は、複雑な工程を必要とする
ことなく、高段差を有する下段面及び上段面のフォトレ
ジスト膜を十分な焦点深度で露光し、精度の良い微細パ
ターンの形成が可能なパターン形成方法を提供すること
にある。An object of the present invention is to form a fine pattern with high accuracy by exposing a photoresist film on a lower step and an upper step having a high step with a sufficient depth of focus without requiring a complicated process. Another object of the present invention is to provide a simple pattern forming method.
【0015】[0015]
【課題を解決するための手段】本発明のパターン形成方
法は、段差を有する基板の主面にフォトレジスト膜を形
成する工程と、前記段差の下段面に光学的正転像(又は
反転像)を形成する為の第1の透光領域と前記段差の上
段面に光学的反転像(又は正転像)を形成する為の第2
の透光領域とを有するマスクを用いて前記フォトレジス
ト膜を露光したのち現像し、前記下段面及び前記上段面
に前記フォトレジスト膜からなるパターンを同時に形成
するものである。A pattern forming method of the present invention comprises a step of forming a photoresist film on a main surface of a substrate having a step, and an optical normal image (or a reverse image) on a lower surface of the step. And a second light-transmitting region for forming an optically inverted image (or a normal image) on the upper surface of the step.
The photoresist film is exposed using a mask having a light-transmitting region and then developed to simultaneously form a pattern of the photoresist film on the lower surface and the upper surface.
【0016】[0016]
【作用】くり返しパターンを有するマスクを用いて露光
する場合は、通常図10(a)に示すようなパターンの
正転像が用いられる。この時の正転像の光強度は極大点
にある。When performing exposure using a mask having a repeating pattern, a normal image of a pattern as shown in FIG. 10A is usually used. At this time, the light intensity of the normal image is at the maximum point.
【0017】次にパターンの焦点位置をずらしていくと
光強度分布は変化し、極大点は図10(b)に示すよう
に減少し、光学的反転像(マスクの遮光部下で光強度が
極大になる像:以下単に反転像という)が現われ、遂に
は図10(c)に示すように、光強度が極大の反転像と
なる。本発明はこの現象を利用して段差を有する基板の
下段面及び上段面に同一露光操作によりレジストパター
ンを形成するものである。Next, when the focus position of the pattern is shifted, the light intensity distribution changes, the maximum point decreases as shown in FIG. 10B, and the optically inverted image (the light intensity becomes maximum under the light shielding portion of the mask). (Hereinafter, simply referred to as an inverted image) appears, and finally, as shown in FIG. 10C, the inverted image has the maximum light intensity. The present invention utilizes this phenomenon to form a resist pattern on the lower and upper surfaces of a stepped substrate by the same exposure operation.
【0018】正転像と反転像における最も光強度比が高
い焦点位置は数μm離れており、その距離(焦点間距
離)はステッパーの光学照明条件により変化する。従っ
て、この焦点間距離が基板の段差と一致するような光学
照明条件を選ぶことにより、基板の下段面に正転像(又
は反転像)を、そして上段面に反転像(又は正転像)を
同時に形成することができる。The focal position having the highest light intensity ratio between the normal image and the inverted image is several μm apart, and the distance (inter-focal distance) varies depending on the optical illumination conditions of the stepper. Therefore, by selecting an optical illumination condition such that the distance between the focal points coincides with the step of the substrate, a normal image (or inverted image) is formed on the lower surface of the substrate, and a reversed image (or normal image) is formed on the upper surface. Can be simultaneously formed.
【0019】光学的正転像と反転像を形成する為の最適
な光学照明条件はシュミレータを用いて定める。The optimal optical illumination conditions for forming the optically normal image and the inverted image are determined using a simulator.
【0020】例えば、パターンの寸法(ラインアントス
ペース)を0.3μm、照明のコヒーレンスファクタσ
を0.3,露光光(KrFエキシマステッパー)の波長
λを248nmとし、レンズの開口数NAをある値(例
えば0.5)に選んでパターンの正転像と反転像を作
り、シュミレータにより焦点の位置(距離)をずらして
各像の最適な光強度比とこの時の焦点間距離を求める。
開口数NAを変化させて求めた焦点間距離の一例を図3
に示す。図3より基板に1.3〜2.0μmの段差があ
る場合は、開口数NAを0.4〜0.6に調整すること
により、正転像と反転像を容易に同一基板上に形成でき
ることが分る。For example, the pattern size (line ant space) is 0.3 μm, and the illumination coherence factor σ
Is set to 0.3, the wavelength λ of the exposure light (KrF excimer stepper) is set to 248 nm, the numerical aperture NA of the lens is set to a certain value (for example, 0.5), and a normal image and an inverted image of the pattern are formed. The optimum light intensity ratio of each image and the inter-focal distance at this time are obtained by shifting the position (distance) of.
FIG. 3 shows an example of the inter-focal distance obtained by changing the numerical aperture NA.
Shown in According to FIG. 3, when the substrate has a step of 1.3 to 2.0 μm, the normal image and the inverted image are easily formed on the same substrate by adjusting the numerical aperture NA to 0.4 to 0.6. See what you can do.
【0021】尚、露光に用いる正転像と反転像の光強度
比が大幅に異なる場合は、形成されるレジストパターン
の精度が低下する恐れがあるが、マスクの寸法や露光量
の局所的調整を行うことにより、同一幅の微細なレジス
トパターンを精度良く形成できる。When the light intensity ratio of the normal image and the reverse image used for exposure is significantly different, the accuracy of the formed resist pattern may be reduced, but the mask size and the exposure amount are locally adjusted. By performing the above, it is possible to accurately form a fine resist pattern having the same width.
【0022】[0022]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【0023】図1(a),(b)は本発明の第1の実施
例を説明する為の半導体チップの断面図である。FIGS. 1A and 1B are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention.
【0024】まず図1(a)に示すように、素子等の形
成により1.7μmの段差2の形成されたシリコン基板
1上にポジ型のフォトレジスト膜3を形成する。次で下
段面2A及び上段面2Bに同時に幅0.3μmの4本の
密なラインパターンを形成する為にマスクを用いKrF
エキシマ光5により露光するが、この時のマスクとして
は、下段面2Aに正転像を形成する為の格子状開口を有
する第1の透光領域4Aと、上段面に反転像を形成する
為の格子状開口を有する第2の透光領域4Bとを有する
ものを用いる。First, as shown in FIG. 1A, a positive photoresist film 3 is formed on a silicon substrate 1 on which a step 2 of 1.7 μm is formed by forming elements and the like. Next, a mask is used to form four dense line patterns having a width of 0.3 μm simultaneously on the lower step surface 2A and the upper step surface 2B using a mask.
Exposure is performed with excimer light 5. The mask used at this time is a first light-transmitting region 4A having a lattice-like opening for forming a normal image on the lower surface 2A, and a reversal image on the upper surface. And a second light-transmitting region 4B having a lattice-shaped opening.
【0025】このマスクを用いて露光する場合、下段面
2Aには図2(a)に示す正転像8Aが、そして上段面
2Bには図2(b)に示す反転像9Aが得られ、かつ各
像の焦点間距離が1.7μmになるような光学照明条件
を用いる。本第1の実施例の場合は、レンズ開口数NA
=0.45,照明のコヒーレンスファクタσ=0.3の
KrFエキシマステッパーを用いることにより、焦点間
距離と段差(1.7μm)を一致させることができる。
この時の焦点位置と光強度比との関係を図4に示す。光
強度比が0.4以上の時に解像するフォトレジスト膜を
用いた場合、正転像及び反転像のそれぞれの焦点深度1
8,19は1.3μmと1.0μmであり、下段面及び
上段面の両方に一度にパターンが形成可能な焦点深度も
1.0μmとなる。この時の正転像の焦点位置10は下
段面に合わせてある。When exposure is performed using this mask, the normal image 8A shown in FIG. 2A is obtained on the lower surface 2A, and the inverted image 9A shown in FIG. 2B is obtained on the upper surface 2B. In addition, the optical illumination condition is used so that the focal length of each image is 1.7 μm. In the case of the first embodiment, the lens numerical aperture NA
By using a KrF excimer stepper with a coherence factor of illumination = 0.45 and a coherence factor of illumination = 0.3, the distance between the focal points and the step (1.7 μm) can be matched.
FIG. 4 shows the relationship between the focus position and the light intensity ratio at this time. When a photoresist film that resolves when the light intensity ratio is 0.4 or more is used, the depth of focus of each of the normal image and the inverted image is 1
8, 19 are 1.3 μm and 1.0 μm, and the depth of focus at which a pattern can be formed on both the lower surface and the upper surface at one time is also 1.0 μm. At this time, the focal position 10 of the normal rotation image is adjusted to the lower step surface.
【0026】このようにして露光したフォトレジスト膜
3を現像することにより、図1(b)に示すように、下
段面2A及び上段面2B上にレジスト膜からなる4本の
密なラインパターン6A,6Bを形成する。By developing the photoresist film 3 exposed in this manner, as shown in FIG. 1B, four dense line patterns 6A made of a resist film are formed on the lower surface 2A and the upper surface 2B. , 6B.
【0027】図5(a),(b)は本発明の第2の実施
例を説明する為の半導体チップの断面図であり、本発明
を4本の密なスペースパターン形成に用いた場合を示
す。FIGS. 5A and 5B are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention, in which the present invention is used for forming four dense space patterns. Show.
【0028】まず図5(a)に示すように、1.5μm
の段差を有するシリコン基板1A上にポジ型フォトレジ
スト膜3を形成したのち、下段面に正転像を形成する為
の4本の格子状開口を有する第1の透光領域14Aと、
上段面2Bに反転像を形成する為の5本の格子状開口を
有する第2の透光領域4Bとを有するマスクを用い、K
rFエキシマ光5を用いて露光する。First, as shown in FIG.
After a positive photoresist film 3 is formed on a silicon substrate 1A having a step, a first light-transmitting region 14A having four lattice-shaped openings for forming a normal rotation image on a lower step surface;
Using a mask having a second light-transmitting region 4B having five lattice-shaped openings for forming an inverted image on the upper step surface 2B, K
Exposure is performed using rF excimer light 5.
【0029】このマスクを用いて露光する場合、下段面
2Aには図6(a)に示す正転像8Bが、そして上段面
2Bには図6(b)に示す反転像9Bが得られ、かつ各
像の焦点間距離が1.5μmになるような光学照明条件
を用いる。本第2の実施例の場合は、レンズ開口数NA
=0.5,照明のコヒーレンスファクターσ=0.3の
KrFエキシマステッパーを用いることにより、各像の
焦点間距離と段差(1.5μm)を一致させることがで
きる。光強度比が0.4以上の時に解像するフォトレジ
スト膜を用いた場合、正転像及び反転像のそれぞれの焦
点深度は図4に示した第1の実施例の場合と同程度とな
り、下段面及び上段面の両方に一度にパターンが形成可
能な焦点深度も1.0μmであった。When exposure is performed using this mask, a normal image 8B shown in FIG. 6A is obtained on the lower surface 2A, and a reverse image 9B shown in FIG. 6B is obtained on the upper surface 2B. Optical illumination conditions are used so that the focal length of each image is 1.5 μm. In the case of the second embodiment, the lens numerical aperture NA
By using a KrF excimer stepper having a coherence factor of σ = 0.5 and an illumination coherence factor of σ = 0.3, the distance between the focal points of each image and the step (1.5 μm) can be made to coincide. When a photoresist film that resolves when the light intensity ratio is 0.4 or more is used, the respective focal depths of the normal image and the inverted image are substantially the same as those of the first embodiment shown in FIG. The depth of focus at which a pattern could be formed on both the lower surface and the upper surface at one time was also 1.0 μm.
【0030】このようにして露光したフォトレジスト膜
3を現像することにより、図5(b)に示すように、下
段面2A及び上段面2B上にレジスト膜からなる4本の
密なスペースパターン16A,16Bを形成する。By developing the photoresist film 3 exposed in this manner, as shown in FIG. 5B, four dense space patterns 16A made of a resist film are formed on the lower surface 2A and the upper surface 2B. , 16B.
【0031】上記実施例では、ポジ型フォトレジスト膜
を用い、4本の密なパターンを形成する場合について説
明したが、フォトレジスト膜はネガ型のものでもよく、
レジストパターンは1本以上のものを形成できる。更
に、本発明は、半導体基板上のみでなく、超電導素子等
を形成する場合の高段差を有する基板にも適用可能であ
る。In the above embodiment, a case was described in which four dense patterns were formed using a positive type photoresist film. However, the negative type photoresist film may be used.
One or more resist patterns can be formed. Further, the present invention is applicable not only to a semiconductor substrate but also to a substrate having a high step when forming a superconducting element or the like.
【0032】[0032]
【発明の効果】以上説明したように本発明は、段差を有
する基板上のフォトレジスト膜を、段差の下段面に光学
的正転像(又は反転像)を形成する為の第1の透光領域
と段差の上段面に光学的反転像(又は正転像)を形成す
る為の第2の透光領域とを有するマスクを用い、正転像
と反転像の焦点間距離と段差を一致させる条件で露光す
ることにより、複雑な工程を必要とすることなく、十分
な焦点深度で露光できる為、微細なパターンを精度良く
形成できる。As described above, according to the present invention, the first transparent film for forming the optical normal rotation image (or reverse image) on the lower surface of the step of the photoresist film on the substrate having the step is provided. Using a mask having a region and a second light-transmitting region for forming an optically inverted image (or a normal rotation image) on the upper surface of the step, the inter-focal distance of the normal rotation image and the reverse image and the step are matched. By performing the exposure under the conditions, the exposure can be performed with a sufficient depth of focus without requiring a complicated process, and thus a fine pattern can be accurately formed.
【図1】本発明の第1の実施例を説明する為の半導体チ
ップの断面図。FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.
【図2】第1の実施例における露光時の正転像及び反転
像を示す図。FIG. 2 is a diagram showing a normal image and a reverse image during exposure in the first embodiment.
【図3】レンズの開口数と焦点間距離との関係を示す
図。FIG. 3 is a diagram showing a relationship between a numerical aperture of a lens and a focal length.
【図4】第1の実施例における正転像及び反転像の焦点
位置と光強度比との関係を示す図。FIG. 4 is a diagram showing a relationship between a focus position of a normal image and a reverse image and a light intensity ratio in the first embodiment.
【図5】本発明の第2の実施例を説明する為の半導体チ
ップの断面図。FIG. 5 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
【図6】第2の実施例における露光時の正転像及び反転
像を示す図。FIG. 6 is a diagram showing a normal image and a reverse image during exposure in a second embodiment.
【図7】従来のパターン形成方法を説明する為の半導体
チップの断面図。FIG. 7 is a sectional view of a semiconductor chip for explaining a conventional pattern forming method.
【図8】光強度比を説明する為の光強度分布を示す図。FIG. 8 is a view showing a light intensity distribution for explaining a light intensity ratio.
【図9】従来技術における像の焦点位置と光強度比との
関係を示す図。FIG. 9 is a diagram showing a relationship between a focus position of an image and a light intensity ratio in the related art.
【図10】焦点をずらした場合の像の変化を説明する為
の光強度分布を示す図。FIG. 10 is a diagram showing a light intensity distribution for explaining a change in an image when a focus is shifted.
1,1A シリコン基板 2 段差 2A 下段面 2B 上段面 3 ポジ型フォトレジスト膜 4 マスク 4A,14A 第1の透光領域 4B,14B 第2の透光領域 5 KrFエキシマ光 6A,6B ラインパターン 7 マスク通過後の光強度 8,8A,8B 正転像 9A,9B 反転像 10,10A 焦点位置 11 下段面の光強度比 12 上段面の光強度比 16A,16B スペースパターン 1, 1A Silicon substrate 2 Step 2A Lower surface 2B Upper surface 3 Positive photoresist film 4 Mask 4A, 14A First translucent area 4B, 14B Second translucent area 5 KrF excimer light 6A, 6B Line pattern 7 Mask Light intensity after passing 8, 8A, 8B Forward image 9A, 9B Inverted image 10, 10A Focus position 11 Light intensity ratio of lower stage 12 Light intensity ratio of upper stage 16A, 16B Space pattern
Claims (2)
ト膜を形成する工程と、前記段差の下段面に光学的正転
像(又は反転像)を形成する為の第1の透光領域と前記
段差の上段面に光学的反転像(又は正転像)を形成する
為の第2の透光領域とを有するマスクを用いて前記フォ
トレジスト膜を露光したのち現像し、前記下段面及び前
記上段面に前記フォトレジスト膜からなるパターンを同
時に形成することを特徴とするパターン形成方法。1. A step of forming a photoresist film on a main surface of a substrate having a step, and a first light-transmitting region for forming an optical normal image (or an inverted image) on a lower surface of the step. The photoresist film is exposed and developed using a mask having a second light-transmitting region for forming an optically inverted image (or a normal image) on the upper surface of the step, and then the lower surface and the A pattern forming method, wherein a pattern made of the photoresist film is simultaneously formed on the upper surface.
距離が基板の段差と等しくなる条件で露光する請求項1
記載のパターン形成方法。2. The exposure is performed under the condition that the distance between the focal points of the optical normal image and the optically inverted image is equal to the step of the substrate.
The pattern forming method described in the above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6257807A JP2647022B2 (en) | 1994-10-24 | 1994-10-24 | Pattern formation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6257807A JP2647022B2 (en) | 1994-10-24 | 1994-10-24 | Pattern formation method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08124827A true JPH08124827A (en) | 1996-05-17 |
JP2647022B2 JP2647022B2 (en) | 1997-08-27 |
Family
ID=17311393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6257807A Expired - Lifetime JP2647022B2 (en) | 1994-10-24 | 1994-10-24 | Pattern formation method |
Country Status (1)
Country | Link |
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JP (1) | JP2647022B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2933236A1 (en) * | 2008-06-30 | 2010-01-01 | Soitec Silicon On Insulator | Silicon on insulator substrate for fabricating micro-electronic devices, has supplementary layer placed on one of two regions in front surface of support, where layer has sufficient thickness for burying crystalline defects of support |
US7977705B2 (en) | 2008-06-30 | 2011-07-12 | S.O.I.Tec Silicon On Insulator Technologies | Low-cost substrates having high-resistivity properties and methods for their manufacture |
US8013417B2 (en) | 2008-06-30 | 2011-09-06 | S.O.I.T.ec Silicon on Insulator Technologies | Low cost substrates and method of forming such substrates |
US8035163B2 (en) | 2008-06-30 | 2011-10-11 | S.O.I.Tec Silicon On Insulator Technologies | Low-cost double-structure substrates and methods for their manufacture |
-
1994
- 1994-10-24 JP JP6257807A patent/JP2647022B2/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2933236A1 (en) * | 2008-06-30 | 2010-01-01 | Soitec Silicon On Insulator | Silicon on insulator substrate for fabricating micro-electronic devices, has supplementary layer placed on one of two regions in front surface of support, where layer has sufficient thickness for burying crystalline defects of support |
US7977705B2 (en) | 2008-06-30 | 2011-07-12 | S.O.I.Tec Silicon On Insulator Technologies | Low-cost substrates having high-resistivity properties and methods for their manufacture |
US8013417B2 (en) | 2008-06-30 | 2011-09-06 | S.O.I.T.ec Silicon on Insulator Technologies | Low cost substrates and method of forming such substrates |
US8035163B2 (en) | 2008-06-30 | 2011-10-11 | S.O.I.Tec Silicon On Insulator Technologies | Low-cost double-structure substrates and methods for their manufacture |
Also Published As
Publication number | Publication date |
---|---|
JP2647022B2 (en) | 1997-08-27 |
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